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[people/ms/u-boot.git] / include / configs / lwmon5.h
1 /*
2 * (C) Copyright 2007-2013
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 /*
9 * lwmon5.h - configuration for lwmon5 board
10 */
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 /*
15 * Liebherr extra version info
16 */
17 #define CONFIG_IDENT_STRING " - v2.0"
18
19 /*
20 * High Level Configuration Options
21 */
22 #define CONFIG_LWMON5 1 /* Board is lwmon5 */
23 #define CONFIG_440EPX 1 /* Specific PPC440EPx */
24 #define CONFIG_440 1 /* ... PPC440 family */
25
26 #define CONFIG_SYS_GENERIC_BOARD
27
28 #ifdef CONFIG_LCD4_LWMON5
29 #define CONFIG_SYS_TEXT_BASE 0x01000000 /* SPL U-Boot TEXT_BASE */
30 #define CONFIG_HOSTNAME lcd4_lwmon5
31 #else
32 #define CONFIG_SYS_TEXT_BASE 0xFFF80000
33 #define CONFIG_HOSTNAME lwmon5
34 #endif
35
36 #define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
37
38 #define CONFIG_4xx_DCACHE /* enable cache in SDRAM */
39
40 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */
41 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
42 #define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */
43 #define CONFIG_MISC_INIT_R /* Call misc_init_r */
44 #define CONFIG_BOARD_RESET /* Call board_reset */
45
46 /*
47 * Base addresses -- Note these are effective addresses where the
48 * actual resources get mapped (not physical addresses)
49 */
50 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */
51 #define CONFIG_SYS_MONITOR_LEN 0x80000
52 #define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */
53
54 #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
55 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
56 #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
57 #define CONFIG_SYS_LIME_BASE_0 0xc0000000
58 #define CONFIG_SYS_LIME_BASE_1 0xc1000000
59 #define CONFIG_SYS_LIME_BASE_2 0xc2000000
60 #define CONFIG_SYS_LIME_BASE_3 0xc3000000
61 #define CONFIG_SYS_FPGA_BASE_0 0xc4000000
62 #define CONFIG_SYS_FPGA_BASE_1 0xc4200000
63 #define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
64 #define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
65 #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
66 #define CONFIG_SYS_PCI_MEMBASE1 (CONFIG_SYS_PCI_MEMBASE + 0x10000000)
67 #define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000)
68 #define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000)
69
70 #ifndef CONFIG_LCD4_LWMON5
71 #define CONFIG_SYS_USB2D0_BASE 0xe0000100
72 #define CONFIG_SYS_USB_DEVICE 0xe0000000
73 #define CONFIG_SYS_USB_HOST 0xe0000400
74 #endif
75
76 /*
77 * Initial RAM & stack pointer
78 *
79 * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
80 * the POST_WORD from OCM to a 440EPx register that preserves it's
81 * content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
82 * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
83 */
84 #ifndef CONFIG_LCD4_LWMON5
85 #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
86 #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
87 #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
88 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
89 GENERATED_GBL_DATA_SIZE)
90 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
91 #else
92 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE
93 #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
94 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
95 GENERATED_GBL_DATA_SIZE)
96 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
97 #endif
98 /* unused GPT0 COMP reg */
99 #define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
100 #define CONFIG_SYS_OCM_SIZE (16 << 10)
101 /* 440EPx errata CHIP 11: don't use last 4kbytes */
102 #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10)
103
104 /* Additional registers for watchdog timer post test */
105 #define CONFIG_SYS_WATCHDOG_TIME_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2)
106 #define CONFIG_SYS_WATCHDOG_FLAGS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1)
107 #define CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
108 #define CONFIG_SYS_OCM_STATUS_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
109 #define CONFIG_SYS_WATCHDOG_MAGIC 0x12480000
110 #define CONFIG_SYS_WATCHDOG_MAGIC_MASK 0xFFFF0000
111 #define CONFIG_SYS_DSPIC_TEST_MASK 0x00000001
112 #define CONFIG_SYS_OCM_STATUS_OK 0x00009A00
113 #define CONFIG_SYS_OCM_STATUS_FAIL 0x0000A300
114 #define CONFIG_SYS_OCM_STATUS_MASK 0x0000FF00
115
116 /*
117 * Serial Port
118 */
119 #define CONFIG_CONS_INDEX 2 /* Use UART1 */
120 #define CONFIG_SYS_NS16550
121 #define CONFIG_SYS_NS16550_SERIAL
122 #define CONFIG_SYS_NS16550_REG_SIZE 1
123 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
124 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */
125 #define CONFIG_BAUDRATE 115200
126
127 #define CONFIG_SYS_BAUDRATE_TABLE \
128 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
129
130 /*
131 * Environment
132 */
133 #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
134
135 /*
136 * FLASH related
137 */
138 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
139 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
140
141 #define CONFIG_SYS_FLASH0 0xFC000000
142 #define CONFIG_SYS_FLASH1 0xF8000000
143 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
144
145 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 /* max number of memory banks */
146 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
147
148 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
149 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
150
151 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
152 #define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */
153
154 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
155 #define CONFIG_SYS_FLASH_QUIET_TEST /* don't warn upon unknown flash */
156
157 #define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
158 #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE)
159 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
160
161 /* Address and size of Redundant Environment Sector */
162 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
163 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
164
165 /*
166 * DDR SDRAM
167 */
168 #define CONFIG_SYS_MBYTES_SDRAM 256
169 #define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
170 #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
171 #ifndef CONFIG_LCD4_LWMON5
172 #define CONFIG_DDR_ECC /* enable ECC */
173 #endif
174
175 #ifndef CONFIG_LCD4_LWMON5
176 /* POST support */
177 #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
178 CONFIG_SYS_POST_CPU | \
179 CONFIG_SYS_POST_ECC | \
180 CONFIG_SYS_POST_ETHER | \
181 CONFIG_SYS_POST_FPU | \
182 CONFIG_SYS_POST_I2C | \
183 CONFIG_SYS_POST_MEMORY | \
184 CONFIG_SYS_POST_OCM | \
185 CONFIG_SYS_POST_RTC | \
186 CONFIG_SYS_POST_SPR | \
187 CONFIG_SYS_POST_UART | \
188 CONFIG_SYS_POST_SYSMON | \
189 CONFIG_SYS_POST_WATCHDOG | \
190 CONFIG_SYS_POST_DSP | \
191 CONFIG_SYS_POST_BSPEC1 | \
192 CONFIG_SYS_POST_BSPEC2 | \
193 CONFIG_SYS_POST_BSPEC3 | \
194 CONFIG_SYS_POST_BSPEC4 | \
195 CONFIG_SYS_POST_BSPEC5)
196
197 /* Define here the base-addresses of the UARTs to test in POST */
198 #define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
199 CONFIG_SYS_NS16550_COM2 }
200
201 #define CONFIG_POST_UART { \
202 "UART test", \
203 "uart", \
204 "This test verifies the UART operation.", \
205 POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL, \
206 &uart_post_test, \
207 NULL, \
208 NULL, \
209 CONFIG_SYS_POST_UART \
210 }
211
212 #define CONFIG_POST_WATCHDOG { \
213 "Watchdog timer test", \
214 "watchdog", \
215 "This test checks the watchdog timer.", \
216 POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \
217 &lwmon5_watchdog_post_test, \
218 NULL, \
219 NULL, \
220 CONFIG_SYS_POST_WATCHDOG \
221 }
222
223 #define CONFIG_POST_BSPEC1 { \
224 "dsPIC init test", \
225 "dspic_init", \
226 "This test returns result of dsPIC READY test run earlier.", \
227 POST_RAM | POST_ALWAYS, \
228 &dspic_init_post_test, \
229 NULL, \
230 NULL, \
231 CONFIG_SYS_POST_BSPEC1 \
232 }
233
234 #define CONFIG_POST_BSPEC2 { \
235 "dsPIC test", \
236 "dspic", \
237 "This test gets result of dsPIC POST and dsPIC version.", \
238 POST_RAM | POST_ALWAYS, \
239 &dspic_post_test, \
240 NULL, \
241 NULL, \
242 CONFIG_SYS_POST_BSPEC2 \
243 }
244
245 #define CONFIG_POST_BSPEC3 { \
246 "FPGA test", \
247 "fpga", \
248 "This test checks FPGA registers and memory.", \
249 POST_RAM | POST_ALWAYS | POST_MANUAL, \
250 &fpga_post_test, \
251 NULL, \
252 NULL, \
253 CONFIG_SYS_POST_BSPEC3 \
254 }
255
256 #define CONFIG_POST_BSPEC4 { \
257 "GDC test", \
258 "gdc", \
259 "This test checks GDC registers and memory.", \
260 POST_RAM | POST_ALWAYS | POST_MANUAL,\
261 &gdc_post_test, \
262 NULL, \
263 NULL, \
264 CONFIG_SYS_POST_BSPEC4 \
265 }
266
267 #define CONFIG_POST_BSPEC5 { \
268 "SYSMON1 test", \
269 "sysmon1", \
270 "This test checks GPIO_62_EPX pin indicating power failure.", \
271 POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \
272 &sysmon1_post_test, \
273 NULL, \
274 NULL, \
275 CONFIG_SYS_POST_BSPEC5 \
276 }
277
278 #define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
279 #define CONFIG_LOGBUFFER
280 /* Reserve GPT0_COMP1-COMP5 for logbuffer header */
281 #define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1)
282 #define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE)
283 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
284 #endif
285
286 /*
287 * I2C
288 */
289 #define CONFIG_SYS_I2C
290 #define CONFIG_SYS_I2C_PPC4XX
291 #define CONFIG_SYS_I2C_PPC4XX_CH0
292 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
293 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
294
295 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* RTC */
296 #define CONFIG_SYS_I2C_EEPROM_CPU_ADDR 0x52 /* EEPROM (CPU Modul) */
297 #define CONFIG_SYS_I2C_EEPROM_MB_ADDR 0x53 /* EEPROM AT24C128 (MainBoard) */
298 #define CONFIG_SYS_I2C_DSPIC_ADDR 0x54 /* dsPIC */
299 #define CONFIG_SYS_I2C_DSPIC_2_ADDR 0x55 /* dsPIC */
300 #define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR 0x56 /* dsPIC */
301 #define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* dsPIC */
302
303 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
304 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */
305 /* 64 byte page write mode using*/
306 /* last 6 bits of the address */
307 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
308 #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
309
310 #define CONFIG_RTC_PCF8563 /* enable Philips PCF8563 RTC */
311 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
312 #define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
313 #define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */
314
315 #define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_RTC_ADDR, \
316 CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\
317 CONFIG_SYS_I2C_EEPROM_MB_ADDR, \
318 CONFIG_SYS_I2C_DSPIC_ADDR, \
319 CONFIG_SYS_I2C_DSPIC_2_ADDR, \
320 CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\
321 CONFIG_SYS_I2C_DSPIC_IO_ADDR }
322
323 /*
324 * Pass open firmware flat tree
325 */
326 #define CONFIG_OF_LIBFDT
327 #define CONFIG_OF_BOARD_SETUP
328 /* Update size in "reg" property of NOR FLASH device tree nodes */
329 #define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
330
331 #define CONFIG_FIT /* enable FIT image support */
332
333 #define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
334
335 #define CONFIG_PREBOOT "setenv bootdelay 15"
336
337 #undef CONFIG_BOOTARGS
338
339 #define CONFIG_EXTRA_ENV_SETTINGS \
340 "hostname=lwmon5\0" \
341 "netdev=eth0\0" \
342 "unlock=yes\0" \
343 "logversion=2\0" \
344 "nfsargs=setenv bootargs root=/dev/nfs rw " \
345 "nfsroot=${serverip}:${rootpath}\0" \
346 "ramargs=setenv bootargs root=/dev/ram rw\0" \
347 "addip=setenv bootargs ${bootargs} " \
348 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
349 ":${hostname}:${netdev}:off panic=1\0" \
350 "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
351 "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
352 "flash_nfs=run nfsargs addip addtty addmisc;" \
353 "bootm ${kernel_addr}\0" \
354 "flash_self=run ramargs addip addtty addmisc;" \
355 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
356 "net_nfs=tftp 200000 ${bootfile};" \
357 "run nfsargs addip addtty addmisc;bootm\0" \
358 "rootpath=/opt/eldk/ppc_4xxFP\0" \
359 "bootfile=/tftpboot/lwmon5/uImage\0" \
360 "kernel_addr=FC000000\0" \
361 "ramdisk_addr=FC180000\0" \
362 "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
363 "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \
364 "cp.b 200000 FFF80000 80000\0" \
365 "upd=run load update\0" \
366 "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \
367 "autoscr 200000\0" \
368 ""
369 #define CONFIG_BOOTCOMMAND "run flash_self"
370
371 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
372
373 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
374 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
375
376 #define CONFIG_PPC4xx_EMAC
377 #define CONFIG_IBM_EMAC4_V4 1
378 #define CONFIG_MII 1 /* MII PHY management */
379 #define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */
380
381 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
382 #define CONFIG_PHY_RESET_DELAY 300
383
384 #define CONFIG_HAS_ETH0
385 #define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
386
387 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
388 #define CONFIG_PHY1_ADDR 1
389
390 /* Video console */
391 #define CONFIG_VIDEO
392 #define CONFIG_VIDEO_MB862xx
393 #define CONFIG_VIDEO_MB862xx_ACCEL
394 #define CONFIG_CFB_CONSOLE
395 #define CONFIG_VIDEO_LOGO
396 #define CONFIG_CONSOLE_EXTRA_INFO
397 #define VIDEO_FB_16BPP_PIXEL_SWAP
398 #define VIDEO_FB_16BPP_WORD_SWAP
399
400 #define CONFIG_VGA_AS_SINGLE_DEVICE
401 #define CONFIG_VIDEO_SW_CURSOR
402 #define CONFIG_SPLASH_SCREEN
403
404 #ifndef CONFIG_LCD4_LWMON5
405 /*
406 * USB/EHCI
407 */
408 #define CONFIG_USB_EHCI /* Enable EHCI USB support */
409 #define CONFIG_USB_EHCI_PPC4XX /* on PPC4xx platform */
410 #define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
411 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
412 #define CONFIG_EHCI_DESC_BIG_ENDIAN
413 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
414 #define CONFIG_USB_STORAGE
415
416 /* Partitions */
417 #define CONFIG_MAC_PARTITION
418 #define CONFIG_DOS_PARTITION
419 #define CONFIG_ISO_PARTITION
420 #endif
421
422 /*
423 * BOOTP options
424 */
425 #define CONFIG_BOOTP_BOOTFILESIZE
426 #define CONFIG_BOOTP_BOOTPATH
427 #define CONFIG_BOOTP_GATEWAY
428 #define CONFIG_BOOTP_HOSTNAME
429
430 /*
431 * Command line configuration.
432 */
433 #define CONFIG_CMD_ASKENV
434 #define CONFIG_CMD_DATE
435 #define CONFIG_CMD_DHCP
436 #define CONFIG_CMD_DIAG
437 #define CONFIG_CMD_EEPROM
438 #define CONFIG_CMD_ELF
439 #define CONFIG_CMD_FAT
440 #define CONFIG_CMD_I2C
441 #define CONFIG_CMD_IRQ
442 #define CONFIG_CMD_MII
443 #define CONFIG_CMD_PING
444 #define CONFIG_CMD_REGINFO
445 #define CONFIG_CMD_SDRAM
446
447 #ifdef CONFIG_VIDEO
448 #define CONFIG_CMD_BMP
449 #endif
450
451 #ifndef CONFIG_LCD4_LWMON5
452 #ifdef CONFIG_440EPX
453 #define CONFIG_CMD_USB
454 #endif
455 #endif
456
457 /*
458 * Miscellaneous configurable options
459 */
460 #define CONFIG_SUPPORT_VFAT
461
462 #define CONFIG_SYS_LONGHELP /* undef to save memory */
463
464 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
465
466 #if defined(CONFIG_CMD_KGDB)
467 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
468 #else
469 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
470 #endif
471 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
472 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
473 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
474
475 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
476 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
477
478 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
479 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
480
481 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
482 #define CONFIG_LOOPW 1 /* enable loopw command */
483 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
484 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
485
486 #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
487
488 #ifndef CONFIG_LCD4_LWMON5
489 #ifndef DEBUG
490 #define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
491 #endif
492 #define CONFIG_WD_PERIOD 40000 /* in usec */
493 #define CONFIG_WD_MAX_RATE 66600 /* in ticks */
494 #endif
495
496 /*
497 * For booting Linux, the board info and command line data
498 * have to be in the first 16 MB of memory, since this is
499 * the maximum mapped by the 40x Linux kernel during initialization.
500 */
501 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */
502 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
503
504 /*
505 * External Bus Controller (EBC) Setup
506 */
507 #define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
508
509 /* Memory Bank 0 (NOR-FLASH) initialization */
510 #define CONFIG_SYS_EBC_PB0AP 0x03000280
511 #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xfc000)
512
513 /* Memory Bank 1 (Lime) initialization */
514 #define CONFIG_SYS_EBC_PB1AP 0x01004380
515 #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xbc000)
516
517 /* Memory Bank 2 (FPGA) initialization */
518 #define CONFIG_SYS_EBC_PB2AP 0x01004400
519 #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE_0 | 0x1c000)
520
521 /* Memory Bank 3 (FPGA2) initialization */
522 #define CONFIG_SYS_EBC_PB3AP 0x01004400
523 #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FPGA_BASE_1 | 0x1c000)
524
525 #define CONFIG_SYS_EBC_CFG 0xb8400000
526
527 /*
528 * Graphics (Fujitsu Lime)
529 */
530 /* SDRAM Clock frequency adjustment register */
531 #define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038
532 #if 1 /* 133MHz is not tested enough, use 100MHz for now */
533 /* Lime Clock frequency is to set 100MHz */
534 #define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000
535 #else
536 /* Lime Clock frequency for 133MHz */
537 #define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000
538 #endif
539
540 /* SDRAM Parameter register */
541 #define CONFIG_SYS_LIME_MMR 0xC1FCFFFC
542 /*
543 * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
544 * and pixel flare on display when 133MHz was configured. According to
545 * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed
546 * Grade
547 */
548 #ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
549 #define CONFIG_SYS_MB862xx_MMR 0x414FB7F3
550 #define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ
551 #else
552 #define CONFIG_SYS_MB862xx_MMR 0x414FB7F2
553 #define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ
554 #endif
555
556 /*
557 * GPIO Setup
558 */
559 #define CONFIG_SYS_GPIO_PHY1_RST 12
560 #define CONFIG_SYS_GPIO_FLASH_WP 14
561 #define CONFIG_SYS_GPIO_PHY0_RST 22
562 #define CONFIG_SYS_GPIO_PERM_VOLT_FEED 49
563 #define CONFIG_SYS_GPIO_DSPIC_READY 51
564 #define CONFIG_SYS_GPIO_CAN_ENABLE 53
565 #define CONFIG_SYS_GPIO_LSB_ENABLE 54
566 #define CONFIG_SYS_GPIO_EEPROM_EXT_WP 55
567 #define CONFIG_SYS_GPIO_HIGHSIDE 56
568 #define CONFIG_SYS_GPIO_EEPROM_INT_WP 57
569 #define CONFIG_SYS_GPIO_BOARD_RESET 58
570 #define CONFIG_SYS_GPIO_LIME_S 59
571 #define CONFIG_SYS_GPIO_LIME_RST 60
572 #define CONFIG_SYS_GPIO_SYSMON_STATUS 62
573 #define CONFIG_SYS_GPIO_WATCHDOG 63
574
575 /* On LCD4, GPIO49 has to be configured to 0 instead of 1 */
576 #ifdef CONFIG_LCD4_LWMON5
577 #define GPIO49_VAL 0
578 #else
579 #define GPIO49_VAL 1
580 #endif
581
582 /*
583 * PPC440 GPIO Configuration
584 */
585 #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
586 { \
587 /* GPIO Core 0 */ \
588 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
589 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
590 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
591 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
592 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
593 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
594 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
595 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
596 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
597 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
598 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
599 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
600 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
601 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
602 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
603 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \
604 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
605 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
606 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
607 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \
608 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
609 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
610 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
611 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
612 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \
613 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \
614 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
615 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
616 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
617 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
618 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
619 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
620 }, \
621 { \
622 /* GPIO Core 1 */ \
623 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
624 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
625 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
626 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
627 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
628 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
629 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
630 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
631 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
632 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
633 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
634 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
635 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
636 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
637 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
638 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
639 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
640 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO49_VAL}, /* GPIO49 Unselect via TraceSelect Bit */ \
641 {GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
642 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
643 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
644 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
645 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
646 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
647 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
648 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \
649 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
650 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
651 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
652 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
653 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
654 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
655 } \
656 }
657
658 #if defined(CONFIG_CMD_KGDB)
659 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
660 #endif
661
662 /*
663 * SPL related defines
664 */
665 #ifdef CONFIG_LCD4_LWMON5
666 #define CONFIG_SPL_FRAMEWORK
667 #define CONFIG_SPL_BOARD_INIT
668 #define CONFIG_SPL_NOR_SUPPORT
669 #define CONFIG_SPL_TEXT_BASE 0xffff0000 /* last 64 KiB for SPL */
670 #define CONFIG_SYS_SPL_MAX_LEN (64 << 10)
671 #define CONFIG_UBOOT_PAD_TO 458752 /* decimal for 'dd' */
672 #define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
673 #define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
674 #define CONFIG_SPL_SERIAL_SUPPORT
675
676 /* Place BSS for SPL near end of SDRAM */
677 #define CONFIG_SPL_BSS_START_ADDR ((256 - 1) << 20)
678 #define CONFIG_SPL_BSS_MAX_SIZE (64 << 10)
679
680 #define CONFIG_SPL_OS_BOOT
681 /* Place patched DT blob (fdt) at this address */
682 #define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000
683
684 #define CONFIG_SPL_TARGET "u-boot-img-spl-at-end.bin"
685
686 /* Settings for real U-Boot to be loaded from NOR flash */
687 #define CONFIG_SYS_UBOOT_BASE (-CONFIG_SYS_MONITOR_LEN)
688 #define CONFIG_SYS_UBOOT_START 0x01002100
689
690 #define CONFIG_SYS_OS_BASE 0xf8000000
691 #define CONFIG_SYS_FDT_BASE 0xf87c0000
692 #endif
693
694 #endif /* __CONFIG_H */
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