include/configs/lwmon5.h

   1 /*
   2  * (C) Copyright 2007-2013
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * lwmon5.h - configuration for lwmon5 board
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * Liebherr extra version info
  16  */
  17 #define CONFIG_IDENT_STRING     " - v2.0"
  18
  19 /*
  20  * High Level Configuration Options
  21  */
  22 #define CONFIG_LWMON5           1               /* Board is lwmon5      */
  23 #define CONFIG_440EPX           1               /* Specific PPC440EPx   */
  24 #define CONFIG_440              1               /* ... PPC440 family    */
  25
  26 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  27 #define CONFIG_HOSTNAME         lwmon5
  28
  29 #define CONFIG_SYS_CLK_FREQ     33300000        /* external freq to pll */
  30
  31 #define CONFIG_4xx_DCACHE               /* enable cache in SDRAM        */
  32
  33 #define CONFIG_BOARD_EARLY_INIT_F       /* Call board_early_init_f      */
  34 #define CONFIG_BOARD_EARLY_INIT_R       /* Call board_early_init_r      */
  35 #define CONFIG_BOARD_POSTCLK_INIT       /* Call board_postclk_init      */
  36 #define CONFIG_MISC_INIT_R              /* Call misc_init_r             */
  37 #define CONFIG_BOARD_RESET              /* Call board_reset             */
  38
  39 /*
  40  * Base addresses -- Note these are effective addresses where the
  41  * actual resources get mapped (not physical addresses)
  42  */
  43 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* Start of U-Boot      */
  44 #define CONFIG_SYS_MONITOR_LEN          0x80000
  45 #define CONFIG_SYS_MALLOC_LEN           (1 << 20)       /* Reserved for malloc  */
  46
  47 #define CONFIG_SYS_BOOT_BASE_ADDR       0xf0000000
  48 #define CONFIG_SYS_SDRAM_BASE           0x00000000      /* _must_ be 0          */
  49 #define CONFIG_SYS_FLASH_BASE           0xf8000000      /* start of FLASH       */
  50 #define CONFIG_SYS_LIME_BASE_0          0xc0000000
  51 #define CONFIG_SYS_LIME_BASE_1          0xc1000000
  52 #define CONFIG_SYS_LIME_BASE_2          0xc2000000
  53 #define CONFIG_SYS_LIME_BASE_3          0xc3000000
  54 #define CONFIG_SYS_FPGA_BASE_0          0xc4000000
  55 #define CONFIG_SYS_FPGA_BASE_1          0xc4200000
  56 #define CONFIG_SYS_OCM_BASE             0xe0010000      /* ocm                  */
  57 #define CONFIG_SYS_PCI_BASE             0xe0000000      /* Internal PCI regs    */
  58 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped pci memory    */
  59 #define CONFIG_SYS_PCI_MEMBASE1         (CONFIG_SYS_PCI_MEMBASE  + 0x10000000)
  60 #define CONFIG_SYS_PCI_MEMBASE2         (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000)
  61 #define CONFIG_SYS_PCI_MEMBASE3         (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000)
  62
  63 #define CONFIG_SYS_USB2D0_BASE          0xe0000100
  64 #define CONFIG_SYS_USB_DEVICE           0xe0000000
  65 #define CONFIG_SYS_USB_HOST             0xe0000400
  66
  67 /*
  68  * Initial RAM & stack pointer
  69  *
  70  * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
  71  * the POST_WORD from OCM to a 440EPx register that preserves it's
  72  * content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
  73  * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
  74  */
  75 #define CONFIG_SYS_INIT_RAM_DCACHE      1               /* d-cache as init ram  */
  76 #define CONFIG_SYS_INIT_RAM_ADDR        0x70000000              /* DCache       */
  77 #define CONFIG_SYS_INIT_RAM_SIZE                (4 << 10)
  78 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
  79                                          GENERATED_GBL_DATA_SIZE)
  80 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  81
  82 /* unused GPT0 COMP reg */
  83 #define CONFIG_SYS_POST_WORD_ADDR       (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
  84 #define CONFIG_SYS_OCM_SIZE             (16 << 10)
  85 /* 440EPx errata CHIP 11: don't use last 4kbytes */
  86 #define CONFIG_SYS_MEM_TOP_HIDE         (4 << 10)
  87
  88 /* Additional registers for watchdog timer post test */
  89 #define CONFIG_SYS_WATCHDOG_TIME_ADDR   (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2)
  90 #define CONFIG_SYS_WATCHDOG_FLAGS_ADDR  (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1)
  91 #define CONFIG_SYS_DSPIC_TEST_ADDR      CONFIG_SYS_WATCHDOG_FLAGS_ADDR
  92 #define CONFIG_SYS_OCM_STATUS_ADDR      CONFIG_SYS_WATCHDOG_FLAGS_ADDR
  93 #define CONFIG_SYS_WATCHDOG_MAGIC       0x12480000
  94 #define CONFIG_SYS_WATCHDOG_MAGIC_MASK  0xFFFF0000
  95 #define CONFIG_SYS_DSPIC_TEST_MASK      0x00000001
  96 #define CONFIG_SYS_OCM_STATUS_OK        0x00009A00
  97 #define CONFIG_SYS_OCM_STATUS_FAIL      0x0000A300
  98 #define CONFIG_SYS_OCM_STATUS_MASK      0x0000FF00
  99
 100 /*
 101  * Serial Port
 102  */
 103 #define CONFIG_CONS_INDEX       2       /* Use UART1                    */
 104 #define CONFIG_SYS_NS16550_SERIAL
 105 #define CONFIG_SYS_NS16550_REG_SIZE     1
 106 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 107 #undef CONFIG_SYS_EXT_SERIAL_CLOCK              /* no external clock provided   */
 108 #define CONFIG_BAUDRATE         115200
 109
 110 #define CONFIG_SYS_BAUDRATE_TABLE                                               \
 111         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 112
 113 /*
 114  * Environment
 115  */
 116 #define CONFIG_ENV_IS_IN_FLASH          /* use FLASH for environment vars       */
 117
 118 /*
 119  * FLASH related
 120  */
 121 #define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
 122 #define CONFIG_FLASH_CFI_DRIVER                 /* Use common CFI driver        */
 123
 124 #define CONFIG_SYS_FLASH0               0xFC000000
 125 #define CONFIG_SYS_FLASH1               0xF8000000
 126 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
 127
 128 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2     /* max number of memory banks           */
 129 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 130
 131 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 132 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 133
 134 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       /* use buffered writes (20x faster)     */
 135 #define CONFIG_SYS_FLASH_PROTECTION             /* use hardware flash protection        */
 136
 137 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 138 #define CONFIG_SYS_FLASH_QUIET_TEST             /* don't warn upon unknown flash        */
 139
 140 #define CONFIG_ENV_SECT_SIZE    0x40000 /* size of one complete sector          */
 141 #define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE)
 142 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 143
 144 /* Address and size of Redundant Environment Sector     */
 145 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 146 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 147
 148 /*
 149  * DDR SDRAM
 150  */
 151 #define CONFIG_SYS_MBYTES_SDRAM         256
 152 #define CONFIG_SYS_DDR_CACHED_ADDR      0x40000000      /* setup 2nd TLB cached here    */
 153 #define CONFIG_DDR_DATA_EYE                     /* use DDR2 optimization        */
 154 #define CONFIG_DDR_ECC                          /* enable ECC                   */
 155
 156 /* POST support */
 157 #define CONFIG_POST             (CONFIG_SYS_POST_CACHE          | \
 158                                  CONFIG_SYS_POST_CPU            | \
 159                                  CONFIG_SYS_POST_ECC            | \
 160                                  CONFIG_SYS_POST_ETHER          | \
 161                                  CONFIG_SYS_POST_FPU            | \
 162                                  CONFIG_SYS_POST_I2C            | \
 163                                  CONFIG_SYS_POST_MEMORY         | \
 164                                  CONFIG_SYS_POST_OCM            | \
 165                                  CONFIG_SYS_POST_RTC            | \
 166                                  CONFIG_SYS_POST_SPR            | \
 167                                  CONFIG_SYS_POST_UART           | \
 168                                  CONFIG_SYS_POST_SYSMON         | \
 169                                  CONFIG_SYS_POST_WATCHDOG       | \
 170                                  CONFIG_SYS_POST_DSP            | \
 171                                  CONFIG_SYS_POST_BSPEC1         | \
 172                                  CONFIG_SYS_POST_BSPEC2         | \
 173                                  CONFIG_SYS_POST_BSPEC3         | \
 174                                  CONFIG_SYS_POST_BSPEC4         | \
 175                                  CONFIG_SYS_POST_BSPEC5)
 176
 177 /* Define here the base-addresses of the UARTs to test in POST */
 178 #define CONFIG_SYS_POST_UART_TABLE      { CONFIG_SYS_NS16550_COM1, \
 179                         CONFIG_SYS_NS16550_COM2 }
 180
 181 #define CONFIG_POST_UART  {                             \
 182         "UART test",                                    \
 183         "uart",                                         \
 184         "This test verifies the UART operation.",       \
 185         POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL,   \
 186         &uart_post_test,                                \
 187         NULL,                                           \
 188         NULL,                                           \
 189         CONFIG_SYS_POST_UART                            \
 190         }
 191
 192 #define CONFIG_POST_WATCHDOG  {                         \
 193         "Watchdog timer test",                          \
 194         "watchdog",                                     \
 195         "This test checks the watchdog timer.",         \
 196         POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \
 197         &lwmon5_watchdog_post_test,                     \
 198         NULL,                                           \
 199         NULL,                                           \
 200         CONFIG_SYS_POST_WATCHDOG                        \
 201         }
 202
 203 #define CONFIG_POST_BSPEC1    {                         \
 204         "dsPIC init test",                              \
 205         "dspic_init",                                   \
 206         "This test returns result of dsPIC READY test run earlier.",    \
 207         POST_RAM | POST_ALWAYS,                         \
 208         &dspic_init_post_test,                          \
 209         NULL,                                           \
 210         NULL,                                           \
 211         CONFIG_SYS_POST_BSPEC1                          \
 212         }
 213
 214 #define CONFIG_POST_BSPEC2    {                         \
 215         "dsPIC test",                                   \
 216         "dspic",                                        \
 217         "This test gets result of dsPIC POST and dsPIC version.",       \
 218         POST_RAM | POST_ALWAYS,                         \
 219         &dspic_post_test,                               \
 220         NULL,                                           \
 221         NULL,                                           \
 222         CONFIG_SYS_POST_BSPEC2                          \
 223         }
 224
 225 #define CONFIG_POST_BSPEC3    {                         \
 226         "FPGA test",                                    \
 227         "fpga",                                         \
 228         "This test checks FPGA registers and memory.",  \
 229         POST_RAM | POST_ALWAYS | POST_MANUAL,           \
 230         &fpga_post_test,                                \
 231         NULL,                                           \
 232         NULL,                                           \
 233         CONFIG_SYS_POST_BSPEC3                          \
 234         }
 235
 236 #define CONFIG_POST_BSPEC4    {                         \
 237         "GDC test",                                     \
 238         "gdc",                                          \
 239         "This test checks GDC registers and memory.",   \
 240         POST_RAM | POST_ALWAYS | POST_MANUAL,\
 241         &gdc_post_test,                                 \
 242         NULL,                                           \
 243         NULL,                                           \
 244         CONFIG_SYS_POST_BSPEC4                          \
 245         }
 246
 247 #define CONFIG_POST_BSPEC5    {                         \
 248         "SYSMON1 test",                                 \
 249         "sysmon1",                                      \
 250         "This test checks GPIO_62_EPX pin indicating power failure.",   \
 251         POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST,   \
 252         &sysmon1_post_test,                             \
 253         NULL,                                           \
 254         NULL,                                           \
 255         CONFIG_SYS_POST_BSPEC5                          \
 256         }
 257
 258 #define CONFIG_SYS_POST_CACHE_ADDR      0x7fff0000 /* free virtual address      */
 259 #define CONFIG_LOGBUFFER
 260 /* Reserve GPT0_COMP1-COMP5 for logbuffer header */
 261 #define CONFIG_ALT_LH_ADDR      (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1)
 262 #define CONFIG_ALT_LB_ADDR      (CONFIG_SYS_OCM_BASE)
 263 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
 264
 265 /*
 266  * I2C
 267  */
 268 #define CONFIG_SYS_I2C
 269 #define CONFIG_SYS_I2C_PPC4XX
 270 #define CONFIG_SYS_I2C_PPC4XX_CH0
 271 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           100000
 272 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 273
 274 #define CONFIG_SYS_I2C_RTC_ADDR 0x51    /* RTC                          */
 275 #define CONFIG_SYS_I2C_EEPROM_CPU_ADDR  0x52    /* EEPROM          (CPU Modul)  */
 276 #define CONFIG_SYS_I2C_EEPROM_MB_ADDR   0x53    /* EEPROM AT24C128 (MainBoard)  */
 277 #define CONFIG_SYS_I2C_DSPIC_ADDR       0x54    /* dsPIC                        */
 278 #define CONFIG_SYS_I2C_DSPIC_2_ADDR     0x55    /* dsPIC                        */
 279 #define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR  0x56    /* dsPIC                        */
 280 #define CONFIG_SYS_I2C_DSPIC_IO_ADDR    0x57    /* dsPIC                        */
 281
 282 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2        /* Bytes of address             */
 283 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6     /* The Atmel AT24C128 has       */
 284                                         /* 64 byte page write mode using*/
 285                                         /* last 6 bits of the address   */
 286 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 287 #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
 288
 289 #define CONFIG_RTC_PCF8563                      /* enable Philips PCF8563 RTC   */
 290 #define CONFIG_SYS_I2C_RTC_ADDR         0x51    /* Philips PCF8563 RTC address  */
 291 #define CONFIG_SYS_I2C_KEYBD_ADDR       0x56    /* PIC LWE keyboard             */
 292 #define CONFIG_SYS_I2C_DSPIC_IO_ADDR    0x57    /* PIC I/O addr               */
 293
 294 #define CONFIG_SYS_POST_I2C_ADDRS       {CONFIG_SYS_I2C_RTC_ADDR,       \
 295                                          CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\
 296                                          CONFIG_SYS_I2C_EEPROM_MB_ADDR, \
 297                                          CONFIG_SYS_I2C_DSPIC_ADDR,     \
 298                                          CONFIG_SYS_I2C_DSPIC_2_ADDR,   \
 299                                          CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\
 300                                          CONFIG_SYS_I2C_DSPIC_IO_ADDR }
 301
 302 /* Update size in "reg" property of NOR FLASH device tree nodes */
 303 #define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
 304
 305 #define CONFIG_POST_KEY_MAGIC   "3C+3E" /* press F3 + F5 keys to force POST */
 306
 307 #define CONFIG_PREBOOT          "setenv bootdelay 15"
 308
 309 #undef  CONFIG_BOOTARGS
 310
 311 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 312         "hostname=lwmon5\0"                                             \
 313         "netdev=eth0\0"                                                 \
 314         "unlock=yes\0"                                                  \
 315         "logversion=2\0"                                                \
 316         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 317                 "nfsroot=${serverip}:${rootpath}\0"                     \
 318         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 319         "addip=setenv bootargs ${bootargs} "                            \
 320                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 321                 ":${hostname}:${netdev}:off panic=1\0"                  \
 322         "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
 323         "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
 324         "flash_nfs=run nfsargs addip addtty addmisc;"                   \
 325                 "bootm ${kernel_addr}\0"                                \
 326         "flash_self=run ramargs addip addtty addmisc;"                  \
 327                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 328         "net_nfs=tftp 200000 ${bootfile};"                              \
 329                 "run nfsargs addip addtty addmisc;bootm\0"              \
 330         "rootpath=/opt/eldk/ppc_4xxFP\0"                                \
 331         "bootfile=/tftpboot/lwmon5/uImage\0"                            \
 332         "kernel_addr=FC000000\0"                                        \
 333         "ramdisk_addr=FC180000\0"                                       \
 334         "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0"           \
 335         "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;"   \
 336                 "cp.b 200000 FFF80000 80000\0"                          \
 337         "upd=run load update\0"                                         \
 338         "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;"       \
 339                 "autoscr 200000\0"                                      \
 340         ""
 341 #define CONFIG_BOOTCOMMAND      "run flash_self"
 342
 343
 344 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 345 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 346
 347 #define CONFIG_PPC4xx_EMAC
 348 #define CONFIG_IBM_EMAC4_V4     1
 349 #define CONFIG_MII              1       /* MII PHY management           */
 350 #define CONFIG_PHY_ADDR         3       /* PHY address, See schematics  */
 351
 352 #define CONFIG_PHY_RESET        1       /* reset phy upon startup         */
 353 #define CONFIG_PHY_RESET_DELAY  300
 354
 355 #define CONFIG_HAS_ETH0
 356 #define CONFIG_SYS_RX_ETH_BUFFER        32      /* Number of ethernet rx buffers & descriptors */
 357
 358 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 359 #define CONFIG_PHY1_ADDR        1
 360
 361 /* Video console */
 362 #define CONFIG_VIDEO
 363 #define CONFIG_VIDEO_MB862xx
 364 #define CONFIG_VIDEO_MB862xx_ACCEL
 365 #define CONFIG_CFB_CONSOLE
 366 #define CONFIG_VIDEO_LOGO
 367 #define CONFIG_CONSOLE_EXTRA_INFO
 368 #define VIDEO_FB_16BPP_PIXEL_SWAP
 369 #define VIDEO_FB_16BPP_WORD_SWAP
 370
 371 #define CONFIG_VGA_AS_SINGLE_DEVICE
 372 #define CONFIG_VIDEO_SW_CURSOR
 373 #define CONFIG_SPLASH_SCREEN
 374
 375 /*
 376  * USB/EHCI
 377  */
 378 #define CONFIG_USB_EHCI                 /* Enable EHCI USB support      */
 379 #define CONFIG_USB_EHCI_PPC4XX          /* on PPC4xx platform           */
 380 #define CONFIG_SYS_PPC4XX_USB_ADDR      0xe0000300
 381 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
 382 #define CONFIG_EHCI_DESC_BIG_ENDIAN
 383 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
 384
 385 /* Partitions */
 386 #define CONFIG_MAC_PARTITION
 387 #define CONFIG_DOS_PARTITION
 388 #define CONFIG_ISO_PARTITION
 389
 390 /*
 391  * BOOTP options
 392  */
 393 #define CONFIG_BOOTP_BOOTFILESIZE
 394 #define CONFIG_BOOTP_BOOTPATH
 395 #define CONFIG_BOOTP_GATEWAY
 396 #define CONFIG_BOOTP_HOSTNAME
 397
 398 /*
 399  * Command line configuration.
 400  */
 401 #define CONFIG_CMD_DATE
 402 #define CONFIG_CMD_DIAG
 403 #define CONFIG_CMD_EEPROM
 404 #define CONFIG_CMD_IRQ
 405 #define CONFIG_CMD_REGINFO
 406 #define CONFIG_CMD_SDRAM
 407
 408 #ifdef CONFIG_VIDEO
 409 #define CONFIG_CMD_BMP
 410 #endif
 411
 412 #ifdef CONFIG_440EPX
 413 #endif
 414
 415 /*
 416  * Miscellaneous configurable options
 417  */
 418 #define CONFIG_SUPPORT_VFAT
 419
 420 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 421
 422 #if defined(CONFIG_CMD_KGDB)
 423 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 424 #else
 425 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 426 #endif
 427 #define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 428 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 429 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size  */
 430
 431 #define CONFIG_SYS_MEMTEST_START        0x0400000 /* memtest works on           */
 432 #define CONFIG_SYS_MEMTEST_END          0x0C00000 /* 4 ... 12 MB in DRAM        */
 433
 434 #define CONFIG_SYS_LOAD_ADDR            0x100000  /* default load address       */
 435 #define CONFIG_SYS_EXTBDINFO            1       /* To use extended board_into (bd_t) */
 436
 437 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 438 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 439
 440 #define CONFIG_SYS_CONSOLE_INFO_QUIET   /* don't print console @ startup*/
 441
 442 #ifndef DEBUG
 443 #define CONFIG_HW_WATCHDOG      1       /* Use external HW-Watchdog     */
 444 #endif
 445 #define CONFIG_WD_PERIOD        40000   /* in usec */
 446 #define CONFIG_WD_MAX_RATE      66600   /* in ticks */
 447
 448 /*
 449  * For booting Linux, the board info and command line data
 450  * have to be in the first 16 MB of memory, since this is
 451  * the maximum mapped by the 40x Linux kernel during initialization.
 452  */
 453 #define CONFIG_SYS_BOOTMAPSZ            (16 << 20) /* Initial Memory map for Linux */
 454 #define CONFIG_SYS_BOOTM_LEN            (16 << 20) /* Increase max gunzip size */
 455
 456 /*
 457  * External Bus Controller (EBC) Setup
 458  */
 459 #define CONFIG_SYS_FLASH                CONFIG_SYS_FLASH_BASE
 460
 461 /* Memory Bank 0 (NOR-FLASH) initialization                                     */
 462 #define CONFIG_SYS_EBC_PB0AP            0x03000280
 463 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH | 0xfc000)
 464
 465 /* Memory Bank 1 (Lime) initialization                                          */
 466 #define CONFIG_SYS_EBC_PB1AP            0x01004380
 467 #define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_LIME_BASE_0 | 0xbc000)
 468
 469 /* Memory Bank 2 (FPGA) initialization                                          */
 470 #define CONFIG_SYS_EBC_PB2AP            0x01004400
 471 #define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_FPGA_BASE_0 | 0x1c000)
 472
 473 /* Memory Bank 3 (FPGA2) initialization                                         */
 474 #define CONFIG_SYS_EBC_PB3AP            0x01004400
 475 #define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_FPGA_BASE_1 | 0x1c000)
 476
 477 #define CONFIG_SYS_EBC_CFG              0xb8400000
 478
 479 /*
 480  * Graphics (Fujitsu Lime)
 481  */
 482 /* SDRAM Clock frequency adjustment register */
 483 #define CONFIG_SYS_LIME_SDRAM_CLOCK     0xC1FC0038
 484 #if 1 /* 133MHz is not tested enough, use 100MHz for now */
 485 /* Lime Clock frequency is to set 100MHz */
 486 #define CONFIG_SYS_LIME_CLOCK_100MHZ    0x00000
 487 #else
 488 /* Lime Clock frequency for 133MHz */
 489 #define CONFIG_SYS_LIME_CLOCK_133MHZ    0x10000
 490 #endif
 491
 492 /* SDRAM Parameter register */
 493 #define CONFIG_SYS_LIME_MMR             0xC1FCFFFC
 494 /*
 495  * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
 496  * and pixel flare on display when 133MHz was configured. According to
 497  * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed
 498  * Grade
 499  */
 500 #ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
 501 #define CONFIG_SYS_MB862xx_MMR  0x414FB7F3
 502 #define CONFIG_SYS_MB862xx_CCF  CONFIG_SYS_LIME_CLOCK_133MHZ
 503 #else
 504 #define CONFIG_SYS_MB862xx_MMR  0x414FB7F2
 505 #define CONFIG_SYS_MB862xx_CCF  CONFIG_SYS_LIME_CLOCK_100MHZ
 506 #endif
 507
 508 /*
 509  * GPIO Setup
 510  */
 511 #define CONFIG_SYS_GPIO_PHY1_RST        12
 512 #define CONFIG_SYS_GPIO_FLASH_WP        14
 513 #define CONFIG_SYS_GPIO_PHY0_RST        22
 514 #define CONFIG_SYS_GPIO_PERM_VOLT_FEED  49
 515 #define CONFIG_SYS_GPIO_DSPIC_READY     51
 516 #define CONFIG_SYS_GPIO_CAN_ENABLE      53
 517 #define CONFIG_SYS_GPIO_LSB_ENABLE      54
 518 #define CONFIG_SYS_GPIO_EEPROM_EXT_WP   55
 519 #define CONFIG_SYS_GPIO_HIGHSIDE        56
 520 #define CONFIG_SYS_GPIO_EEPROM_INT_WP   57
 521 #define CONFIG_SYS_GPIO_BOARD_RESET     58
 522 #define CONFIG_SYS_GPIO_LIME_S          59
 523 #define CONFIG_SYS_GPIO_LIME_RST        60
 524 #define CONFIG_SYS_GPIO_SYSMON_STATUS   62
 525 #define CONFIG_SYS_GPIO_WATCHDOG        63
 526
 527 #define GPIO49_VAL      1
 528
 529 /*
 530  * PPC440 GPIO Configuration
 531  */
 532 #define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 533 {                                                                                       \
 534 /* GPIO Core 0 */                                                                       \
 535 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7)     DMA_REQ(2)      */      \
 536 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6)     DMA_ACK(2)      */      \
 537 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5)     DMA_EOT/TC(2)   */      \
 538 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4)     DMA_REQ(3)      */      \
 539 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3)     DMA_ACK(3)      */      \
 540 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2)     DMA_EOT/TC(3)   */      \
 541 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1)                     */      \
 542 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2)                     */      \
 543 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3)                     */      \
 544 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4)                     */      \
 545 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5)                    */      \
 546 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR                    */      \
 547 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12                                */      \
 548 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13                                */      \
 549 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14                                */      \
 550 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15                                */      \
 551 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4)                      */      \
 552 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5)                      */      \
 553 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6)                      */      \
 554 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7)                      */      \
 555 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0                     */      \
 556 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1                     */      \
 557 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22                                */      \
 558 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0                          */      \
 559 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2)                      */      \
 560 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3)                      */      \
 561 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26                                */      \
 562 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ    USB2D_RXERROR   */      \
 563 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28                USB2D_TXVALID   */      \
 564 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA   USB2D_PAD_SUSPNDM */    \
 565 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK    USB2D_XCVRSELECT*/      \
 566 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/      \
 567 },                                                                                      \
 568 {                                                                                       \
 569 /* GPIO Core 1 */                                                                       \
 570 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0  EBC_DATA(2)     */      \
 571 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1  EBC_DATA(3)     */      \
 572 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N    UART1_DSR_CTS_N UART2_SOUT*/ \
 573 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 574 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0)   UART3_SIN*/ \
 575 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N    EBC_DATA(1)     UART3_SOUT*/ \
 576 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N    UART1_SOUT      */      \
 577 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N     UART1_SIN       */      \
 578 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0)                     */      \
 579 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1)                     */      \
 580 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2)                     */      \
 581 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3)                     */      \
 582 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4)     DMA_ACK(1)      */      \
 583 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6)     DMA_EOT/TC(1)   */      \
 584 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7)     DMA_REQ(0)      */      \
 585 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8)     DMA_ACK(0)      */      \
 586 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9)     DMA_EOT/TC(0)   */      \
 587 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO49_VAL}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 588 {GPIO1_BASE, GPIO_IN,  GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 589 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 590 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 591 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 592 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 593 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 594 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 595 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 596 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 597 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 598 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 599 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 600 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 601 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 602 }                                                                                       \
 603 }
 604
 605 #if defined(CONFIG_CMD_KGDB)
 606 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 607 #endif
 608
 609 #endif  /* __CONFIG_H */