]> git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/lwmon5.h
projects / people / ms / u-boot.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Revert "powerpc: ppc4xx: remove lwmon5 support"
[people/ms/u-boot.git] / include / configs / lwmon5.h
1 /*
2 * (C) Copyright 2007-2013
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 /*
9 * lwmon5.h - configuration for lwmon5 board
10 */
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 /*
15 * Liebherr extra version info
16 */
17 #define CONFIG_IDENT_STRING " - v2.0"
18
19 /*
20 * High Level Configuration Options
21 */
22 #define CONFIG_LWMON5 1 /* Board is lwmon5 */
23 #define CONFIG_440EPX 1 /* Specific PPC440EPx */
24 #define CONFIG_440 1 /* ... PPC440 family */
25
26 #ifdef CONFIG_LCD4_LWMON5
27 #define CONFIG_SYS_TEXT_BASE 0x01000000 /* SPL U-Boot TEXT_BASE */
28 #define CONFIG_HOSTNAME lcd4_lwmon5
29 #else
30 #define CONFIG_SYS_TEXT_BASE 0xFFF80000
31 #define CONFIG_HOSTNAME lwmon5
32 #endif
33
34 #define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
35
36 #define CONFIG_4xx_DCACHE /* enable cache in SDRAM */
37
38 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */
39 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
40 #define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */
41 #define CONFIG_MISC_INIT_R /* Call misc_init_r */
42 #define CONFIG_BOARD_RESET /* Call board_reset */
43
44 /*
45 * Base addresses -- Note these are effective addresses where the
46 * actual resources get mapped (not physical addresses)
47 */
48 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */
49 #define CONFIG_SYS_MONITOR_LEN 0x80000
50 #define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */
51
52 #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
53 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
54 #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
55 #define CONFIG_SYS_LIME_BASE_0 0xc0000000
56 #define CONFIG_SYS_LIME_BASE_1 0xc1000000
57 #define CONFIG_SYS_LIME_BASE_2 0xc2000000
58 #define CONFIG_SYS_LIME_BASE_3 0xc3000000
59 #define CONFIG_SYS_FPGA_BASE_0 0xc4000000
60 #define CONFIG_SYS_FPGA_BASE_1 0xc4200000
61 #define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
62 #define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
63 #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
64 #define CONFIG_SYS_PCI_MEMBASE1 (CONFIG_SYS_PCI_MEMBASE + 0x10000000)
65 #define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000)
66 #define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000)
67
68 #ifndef CONFIG_LCD4_LWMON5
69 #define CONFIG_SYS_USB2D0_BASE 0xe0000100
70 #define CONFIG_SYS_USB_DEVICE 0xe0000000
71 #define CONFIG_SYS_USB_HOST 0xe0000400
72 #endif
73
74 /*
75 * Initial RAM & stack pointer
76 *
77 * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
78 * the POST_WORD from OCM to a 440EPx register that preserves it's
79 * content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
80 * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
81 */
82 #ifndef CONFIG_LCD4_LWMON5
83 #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
84 #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
85 #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
86 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
87 GENERATED_GBL_DATA_SIZE)
88 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
89 #else
90 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE
91 #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
92 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
93 GENERATED_GBL_DATA_SIZE)
94 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
95 #endif
96 /* unused GPT0 COMP reg */
97 #define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
98 #define CONFIG_SYS_OCM_SIZE (16 << 10)
99 /* 440EPx errata CHIP 11: don't use last 4kbytes */
100 #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10)
101
102 /* Additional registers for watchdog timer post test */
103 #define CONFIG_SYS_WATCHDOG_TIME_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2)
104 #define CONFIG_SYS_WATCHDOG_FLAGS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1)
105 #define CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
106 #define CONFIG_SYS_OCM_STATUS_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
107 #define CONFIG_SYS_WATCHDOG_MAGIC 0x12480000
108 #define CONFIG_SYS_WATCHDOG_MAGIC_MASK 0xFFFF0000
109 #define CONFIG_SYS_DSPIC_TEST_MASK 0x00000001
110 #define CONFIG_SYS_OCM_STATUS_OK 0x00009A00
111 #define CONFIG_SYS_OCM_STATUS_FAIL 0x0000A300
112 #define CONFIG_SYS_OCM_STATUS_MASK 0x0000FF00
113
114 /*
115 * Serial Port
116 */
117 #define CONFIG_CONS_INDEX 2 /* Use UART1 */
118 #define CONFIG_SYS_NS16550
119 #define CONFIG_SYS_NS16550_SERIAL
120 #define CONFIG_SYS_NS16550_REG_SIZE 1
121 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
122 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */
123 #define CONFIG_BAUDRATE 115200
124
125 #define CONFIG_SYS_BAUDRATE_TABLE \
126 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
127
128 /*
129 * Environment
130 */
131 #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
132
133 /*
134 * FLASH related
135 */
136 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
137 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
138
139 #define CONFIG_SYS_FLASH0 0xFC000000
140 #define CONFIG_SYS_FLASH1 0xF8000000
141 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
142
143 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 /* max number of memory banks */
144 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
145
146 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
147 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
148
149 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
150 #define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */
151
152 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
153 #define CONFIG_SYS_FLASH_QUIET_TEST /* don't warn upon unknown flash */
154
155 #define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
156 #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE)
157 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
158
159 /* Address and size of Redundant Environment Sector */
160 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
161 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
162
163 /*
164 * DDR SDRAM
165 */
166 #define CONFIG_SYS_MBYTES_SDRAM 256
167 #define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
168 #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
169 #ifndef CONFIG_LCD4_LWMON5
170 #define CONFIG_DDR_ECC /* enable ECC */
171 #endif
172
173 #ifndef CONFIG_LCD4_LWMON5
174 /* POST support */
175 #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
176 CONFIG_SYS_POST_CPU | \
177 CONFIG_SYS_POST_ECC | \
178 CONFIG_SYS_POST_ETHER | \
179 CONFIG_SYS_POST_FPU | \
180 CONFIG_SYS_POST_I2C | \
181 CONFIG_SYS_POST_MEMORY | \
182 CONFIG_SYS_POST_OCM | \
183 CONFIG_SYS_POST_RTC | \
184 CONFIG_SYS_POST_SPR | \
185 CONFIG_SYS_POST_UART | \
186 CONFIG_SYS_POST_SYSMON | \
187 CONFIG_SYS_POST_WATCHDOG | \
188 CONFIG_SYS_POST_DSP | \
189 CONFIG_SYS_POST_BSPEC1 | \
190 CONFIG_SYS_POST_BSPEC2 | \
191 CONFIG_SYS_POST_BSPEC3 | \
192 CONFIG_SYS_POST_BSPEC4 | \
193 CONFIG_SYS_POST_BSPEC5)
194
195 /* Define here the base-addresses of the UARTs to test in POST */
196 #define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
197 CONFIG_SYS_NS16550_COM2 }
198
199 #define CONFIG_POST_UART { \
200 "UART test", \
201 "uart", \
202 "This test verifies the UART operation.", \
203 POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL, \
204 &uart_post_test, \
205 NULL, \
206 NULL, \
207 CONFIG_SYS_POST_UART \
208 }
209
210 #define CONFIG_POST_WATCHDOG { \
211 "Watchdog timer test", \
212 "watchdog", \
213 "This test checks the watchdog timer.", \
214 POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \
215 &lwmon5_watchdog_post_test, \
216 NULL, \
217 NULL, \
218 CONFIG_SYS_POST_WATCHDOG \
219 }
220
221 #define CONFIG_POST_BSPEC1 { \
222 "dsPIC init test", \
223 "dspic_init", \
224 "This test returns result of dsPIC READY test run earlier.", \
225 POST_RAM | POST_ALWAYS, \
226 &dspic_init_post_test, \
227 NULL, \
228 NULL, \
229 CONFIG_SYS_POST_BSPEC1 \
230 }
231
232 #define CONFIG_POST_BSPEC2 { \
233 "dsPIC test", \
234 "dspic", \
235 "This test gets result of dsPIC POST and dsPIC version.", \
236 POST_RAM | POST_ALWAYS, \
237 &dspic_post_test, \
238 NULL, \
239 NULL, \
240 CONFIG_SYS_POST_BSPEC2 \
241 }
242
243 #define CONFIG_POST_BSPEC3 { \
244 "FPGA test", \
245 "fpga", \
246 "This test checks FPGA registers and memory.", \
247 POST_RAM | POST_ALWAYS | POST_MANUAL, \
248 &fpga_post_test, \
249 NULL, \
250 NULL, \
251 CONFIG_SYS_POST_BSPEC3 \
252 }
253
254 #define CONFIG_POST_BSPEC4 { \
255 "GDC test", \
256 "gdc", \
257 "This test checks GDC registers and memory.", \
258 POST_RAM | POST_ALWAYS | POST_MANUAL,\
259 &gdc_post_test, \
260 NULL, \
261 NULL, \
262 CONFIG_SYS_POST_BSPEC4 \
263 }
264
265 #define CONFIG_POST_BSPEC5 { \
266 "SYSMON1 test", \
267 "sysmon1", \
268 "This test checks GPIO_62_EPX pin indicating power failure.", \
269 POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \
270 &sysmon1_post_test, \
271 NULL, \
272 NULL, \
273 CONFIG_SYS_POST_BSPEC5 \
274 }
275
276 #define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
277 #define CONFIG_LOGBUFFER
278 /* Reserve GPT0_COMP1-COMP5 for logbuffer header */
279 #define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1)
280 #define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE)
281 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
282 #endif
283
284 /*
285 * I2C
286 */
287 #define CONFIG_SYS_I2C
288 #define CONFIG_SYS_I2C_PPC4XX
289 #define CONFIG_SYS_I2C_PPC4XX_CH0
290 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
291 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
292
293 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* RTC */
294 #define CONFIG_SYS_I2C_EEPROM_CPU_ADDR 0x52 /* EEPROM (CPU Modul) */
295 #define CONFIG_SYS_I2C_EEPROM_MB_ADDR 0x53 /* EEPROM AT24C128 (MainBoard) */
296 #define CONFIG_SYS_I2C_DSPIC_ADDR 0x54 /* dsPIC */
297 #define CONFIG_SYS_I2C_DSPIC_2_ADDR 0x55 /* dsPIC */
298 #define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR 0x56 /* dsPIC */
299 #define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* dsPIC */
300
301 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
302 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */
303 /* 64 byte page write mode using*/
304 /* last 6 bits of the address */
305 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
306 #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
307
308 #define CONFIG_RTC_PCF8563 /* enable Philips PCF8563 RTC */
309 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
310 #define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
311 #define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */
312
313 #define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_RTC_ADDR, \
314 CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\
315 CONFIG_SYS_I2C_EEPROM_MB_ADDR, \
316 CONFIG_SYS_I2C_DSPIC_ADDR, \
317 CONFIG_SYS_I2C_DSPIC_2_ADDR, \
318 CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\
319 CONFIG_SYS_I2C_DSPIC_IO_ADDR }
320
321 /*
322 * Pass open firmware flat tree
323 */
324 #define CONFIG_OF_LIBFDT
325 #define CONFIG_OF_BOARD_SETUP
326 /* Update size in "reg" property of NOR FLASH device tree nodes */
327 #define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
328
329 #define CONFIG_FIT /* enable FIT image support */
330
331 #define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
332
333 #define CONFIG_PREBOOT "setenv bootdelay 15"
334
335 #undef CONFIG_BOOTARGS
336
337 #define CONFIG_EXTRA_ENV_SETTINGS \
338 "hostname=lwmon5\0" \
339 "netdev=eth0\0" \
340 "unlock=yes\0" \
341 "logversion=2\0" \
342 "nfsargs=setenv bootargs root=/dev/nfs rw " \
343 "nfsroot=${serverip}:${rootpath}\0" \
344 "ramargs=setenv bootargs root=/dev/ram rw\0" \
345 "addip=setenv bootargs ${bootargs} " \
346 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
347 ":${hostname}:${netdev}:off panic=1\0" \
348 "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
349 "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
350 "flash_nfs=run nfsargs addip addtty addmisc;" \
351 "bootm ${kernel_addr}\0" \
352 "flash_self=run ramargs addip addtty addmisc;" \
353 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
354 "net_nfs=tftp 200000 ${bootfile};" \
355 "run nfsargs addip addtty addmisc;bootm\0" \
356 "rootpath=/opt/eldk/ppc_4xxFP\0" \
357 "bootfile=/tftpboot/lwmon5/uImage\0" \
358 "kernel_addr=FC000000\0" \
359 "ramdisk_addr=FC180000\0" \
360 "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
361 "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \
362 "cp.b 200000 FFF80000 80000\0" \
363 "upd=run load update\0" \
364 "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \
365 "autoscr 200000\0" \
366 ""
367 #define CONFIG_BOOTCOMMAND "run flash_self"
368
369 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
370
371 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
372 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
373
374 #define CONFIG_PPC4xx_EMAC
375 #define CONFIG_IBM_EMAC4_V4 1
376 #define CONFIG_MII 1 /* MII PHY management */
377 #define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */
378
379 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
380 #define CONFIG_PHY_RESET_DELAY 300
381
382 #define CONFIG_HAS_ETH0
383 #define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
384
385 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
386 #define CONFIG_PHY1_ADDR 1
387
388 /* Video console */
389 #define CONFIG_VIDEO
390 #define CONFIG_VIDEO_MB862xx
391 #define CONFIG_VIDEO_MB862xx_ACCEL
392 #define CONFIG_CFB_CONSOLE
393 #define CONFIG_VIDEO_LOGO
394 #define CONFIG_CONSOLE_EXTRA_INFO
395 #define VIDEO_FB_16BPP_PIXEL_SWAP
396 #define VIDEO_FB_16BPP_WORD_SWAP
397
398 #define CONFIG_VGA_AS_SINGLE_DEVICE
399 #define CONFIG_VIDEO_SW_CURSOR
400 #define CONFIG_SPLASH_SCREEN
401
402 #ifndef CONFIG_LCD4_LWMON5
403 /*
404 * USB/EHCI
405 */
406 #define CONFIG_USB_EHCI /* Enable EHCI USB support */
407 #define CONFIG_USB_EHCI_PPC4XX /* on PPC4xx platform */
408 #define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
409 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
410 #define CONFIG_EHCI_DESC_BIG_ENDIAN
411 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
412 #define CONFIG_USB_STORAGE
413
414 /* Partitions */
415 #define CONFIG_MAC_PARTITION
416 #define CONFIG_DOS_PARTITION
417 #define CONFIG_ISO_PARTITION
418 #endif
419
420 /*
421 * BOOTP options
422 */
423 #define CONFIG_BOOTP_BOOTFILESIZE
424 #define CONFIG_BOOTP_BOOTPATH
425 #define CONFIG_BOOTP_GATEWAY
426 #define CONFIG_BOOTP_HOSTNAME
427
428 /*
429 * Command line configuration.
430 */
431 #define CONFIG_CMD_ASKENV
432 #define CONFIG_CMD_DATE
433 #define CONFIG_CMD_DHCP
434 #define CONFIG_CMD_DIAG
435 #define CONFIG_CMD_EEPROM
436 #define CONFIG_CMD_ELF
437 #define CONFIG_CMD_FAT
438 #define CONFIG_CMD_I2C
439 #define CONFIG_CMD_IRQ
440 #define CONFIG_CMD_MII
441 #define CONFIG_CMD_PING
442 #define CONFIG_CMD_REGINFO
443 #define CONFIG_CMD_SDRAM
444
445 #ifdef CONFIG_VIDEO
446 #define CONFIG_CMD_BMP
447 #endif
448
449 #ifndef CONFIG_LCD4_LWMON5
450 #ifdef CONFIG_440EPX
451 #define CONFIG_CMD_USB
452 #endif
453 #endif
454
455 /*
456 * Miscellaneous configurable options
457 */
458 #define CONFIG_SUPPORT_VFAT
459
460 #define CONFIG_SYS_LONGHELP /* undef to save memory */
461
462 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
463
464 #if defined(CONFIG_CMD_KGDB)
465 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
466 #else
467 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
468 #endif
469 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
470 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
471 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
472
473 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
474 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
475
476 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
477 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
478
479 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
480 #define CONFIG_LOOPW 1 /* enable loopw command */
481 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
482 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
483
484 #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
485
486 #ifndef CONFIG_LCD4_LWMON5
487 #ifndef DEBUG
488 #define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
489 #endif
490 #define CONFIG_WD_PERIOD 40000 /* in usec */
491 #define CONFIG_WD_MAX_RATE 66600 /* in ticks */
492 #endif
493
494 /*
495 * For booting Linux, the board info and command line data
496 * have to be in the first 16 MB of memory, since this is
497 * the maximum mapped by the 40x Linux kernel during initialization.
498 */
499 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */
500 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
501
502 /*
503 * External Bus Controller (EBC) Setup
504 */
505 #define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
506
507 /* Memory Bank 0 (NOR-FLASH) initialization */
508 #define CONFIG_SYS_EBC_PB0AP 0x03000280
509 #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xfc000)
510
511 /* Memory Bank 1 (Lime) initialization */
512 #define CONFIG_SYS_EBC_PB1AP 0x01004380
513 #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xbc000)
514
515 /* Memory Bank 2 (FPGA) initialization */
516 #define CONFIG_SYS_EBC_PB2AP 0x01004400
517 #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE_0 | 0x1c000)
518
519 /* Memory Bank 3 (FPGA2) initialization */
520 #define CONFIG_SYS_EBC_PB3AP 0x01004400
521 #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FPGA_BASE_1 | 0x1c000)
522
523 #define CONFIG_SYS_EBC_CFG 0xb8400000
524
525 /*
526 * Graphics (Fujitsu Lime)
527 */
528 /* SDRAM Clock frequency adjustment register */
529 #define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038
530 #if 1 /* 133MHz is not tested enough, use 100MHz for now */
531 /* Lime Clock frequency is to set 100MHz */
532 #define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000
533 #else
534 /* Lime Clock frequency for 133MHz */
535 #define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000
536 #endif
537
538 /* SDRAM Parameter register */
539 #define CONFIG_SYS_LIME_MMR 0xC1FCFFFC
540 /*
541 * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
542 * and pixel flare on display when 133MHz was configured. According to
543 * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed
544 * Grade
545 */
546 #ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
547 #define CONFIG_SYS_MB862xx_MMR 0x414FB7F3
548 #define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ
549 #else
550 #define CONFIG_SYS_MB862xx_MMR 0x414FB7F2
551 #define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ
552 #endif
553
554 /*
555 * GPIO Setup
556 */
557 #define CONFIG_SYS_GPIO_PHY1_RST 12
558 #define CONFIG_SYS_GPIO_FLASH_WP 14
559 #define CONFIG_SYS_GPIO_PHY0_RST 22
560 #define CONFIG_SYS_GPIO_PERM_VOLT_FEED 49
561 #define CONFIG_SYS_GPIO_DSPIC_READY 51
562 #define CONFIG_SYS_GPIO_CAN_ENABLE 53
563 #define CONFIG_SYS_GPIO_LSB_ENABLE 54
564 #define CONFIG_SYS_GPIO_EEPROM_EXT_WP 55
565 #define CONFIG_SYS_GPIO_HIGHSIDE 56
566 #define CONFIG_SYS_GPIO_EEPROM_INT_WP 57
567 #define CONFIG_SYS_GPIO_BOARD_RESET 58
568 #define CONFIG_SYS_GPIO_LIME_S 59
569 #define CONFIG_SYS_GPIO_LIME_RST 60
570 #define CONFIG_SYS_GPIO_SYSMON_STATUS 62
571 #define CONFIG_SYS_GPIO_WATCHDOG 63
572
573 /* On LCD4, GPIO49 has to be configured to 0 instead of 1 */
574 #ifdef CONFIG_LCD4_LWMON5
575 #define GPIO49_VAL 0
576 #else
577 #define GPIO49_VAL 1
578 #endif
579
580 /*
581 * PPC440 GPIO Configuration
582 */
583 #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
584 { \
585 /* GPIO Core 0 */ \
586 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
587 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
588 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
589 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
590 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
591 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
592 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
593 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
594 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
595 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
596 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
597 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
598 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
599 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
600 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
601 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \
602 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
603 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
604 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
605 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \
606 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
607 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
608 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
609 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
610 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \
611 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \
612 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
613 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
614 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
615 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
616 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
617 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
618 }, \
619 { \
620 /* GPIO Core 1 */ \
621 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
622 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
623 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
624 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
625 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
626 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
627 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
628 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
629 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
630 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
631 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
632 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
633 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
634 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
635 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
636 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
637 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
638 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO49_VAL}, /* GPIO49 Unselect via TraceSelect Bit */ \
639 {GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
640 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
641 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
642 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
643 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
644 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
645 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
646 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \
647 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
648 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
649 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
650 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
651 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
652 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
653 } \
654 }
655
656 #if defined(CONFIG_CMD_KGDB)
657 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
658 #endif
659
660 /*
661 * SPL related defines
662 */
663 #ifdef CONFIG_LCD4_LWMON5
664 #define CONFIG_SPL_FRAMEWORK
665 #define CONFIG_SPL_BOARD_INIT
666 #define CONFIG_SPL_NOR_SUPPORT
667 #define CONFIG_SPL_TEXT_BASE 0xffff0000 /* last 64 KiB for SPL */
668 #define CONFIG_SYS_SPL_MAX_LEN (64 << 10)
669 #define CONFIG_UBOOT_PAD_TO 458752 /* decimal for 'dd' */
670 #define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
671 #define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
672 #define CONFIG_SPL_SERIAL_SUPPORT
673
674 /* Place BSS for SPL near end of SDRAM */
675 #define CONFIG_SPL_BSS_START_ADDR ((256 - 1) << 20)
676 #define CONFIG_SPL_BSS_MAX_SIZE (64 << 10)
677
678 #define CONFIG_SPL_OS_BOOT
679 /* Place patched DT blob (fdt) at this address */
680 #define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000
681
682 #define CONFIG_SPL_TARGET "u-boot-img-spl-at-end.bin"
683
684 /* Settings for real U-Boot to be loaded from NOR flash */
685 #define CONFIG_SYS_UBOOT_BASE (-CONFIG_SYS_MONITOR_LEN)
686 #define CONFIG_SYS_UBOOT_START 0x01002100
687
688 #define CONFIG_SYS_OS_BASE 0xf8000000
689 #define CONFIG_SYS_FDT_BASE 0xf87c0000
690 #endif
691
692 #endif /* __CONFIG_H */
"Das U-Boot" Source Tree