include/configs/lwmon5.h

   1 /*
   2  * (C) Copyright 2007-2010
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 /*
  22  * lwmon5.h - configuration for lwmon5 board
  23  */
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * Liebherr extra version info
  29  */
  30 #define CONFIG_IDENT_STRING     " - v2.0"
  31
  32 /*
  33  * High Level Configuration Options
  34  */
  35 #define CONFIG_LWMON5           1               /* Board is lwmon5      */
  36 #define CONFIG_440EPX           1               /* Specific PPC440EPx   */
  37 #define CONFIG_440              1               /* ... PPC440 family    */
  38 #define CONFIG_4xx              1               /* ... PPC4xx family    */
  39
  40 #ifndef CONFIG_SYS_TEXT_BASE
  41 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  42 #endif
  43
  44 #define CONFIG_SYS_CLK_FREQ     33300000        /* external freq to pll */
  45
  46 #define CONFIG_4xx_DCACHE               /* enable cache in SDRAM        */
  47
  48 #define CONFIG_BOARD_EARLY_INIT_F       /* Call board_early_init_f      */
  49 #define CONFIG_BOARD_EARLY_INIT_R       /* Call board_early_init_r      */
  50 #define CONFIG_BOARD_POSTCLK_INIT       /* Call board_postclk_init      */
  51 #define CONFIG_MISC_INIT_R              /* Call misc_init_r             */
  52 #define CONFIG_BOARD_RESET              /* Call board_reset             */
  53
  54 /*
  55  * Base addresses -- Note these are effective addresses where the
  56  * actual resources get mapped (not physical addresses)
  57  */
  58 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* Start of U-Boot      */
  59 #define CONFIG_SYS_MONITOR_LEN          (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1)
  60 #define CONFIG_SYS_MALLOC_LEN           (1 << 20)       /* Reserved for malloc  */
  61
  62 #define CONFIG_SYS_BOOT_BASE_ADDR       0xf0000000
  63 #define CONFIG_SYS_SDRAM_BASE           0x00000000      /* _must_ be 0          */
  64 #define CONFIG_SYS_FLASH_BASE           0xf8000000      /* start of FLASH       */
  65 #define CONFIG_SYS_LIME_BASE_0          0xc0000000
  66 #define CONFIG_SYS_LIME_BASE_1          0xc1000000
  67 #define CONFIG_SYS_LIME_BASE_2          0xc2000000
  68 #define CONFIG_SYS_LIME_BASE_3          0xc3000000
  69 #define CONFIG_SYS_FPGA_BASE_0          0xc4000000
  70 #define CONFIG_SYS_FPGA_BASE_1          0xc4200000
  71 #define CONFIG_SYS_OCM_BASE             0xe0010000      /* ocm                  */
  72 #define CONFIG_SYS_PCI_BASE             0xe0000000      /* Internal PCI regs    */
  73 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped pci memory    */
  74 #define CONFIG_SYS_PCI_MEMBASE1         (CONFIG_SYS_PCI_MEMBASE  + 0x10000000)
  75 #define CONFIG_SYS_PCI_MEMBASE2         (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000)
  76 #define CONFIG_SYS_PCI_MEMBASE3         (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000)
  77
  78 #define CONFIG_SYS_USB2D0_BASE          0xe0000100
  79 #define CONFIG_SYS_USB_DEVICE           0xe0000000
  80 #define CONFIG_SYS_USB_HOST             0xe0000400
  81
  82 /*
  83  * Initial RAM & stack pointer
  84  *
  85  * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
  86  * the POST_WORD from OCM to a 440EPx register that preserves it's
  87  * content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
  88  * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
  89  */
  90 #define CONFIG_SYS_INIT_RAM_DCACHE      1               /* d-cache as init ram  */
  91 #define CONFIG_SYS_INIT_RAM_ADDR        0x70000000              /* DCache       */
  92 #define CONFIG_SYS_INIT_RAM_SIZE                (4 << 10)
  93 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
  94                                          GENERATED_GBL_DATA_SIZE)
  95 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  96 /* unused GPT0 COMP reg */
  97 #define CONFIG_SYS_POST_WORD_ADDR       (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
  98 #define CONFIG_SYS_OCM_SIZE             (16 << 10)
  99 /* 440EPx errata CHIP 11: don't use last 4kbytes */
 100 #define CONFIG_SYS_MEM_TOP_HIDE         (4 << 10)
 101
 102 /* Additional registers for watchdog timer post test */
 103 #define CONFIG_SYS_WATCHDOG_TIME_ADDR   (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2)
 104 #define CONFIG_SYS_WATCHDOG_FLAGS_ADDR  (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1)
 105 #define CONFIG_SYS_DSPIC_TEST_ADDR      CONFIG_SYS_WATCHDOG_FLAGS_ADDR
 106 #define CONFIG_SYS_OCM_STATUS_ADDR      CONFIG_SYS_WATCHDOG_FLAGS_ADDR
 107 #define CONFIG_SYS_WATCHDOG_MAGIC       0x12480000
 108 #define CONFIG_SYS_WATCHDOG_MAGIC_MASK  0xFFFF0000
 109 #define CONFIG_SYS_DSPIC_TEST_MASK      0x00000001
 110 #define CONFIG_SYS_OCM_STATUS_OK        0x00009A00
 111 #define CONFIG_SYS_OCM_STATUS_FAIL      0x0000A300
 112 #define CONFIG_SYS_OCM_STATUS_MASK      0x0000FF00
 113
 114 /*
 115  * Serial Port
 116  */
 117 #define CONFIG_CONS_INDEX       2       /* Use UART1                    */
 118 #define CONFIG_SYS_NS16550
 119 #define CONFIG_SYS_NS16550_SERIAL
 120 #define CONFIG_SYS_NS16550_REG_SIZE     1
 121 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 122 #undef CONFIG_SYS_EXT_SERIAL_CLOCK              /* no external clock provided   */
 123 #define CONFIG_BAUDRATE         115200
 124 #define CONFIG_SERIAL_MULTI
 125
 126 #define CONFIG_SYS_BAUDRATE_TABLE                                               \
 127         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 128
 129 /*
 130  * Environment
 131  */
 132 #define CONFIG_ENV_IS_IN_FLASH          /* use FLASH for environment vars       */
 133
 134 /*
 135  * FLASH related
 136  */
 137 #define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
 138 #define CONFIG_FLASH_CFI_DRIVER                 /* Use common CFI driver        */
 139
 140 #define CONFIG_SYS_FLASH0               0xFC000000
 141 #define CONFIG_SYS_FLASH1               0xF8000000
 142 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
 143
 144 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2     /* max number of memory banks           */
 145 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 146
 147 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 148 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 149
 150 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       /* use buffered writes (20x faster)     */
 151 #define CONFIG_SYS_FLASH_PROTECTION             /* use hardware flash protection        */
 152
 153 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 154 #define CONFIG_SYS_FLASH_QUIET_TEST             /* don't warn upon unknown flash        */
 155
 156 #define CONFIG_ENV_SECT_SIZE    0x40000 /* size of one complete sector          */
 157 #define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE)
 158 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 159
 160 /* Address and size of Redundant Environment Sector     */
 161 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 162 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 163
 164 /*
 165  * DDR SDRAM
 166  */
 167 #define CONFIG_SYS_MBYTES_SDRAM         256
 168 #define CONFIG_SYS_DDR_CACHED_ADDR      0x40000000      /* setup 2nd TLB cached here    */
 169 #define CONFIG_DDR_DATA_EYE                     /* use DDR2 optimization        */
 170 #define CONFIG_DDR_ECC                          /* enable ECC                   */
 171
 172 /* POST support */
 173 #define CONFIG_POST             (CONFIG_SYS_POST_CACHE          | \
 174                                  CONFIG_SYS_POST_CPU            | \
 175                                  CONFIG_SYS_POST_ECC            | \
 176                                  CONFIG_SYS_POST_ETHER          | \
 177                                  CONFIG_SYS_POST_FPU            | \
 178                                  CONFIG_SYS_POST_I2C            | \
 179                                  CONFIG_SYS_POST_MEMORY         | \
 180                                  CONFIG_SYS_POST_OCM            | \
 181                                  CONFIG_SYS_POST_RTC            | \
 182                                  CONFIG_SYS_POST_SPR            | \
 183                                  CONFIG_SYS_POST_UART           | \
 184                                  CONFIG_SYS_POST_SYSMON         | \
 185                                  CONFIG_SYS_POST_WATCHDOG       | \
 186                                  CONFIG_SYS_POST_DSP            | \
 187                                  CONFIG_SYS_POST_BSPEC1         | \
 188                                  CONFIG_SYS_POST_BSPEC2         | \
 189                                  CONFIG_SYS_POST_BSPEC3         | \
 190                                  CONFIG_SYS_POST_BSPEC4         | \
 191                                  CONFIG_SYS_POST_BSPEC5)
 192
 193 /* Define here the base-addresses of the UARTs to test in POST */
 194 #define CONFIG_SYS_POST_UART_TABLE      { CONFIG_SYS_NS16550_COM1, \
 195                         CONFIG_SYS_NS16550_COM2 }
 196
 197 #define CONFIG_POST_UART  {                             \
 198         "UART test",                                    \
 199         "uart",                                         \
 200         "This test verifies the UART operation.",       \
 201         POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL,   \
 202         &uart_post_test,                                \
 203         NULL,                                           \
 204         NULL,                                           \
 205         CONFIG_SYS_POST_UART                            \
 206         }
 207
 208 #define CONFIG_POST_WATCHDOG  {                         \
 209         "Watchdog timer test",                          \
 210         "watchdog",                                     \
 211         "This test checks the watchdog timer.",         \
 212         POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \
 213         &lwmon5_watchdog_post_test,                     \
 214         NULL,                                           \
 215         NULL,                                           \
 216         CONFIG_SYS_POST_WATCHDOG                        \
 217         }
 218
 219 #define CONFIG_POST_BSPEC1    {                         \
 220         "dsPIC init test",                              \
 221         "dspic_init",                                   \
 222         "This test returns result of dsPIC READY test run earlier.",    \
 223         POST_RAM | POST_ALWAYS,                         \
 224         &dspic_init_post_test,                          \
 225         NULL,                                           \
 226         NULL,                                           \
 227         CONFIG_SYS_POST_BSPEC1                          \
 228         }
 229
 230 #define CONFIG_POST_BSPEC2    {                         \
 231         "dsPIC test",                                   \
 232         "dspic",                                        \
 233         "This test gets result of dsPIC POST and dsPIC version.",       \
 234         POST_RAM | POST_ALWAYS,                         \
 235         &dspic_post_test,                               \
 236         NULL,                                           \
 237         NULL,                                           \
 238         CONFIG_SYS_POST_BSPEC2                          \
 239         }
 240
 241 #define CONFIG_POST_BSPEC3    {                         \
 242         "FPGA test",                                    \
 243         "fpga",                                         \
 244         "This test checks FPGA registers and memory.",  \
 245         POST_RAM | POST_ALWAYS | POST_MANUAL,           \
 246         &fpga_post_test,                                \
 247         NULL,                                           \
 248         NULL,                                           \
 249         CONFIG_SYS_POST_BSPEC3                          \
 250         }
 251
 252 #define CONFIG_POST_BSPEC4    {                         \
 253         "GDC test",                                     \
 254         "gdc",                                          \
 255         "This test checks GDC registers and memory.",   \
 256         POST_RAM | POST_ALWAYS | POST_MANUAL,\
 257         &gdc_post_test,                                 \
 258         NULL,                                           \
 259         NULL,                                           \
 260         CONFIG_SYS_POST_BSPEC4                          \
 261         }
 262
 263 #define CONFIG_POST_BSPEC5    {                         \
 264         "SYSMON1 test",                                 \
 265         "sysmon1",                                      \
 266         "This test checks GPIO_62_EPX pin indicating power failure.",   \
 267         POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST,   \
 268         &sysmon1_post_test,                             \
 269         NULL,                                           \
 270         NULL,                                           \
 271         CONFIG_SYS_POST_BSPEC5                          \
 272         }
 273
 274 #define CONFIG_SYS_POST_CACHE_ADDR      0x7fff0000 /* free virtual address      */
 275 #define CONFIG_LOGBUFFER
 276 /* Reserve GPT0_COMP1-COMP5 for logbuffer header */
 277 #define CONFIG_ALT_LH_ADDR      (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1)
 278 #define CONFIG_ALT_LB_ADDR      (CONFIG_SYS_OCM_BASE)
 279 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
 280
 281 /*
 282  * I2C
 283  */
 284 #define CONFIG_HARD_I2C                         /* I2C with hardware support    */
 285 #undef  CONFIG_SOFT_I2C                         /* I2C bit-banged               */
 286 #define CONFIG_PPC4XX_I2C               /* use PPC4xx driver            */
 287 #define CONFIG_SYS_I2C_SPEED            100000          /* I2C speed and slave address  */
 288 #define CONFIG_SYS_I2C_SLAVE            0x7F
 289
 290 #define CONFIG_SYS_I2C_RTC_ADDR 0x51    /* RTC                          */
 291 #define CONFIG_SYS_I2C_EEPROM_CPU_ADDR  0x52    /* EEPROM          (CPU Modul)  */
 292 #define CONFIG_SYS_I2C_EEPROM_MB_ADDR   0x53    /* EEPROM AT24C128 (MainBoard)  */
 293 #define CONFIG_SYS_I2C_DSPIC_ADDR       0x54    /* dsPIC                        */
 294 #define CONFIG_SYS_I2C_DSPIC_2_ADDR     0x55    /* dsPIC                        */
 295 #define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR  0x56    /* dsPIC                        */
 296 #define CONFIG_SYS_I2C_DSPIC_IO_ADDR    0x57    /* dsPIC                        */
 297
 298 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2        /* Bytes of address             */
 299 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6     /* The Atmel AT24C128 has       */
 300                                         /* 64 byte page write mode using*/
 301                                         /* last 6 bits of the address   */
 302 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 303 #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
 304
 305 #define CONFIG_RTC_PCF8563                      /* enable Philips PCF8563 RTC   */
 306 #define CONFIG_SYS_I2C_RTC_ADDR         0x51    /* Philips PCF8563 RTC address  */
 307 #define CONFIG_SYS_I2C_KEYBD_ADDR       0x56    /* PIC LWE keyboard             */
 308 #define CONFIG_SYS_I2C_DSPIC_IO_ADDR    0x57    /* PIC I/O addr               */
 309
 310 #define CONFIG_SYS_POST_I2C_ADDRS       {CONFIG_SYS_I2C_RTC_ADDR,       \
 311                                          CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\
 312                                          CONFIG_SYS_I2C_EEPROM_MB_ADDR, \
 313                                          CONFIG_SYS_I2C_DSPIC_ADDR,     \
 314                                          CONFIG_SYS_I2C_DSPIC_2_ADDR,   \
 315                                          CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\
 316                                          CONFIG_SYS_I2C_DSPIC_IO_ADDR }
 317
 318 /*
 319  * Pass open firmware flat tree
 320  */
 321 #define CONFIG_OF_LIBFDT
 322 #define CONFIG_OF_BOARD_SETUP
 323 /* Update size in "reg" property of NOR FLASH device tree nodes */
 324 #define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
 325
 326 #define CONFIG_FIT                      /* enable FIT image support     */
 327
 328 #define CONFIG_POST_KEY_MAGIC   "3C+3E" /* press F3 + F5 keys to force POST */
 329
 330 #define CONFIG_PREBOOT          "setenv bootdelay 15"
 331
 332 #undef  CONFIG_BOOTARGS
 333
 334 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 335         "hostname=lwmon5\0"                                             \
 336         "netdev=eth0\0"                                                 \
 337         "unlock=yes\0"                                                  \
 338         "logversion=2\0"                                                \
 339         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 340                 "nfsroot=${serverip}:${rootpath}\0"                     \
 341         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 342         "addip=setenv bootargs ${bootargs} "                            \
 343                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 344                 ":${hostname}:${netdev}:off panic=1\0"                  \
 345         "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
 346         "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
 347         "flash_nfs=run nfsargs addip addtty addmisc;"                   \
 348                 "bootm ${kernel_addr}\0"                                \
 349         "flash_self=run ramargs addip addtty addmisc;"                  \
 350                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 351         "net_nfs=tftp 200000 ${bootfile};"                              \
 352                 "run nfsargs addip addtty addmisc;bootm\0"              \
 353         "rootpath=/opt/eldk/ppc_4xxFP\0"                                \
 354         "bootfile=/tftpboot/lwmon5/uImage\0"                            \
 355         "kernel_addr=FC000000\0"                                        \
 356         "ramdisk_addr=FC180000\0"                                       \
 357         "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0"           \
 358         "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;"   \
 359                 "cp.b 200000 FFF80000 80000\0"                          \
 360         "upd=run load update\0"                                         \
 361         "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;"       \
 362                 "autoscr 200000\0"                                      \
 363         ""
 364 #define CONFIG_BOOTCOMMAND      "run flash_self"
 365
 366 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 367
 368 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 369 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 370
 371 #define CONFIG_PPC4xx_EMAC
 372 #define CONFIG_IBM_EMAC4_V4     1
 373 #define CONFIG_MII              1       /* MII PHY management           */
 374 #define CONFIG_PHY_ADDR         3       /* PHY address, See schematics  */
 375
 376 #define CONFIG_PHY_RESET        1       /* reset phy upon startup         */
 377 #define CONFIG_PHY_RESET_DELAY  300
 378
 379 #define CONFIG_HAS_ETH0
 380 #define CONFIG_SYS_RX_ETH_BUFFER        32      /* Number of ethernet rx buffers & descriptors */
 381
 382 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 383 #define CONFIG_PHY1_ADDR        1
 384
 385 /* Video console */
 386 #define CONFIG_VIDEO
 387 #define CONFIG_VIDEO_MB862xx
 388 #define CONFIG_VIDEO_MB862xx_ACCEL
 389 #define CONFIG_CFB_CONSOLE
 390 #define CONFIG_VIDEO_LOGO
 391 #define CONFIG_CONSOLE_EXTRA_INFO
 392 #define VIDEO_FB_16BPP_PIXEL_SWAP
 393 #define VIDEO_FB_16BPP_WORD_SWAP
 394
 395 #define CONFIG_VGA_AS_SINGLE_DEVICE
 396 #define CONFIG_VIDEO_SW_CURSOR
 397 #define CONFIG_SPLASH_SCREEN
 398
 399 /*
 400  * USB/EHCI
 401  */
 402 #define CONFIG_USB_EHCI                 /* Enable EHCI USB support      */
 403 #define CONFIG_USB_EHCI_PPC4XX          /* on PPC4xx platform           */
 404 #define CONFIG_SYS_PPC4XX_USB_ADDR      0xe0000300
 405 #define CONFIG_EHCI_DCACHE              /* with dcache handling support */
 406 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
 407 #define CONFIG_EHCI_DESC_BIG_ENDIAN
 408 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
 409 #define CONFIG_USB_STORAGE
 410
 411 /* Partitions */
 412 #define CONFIG_MAC_PARTITION
 413 #define CONFIG_DOS_PARTITION
 414 #define CONFIG_ISO_PARTITION
 415
 416 /*
 417  * BOOTP options
 418  */
 419 #define CONFIG_BOOTP_BOOTFILESIZE
 420 #define CONFIG_BOOTP_BOOTPATH
 421 #define CONFIG_BOOTP_GATEWAY
 422 #define CONFIG_BOOTP_HOSTNAME
 423
 424 /*
 425  * Command line configuration.
 426  */
 427 #include <config_cmd_default.h>
 428
 429 #define CONFIG_CMD_ASKENV
 430 #define CONFIG_CMD_DATE
 431 #define CONFIG_CMD_DHCP
 432 #define CONFIG_CMD_DIAG
 433 #define CONFIG_CMD_EEPROM
 434 #define CONFIG_CMD_ELF
 435 #define CONFIG_CMD_FAT
 436 #define CONFIG_CMD_I2C
 437 #define CONFIG_CMD_IRQ
 438 #define CONFIG_CMD_MII
 439 #define CONFIG_CMD_NET
 440 #define CONFIG_CMD_NFS
 441 #define CONFIG_CMD_PING
 442 #define CONFIG_CMD_REGINFO
 443 #define CONFIG_CMD_SDRAM
 444
 445 #ifdef CONFIG_VIDEO
 446 #define CONFIG_CMD_BMP
 447 #endif
 448
 449 #ifdef CONFIG_440EPX
 450 #define CONFIG_CMD_USB
 451 #endif
 452
 453 /*
 454  * Miscellaneous configurable options
 455  */
 456 #define CONFIG_SUPPORT_VFAT
 457
 458 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 459 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt       */
 460
 461 #define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser          */
 462 #ifdef  CONFIG_SYS_HUSH_PARSER
 463 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 464 #endif
 465
 466 #if defined(CONFIG_CMD_KGDB)
 467 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 468 #else
 469 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 470 #endif
 471 #define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 472 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 473 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size  */
 474
 475 #define CONFIG_SYS_MEMTEST_START        0x0400000 /* memtest works on           */
 476 #define CONFIG_SYS_MEMTEST_END          0x0C00000 /* 4 ... 12 MB in DRAM        */
 477
 478 #define CONFIG_SYS_LOAD_ADDR            0x100000  /* default load address       */
 479 #define CONFIG_SYS_EXTBDINFO            1       /* To use extended board_into (bd_t) */
 480
 481 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 482
 483 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 484 #define CONFIG_LOOPW            1       /* enable loopw command         */
 485 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 486 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 487
 488 #ifndef DEBUG
 489 #define CONFIG_HW_WATCHDOG      1       /* Use external HW-Watchdog     */
 490 #endif
 491 #define CONFIG_WD_PERIOD        40000   /* in usec */
 492 #define CONFIG_WD_MAX_RATE      66600   /* in ticks */
 493
 494 /*
 495  * For booting Linux, the board info and command line data
 496  * have to be in the first 16 MB of memory, since this is
 497  * the maximum mapped by the 40x Linux kernel during initialization.
 498  */
 499 #define CONFIG_SYS_BOOTMAPSZ            (16 << 20) /* Initial Memory map for Linux */
 500 #define CONFIG_SYS_BOOTM_LEN            (16 << 20) /* Increase max gunzip size */
 501
 502 /*
 503  * External Bus Controller (EBC) Setup
 504  */
 505 #define CONFIG_SYS_FLASH                CONFIG_SYS_FLASH_BASE
 506
 507 /* Memory Bank 0 (NOR-FLASH) initialization                                     */
 508 #define CONFIG_SYS_EBC_PB0AP            0x03000280
 509 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH | 0xfc000)
 510
 511 /* Memory Bank 1 (Lime) initialization                                          */
 512 #define CONFIG_SYS_EBC_PB1AP            0x01004380
 513 #define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_LIME_BASE_0 | 0xbc000)
 514
 515 /* Memory Bank 2 (FPGA) initialization                                          */
 516 #define CONFIG_SYS_EBC_PB2AP            0x01004400
 517 #define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_FPGA_BASE_0 | 0x1c000)
 518
 519 /* Memory Bank 3 (FPGA2) initialization                                         */
 520 #define CONFIG_SYS_EBC_PB3AP            0x01004400
 521 #define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_FPGA_BASE_1 | 0x1c000)
 522
 523 #define CONFIG_SYS_EBC_CFG              0xb8400000
 524
 525 /*
 526  * Graphics (Fujitsu Lime)
 527  */
 528 /* SDRAM Clock frequency adjustment register */
 529 #define CONFIG_SYS_LIME_SDRAM_CLOCK     0xC1FC0038
 530 #if 1 /* 133MHz is not tested enough, use 100MHz for now */
 531 /* Lime Clock frequency is to set 100MHz */
 532 #define CONFIG_SYS_LIME_CLOCK_100MHZ    0x00000
 533 #else
 534 /* Lime Clock frequency for 133MHz */
 535 #define CONFIG_SYS_LIME_CLOCK_133MHZ    0x10000
 536 #endif
 537
 538 /* SDRAM Parameter register */
 539 #define CONFIG_SYS_LIME_MMR             0xC1FCFFFC
 540 /*
 541  * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
 542  * and pixel flare on display when 133MHz was configured. According to
 543  * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed
 544  * Grade
 545  */
 546 #ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
 547 #define CONFIG_SYS_MB862xx_MMR  0x414FB7F3
 548 #define CONFIG_SYS_MB862xx_CCF  CONFIG_SYS_LIME_CLOCK_133MHZ
 549 #else
 550 #define CONFIG_SYS_MB862xx_MMR  0x414FB7F2
 551 #define CONFIG_SYS_MB862xx_CCF  CONFIG_SYS_LIME_CLOCK_100MHZ
 552 #endif
 553
 554 /*
 555  * GPIO Setup
 556  */
 557 #define CONFIG_SYS_GPIO_PHY1_RST        12
 558 #define CONFIG_SYS_GPIO_FLASH_WP        14
 559 #define CONFIG_SYS_GPIO_PHY0_RST        22
 560 #define CONFIG_SYS_GPIO_DSPIC_READY     51
 561 #define CONFIG_SYS_GPIO_CAN_ENABLE      53
 562 #define CONFIG_SYS_GPIO_LSB_ENABLE      54
 563 #define CONFIG_SYS_GPIO_EEPROM_EXT_WP   55
 564 #define CONFIG_SYS_GPIO_HIGHSIDE        56
 565 #define CONFIG_SYS_GPIO_EEPROM_INT_WP   57
 566 #define CONFIG_SYS_GPIO_BOARD_RESET     58
 567 #define CONFIG_SYS_GPIO_LIME_S          59
 568 #define CONFIG_SYS_GPIO_LIME_RST        60
 569 #define CONFIG_SYS_GPIO_SYSMON_STATUS   62
 570 #define CONFIG_SYS_GPIO_WATCHDOG        63
 571
 572 /*
 573  * PPC440 GPIO Configuration
 574  */
 575 #define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 576 {                                                                                       \
 577 /* GPIO Core 0 */                                                                       \
 578 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7)     DMA_REQ(2)      */      \
 579 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6)     DMA_ACK(2)      */      \
 580 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5)     DMA_EOT/TC(2)   */      \
 581 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4)     DMA_REQ(3)      */      \
 582 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3)     DMA_ACK(3)      */      \
 583 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2)     DMA_EOT/TC(3)   */      \
 584 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1)                     */      \
 585 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2)                     */      \
 586 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3)                     */      \
 587 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4)                     */      \
 588 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5)                    */      \
 589 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR                    */      \
 590 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12                                */      \
 591 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13                                */      \
 592 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14                                */      \
 593 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15                                */      \
 594 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4)                      */      \
 595 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5)                      */      \
 596 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6)                      */      \
 597 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7)                      */      \
 598 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0                     */      \
 599 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1                     */      \
 600 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22                                */      \
 601 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0                          */      \
 602 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2)                      */      \
 603 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3)                      */      \
 604 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26                                */      \
 605 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ    USB2D_RXERROR   */      \
 606 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28                USB2D_TXVALID   */      \
 607 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA   USB2D_PAD_SUSPNDM */    \
 608 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK    USB2D_XCVRSELECT*/      \
 609 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/      \
 610 },                                                                                      \
 611 {                                                                                       \
 612 /* GPIO Core 1 */                                                                       \
 613 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0  EBC_DATA(2)     */      \
 614 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1  EBC_DATA(3)     */      \
 615 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N    UART1_DSR_CTS_N UART2_SOUT*/ \
 616 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 617 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0)   UART3_SIN*/ \
 618 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N    EBC_DATA(1)     UART3_SOUT*/ \
 619 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N    UART1_SOUT      */      \
 620 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N     UART1_SIN       */      \
 621 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0)                     */      \
 622 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1)                     */      \
 623 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2)                     */      \
 624 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3)                     */      \
 625 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4)     DMA_ACK(1)      */      \
 626 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6)     DMA_EOT/TC(1)   */      \
 627 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7)     DMA_REQ(0)      */      \
 628 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8)     DMA_ACK(0)      */      \
 629 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9)     DMA_EOT/TC(0)   */      \
 630 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 631 {GPIO1_BASE, GPIO_IN,  GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 632 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 633 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 634 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 635 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 636 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 637 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 638 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 639 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 640 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 641 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 642 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 643 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 644 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 645 }                                                                                       \
 646 }
 647
 648 #if defined(CONFIG_CMD_KGDB)
 649 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 650 #define CONFIG_KGDB_SER_INDEX   2           /* which serial port to use */
 651 #endif
 652 #endif  /* __CONFIG_H */