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Merge branch 'microblaze' of git://www.denx.de/git/u-boot-microblaze
[people/ms/u-boot.git] / include / configs / lwmon5.h
1 /*
2 * (C) Copyright 2007-2013
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21 /*
22 * lwmon5.h - configuration for lwmon5 board
23 */
24 #ifndef __CONFIG_H
25 #define __CONFIG_H
26
27 /*
28 * Liebherr extra version info
29 */
30 #define CONFIG_IDENT_STRING " - v2.0"
31
32 /*
33 * High Level Configuration Options
34 */
35 #define CONFIG_LWMON5 1 /* Board is lwmon5 */
36 #define CONFIG_440EPX 1 /* Specific PPC440EPx */
37 #define CONFIG_440 1 /* ... PPC440 family */
38 #define CONFIG_4xx 1 /* ... PPC4xx family */
39
40 #ifdef CONFIG_LCD4_LWMON5
41 #define CONFIG_SYS_TEXT_BASE 0x01000000 /* SPL U-Boot TEXT_BASE */
42 #define CONFIG_HOSTNAME lcd4_lwmon5
43 #else
44 #define CONFIG_SYS_TEXT_BASE 0xFFF80000
45 #define CONFIG_HOSTNAME lwmon5
46 #endif
47
48 #define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
49
50 #define CONFIG_4xx_DCACHE /* enable cache in SDRAM */
51
52 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */
53 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
54 #define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */
55 #define CONFIG_MISC_INIT_R /* Call misc_init_r */
56 #define CONFIG_BOARD_RESET /* Call board_reset */
57
58 /*
59 * Base addresses -- Note these are effective addresses where the
60 * actual resources get mapped (not physical addresses)
61 */
62 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */
63 #define CONFIG_SYS_MONITOR_LEN 0x80000
64 #define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */
65
66 #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
67 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
68 #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
69 #define CONFIG_SYS_LIME_BASE_0 0xc0000000
70 #define CONFIG_SYS_LIME_BASE_1 0xc1000000
71 #define CONFIG_SYS_LIME_BASE_2 0xc2000000
72 #define CONFIG_SYS_LIME_BASE_3 0xc3000000
73 #define CONFIG_SYS_FPGA_BASE_0 0xc4000000
74 #define CONFIG_SYS_FPGA_BASE_1 0xc4200000
75 #define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
76 #define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
77 #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
78 #define CONFIG_SYS_PCI_MEMBASE1 (CONFIG_SYS_PCI_MEMBASE + 0x10000000)
79 #define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000)
80 #define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000)
81
82 #ifndef CONFIG_LCD4_LWMON5
83 #define CONFIG_SYS_USB2D0_BASE 0xe0000100
84 #define CONFIG_SYS_USB_DEVICE 0xe0000000
85 #define CONFIG_SYS_USB_HOST 0xe0000400
86 #endif
87
88 /*
89 * Initial RAM & stack pointer
90 *
91 * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
92 * the POST_WORD from OCM to a 440EPx register that preserves it's
93 * content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
94 * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
95 */
96 #ifndef CONFIG_LCD4_LWMON5
97 #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
98 #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
99 #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
100 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
101 GENERATED_GBL_DATA_SIZE)
102 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
103 #else
104 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE
105 #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
106 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
107 GENERATED_GBL_DATA_SIZE)
108 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
109 #endif
110 /* unused GPT0 COMP reg */
111 #define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
112 #define CONFIG_SYS_OCM_SIZE (16 << 10)
113 /* 440EPx errata CHIP 11: don't use last 4kbytes */
114 #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10)
115
116 /* Additional registers for watchdog timer post test */
117 #define CONFIG_SYS_WATCHDOG_TIME_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2)
118 #define CONFIG_SYS_WATCHDOG_FLAGS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1)
119 #define CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
120 #define CONFIG_SYS_OCM_STATUS_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
121 #define CONFIG_SYS_WATCHDOG_MAGIC 0x12480000
122 #define CONFIG_SYS_WATCHDOG_MAGIC_MASK 0xFFFF0000
123 #define CONFIG_SYS_DSPIC_TEST_MASK 0x00000001
124 #define CONFIG_SYS_OCM_STATUS_OK 0x00009A00
125 #define CONFIG_SYS_OCM_STATUS_FAIL 0x0000A300
126 #define CONFIG_SYS_OCM_STATUS_MASK 0x0000FF00
127
128 /*
129 * Serial Port
130 */
131 #define CONFIG_CONS_INDEX 2 /* Use UART1 */
132 #define CONFIG_SYS_NS16550
133 #define CONFIG_SYS_NS16550_SERIAL
134 #define CONFIG_SYS_NS16550_REG_SIZE 1
135 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
136 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */
137 #define CONFIG_BAUDRATE 115200
138
139 #define CONFIG_SYS_BAUDRATE_TABLE \
140 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
141
142 /*
143 * Environment
144 */
145 #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
146
147 /*
148 * FLASH related
149 */
150 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
151 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
152
153 #define CONFIG_SYS_FLASH0 0xFC000000
154 #define CONFIG_SYS_FLASH1 0xF8000000
155 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
156
157 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 /* max number of memory banks */
158 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
159
160 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
161 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
162
163 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
164 #define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */
165
166 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
167 #define CONFIG_SYS_FLASH_QUIET_TEST /* don't warn upon unknown flash */
168
169 #define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
170 #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE)
171 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
172
173 /* Address and size of Redundant Environment Sector */
174 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
175 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
176
177 /*
178 * DDR SDRAM
179 */
180 #define CONFIG_SYS_MBYTES_SDRAM 256
181 #define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
182 #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
183 #ifndef CONFIG_LCD4_LWMON5
184 #define CONFIG_DDR_ECC /* enable ECC */
185 #endif
186
187 #ifndef CONFIG_LCD4_LWMON5
188 /* POST support */
189 #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
190 CONFIG_SYS_POST_CPU | \
191 CONFIG_SYS_POST_ECC | \
192 CONFIG_SYS_POST_ETHER | \
193 CONFIG_SYS_POST_FPU | \
194 CONFIG_SYS_POST_I2C | \
195 CONFIG_SYS_POST_MEMORY | \
196 CONFIG_SYS_POST_OCM | \
197 CONFIG_SYS_POST_RTC | \
198 CONFIG_SYS_POST_SPR | \
199 CONFIG_SYS_POST_UART | \
200 CONFIG_SYS_POST_SYSMON | \
201 CONFIG_SYS_POST_WATCHDOG | \
202 CONFIG_SYS_POST_DSP | \
203 CONFIG_SYS_POST_BSPEC1 | \
204 CONFIG_SYS_POST_BSPEC2 | \
205 CONFIG_SYS_POST_BSPEC3 | \
206 CONFIG_SYS_POST_BSPEC4 | \
207 CONFIG_SYS_POST_BSPEC5)
208
209 /* Define here the base-addresses of the UARTs to test in POST */
210 #define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
211 CONFIG_SYS_NS16550_COM2 }
212
213 #define CONFIG_POST_UART { \
214 "UART test", \
215 "uart", \
216 "This test verifies the UART operation.", \
217 POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL, \
218 &uart_post_test, \
219 NULL, \
220 NULL, \
221 CONFIG_SYS_POST_UART \
222 }
223
224 #define CONFIG_POST_WATCHDOG { \
225 "Watchdog timer test", \
226 "watchdog", \
227 "This test checks the watchdog timer.", \
228 POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \
229 &lwmon5_watchdog_post_test, \
230 NULL, \
231 NULL, \
232 CONFIG_SYS_POST_WATCHDOG \
233 }
234
235 #define CONFIG_POST_BSPEC1 { \
236 "dsPIC init test", \
237 "dspic_init", \
238 "This test returns result of dsPIC READY test run earlier.", \
239 POST_RAM | POST_ALWAYS, \
240 &dspic_init_post_test, \
241 NULL, \
242 NULL, \
243 CONFIG_SYS_POST_BSPEC1 \
244 }
245
246 #define CONFIG_POST_BSPEC2 { \
247 "dsPIC test", \
248 "dspic", \
249 "This test gets result of dsPIC POST and dsPIC version.", \
250 POST_RAM | POST_ALWAYS, \
251 &dspic_post_test, \
252 NULL, \
253 NULL, \
254 CONFIG_SYS_POST_BSPEC2 \
255 }
256
257 #define CONFIG_POST_BSPEC3 { \
258 "FPGA test", \
259 "fpga", \
260 "This test checks FPGA registers and memory.", \
261 POST_RAM | POST_ALWAYS | POST_MANUAL, \
262 &fpga_post_test, \
263 NULL, \
264 NULL, \
265 CONFIG_SYS_POST_BSPEC3 \
266 }
267
268 #define CONFIG_POST_BSPEC4 { \
269 "GDC test", \
270 "gdc", \
271 "This test checks GDC registers and memory.", \
272 POST_RAM | POST_ALWAYS | POST_MANUAL,\
273 &gdc_post_test, \
274 NULL, \
275 NULL, \
276 CONFIG_SYS_POST_BSPEC4 \
277 }
278
279 #define CONFIG_POST_BSPEC5 { \
280 "SYSMON1 test", \
281 "sysmon1", \
282 "This test checks GPIO_62_EPX pin indicating power failure.", \
283 POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \
284 &sysmon1_post_test, \
285 NULL, \
286 NULL, \
287 CONFIG_SYS_POST_BSPEC5 \
288 }
289
290 #define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
291 #define CONFIG_LOGBUFFER
292 /* Reserve GPT0_COMP1-COMP5 for logbuffer header */
293 #define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1)
294 #define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE)
295 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
296 #endif
297
298 /*
299 * I2C
300 */
301 #define CONFIG_HARD_I2C /* I2C with hardware support */
302 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
303 #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
304 #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
305 #define CONFIG_SYS_I2C_SLAVE 0x7F
306
307 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* RTC */
308 #define CONFIG_SYS_I2C_EEPROM_CPU_ADDR 0x52 /* EEPROM (CPU Modul) */
309 #define CONFIG_SYS_I2C_EEPROM_MB_ADDR 0x53 /* EEPROM AT24C128 (MainBoard) */
310 #define CONFIG_SYS_I2C_DSPIC_ADDR 0x54 /* dsPIC */
311 #define CONFIG_SYS_I2C_DSPIC_2_ADDR 0x55 /* dsPIC */
312 #define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR 0x56 /* dsPIC */
313 #define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* dsPIC */
314
315 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
316 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */
317 /* 64 byte page write mode using*/
318 /* last 6 bits of the address */
319 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
320 #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
321
322 #define CONFIG_RTC_PCF8563 /* enable Philips PCF8563 RTC */
323 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
324 #define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
325 #define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */
326
327 #define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_RTC_ADDR, \
328 CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\
329 CONFIG_SYS_I2C_EEPROM_MB_ADDR, \
330 CONFIG_SYS_I2C_DSPIC_ADDR, \
331 CONFIG_SYS_I2C_DSPIC_2_ADDR, \
332 CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\
333 CONFIG_SYS_I2C_DSPIC_IO_ADDR }
334
335 /*
336 * Pass open firmware flat tree
337 */
338 #define CONFIG_OF_LIBFDT
339 #define CONFIG_OF_BOARD_SETUP
340 /* Update size in "reg" property of NOR FLASH device tree nodes */
341 #define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
342
343 #define CONFIG_FIT /* enable FIT image support */
344
345 #define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
346
347 #define CONFIG_PREBOOT "setenv bootdelay 15"
348
349 #undef CONFIG_BOOTARGS
350
351 #define CONFIG_EXTRA_ENV_SETTINGS \
352 "hostname=lwmon5\0" \
353 "netdev=eth0\0" \
354 "unlock=yes\0" \
355 "logversion=2\0" \
356 "nfsargs=setenv bootargs root=/dev/nfs rw " \
357 "nfsroot=${serverip}:${rootpath}\0" \
358 "ramargs=setenv bootargs root=/dev/ram rw\0" \
359 "addip=setenv bootargs ${bootargs} " \
360 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
361 ":${hostname}:${netdev}:off panic=1\0" \
362 "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
363 "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
364 "flash_nfs=run nfsargs addip addtty addmisc;" \
365 "bootm ${kernel_addr}\0" \
366 "flash_self=run ramargs addip addtty addmisc;" \
367 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
368 "net_nfs=tftp 200000 ${bootfile};" \
369 "run nfsargs addip addtty addmisc;bootm\0" \
370 "rootpath=/opt/eldk/ppc_4xxFP\0" \
371 "bootfile=/tftpboot/lwmon5/uImage\0" \
372 "kernel_addr=FC000000\0" \
373 "ramdisk_addr=FC180000\0" \
374 "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
375 "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \
376 "cp.b 200000 FFF80000 80000\0" \
377 "upd=run load update\0" \
378 "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \
379 "autoscr 200000\0" \
380 ""
381 #define CONFIG_BOOTCOMMAND "run flash_self"
382
383 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
384
385 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
386 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
387
388 #define CONFIG_PPC4xx_EMAC
389 #define CONFIG_IBM_EMAC4_V4 1
390 #define CONFIG_MII 1 /* MII PHY management */
391 #define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */
392
393 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
394 #define CONFIG_PHY_RESET_DELAY 300
395
396 #define CONFIG_HAS_ETH0
397 #define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
398
399 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
400 #define CONFIG_PHY1_ADDR 1
401
402 /* Video console */
403 #define CONFIG_VIDEO
404 #define CONFIG_VIDEO_MB862xx
405 #define CONFIG_VIDEO_MB862xx_ACCEL
406 #define CONFIG_CFB_CONSOLE
407 #define CONFIG_VIDEO_LOGO
408 #define CONFIG_CONSOLE_EXTRA_INFO
409 #define VIDEO_FB_16BPP_PIXEL_SWAP
410 #define VIDEO_FB_16BPP_WORD_SWAP
411
412 #define CONFIG_VGA_AS_SINGLE_DEVICE
413 #define CONFIG_VIDEO_SW_CURSOR
414 #define CONFIG_SPLASH_SCREEN
415
416 #ifndef CONFIG_LCD4_LWMON5
417 /*
418 * USB/EHCI
419 */
420 #define CONFIG_USB_EHCI /* Enable EHCI USB support */
421 #define CONFIG_USB_EHCI_PPC4XX /* on PPC4xx platform */
422 #define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
423 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
424 #define CONFIG_EHCI_DESC_BIG_ENDIAN
425 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
426 #define CONFIG_USB_STORAGE
427
428 /* Partitions */
429 #define CONFIG_MAC_PARTITION
430 #define CONFIG_DOS_PARTITION
431 #define CONFIG_ISO_PARTITION
432 #endif
433
434 /*
435 * BOOTP options
436 */
437 #define CONFIG_BOOTP_BOOTFILESIZE
438 #define CONFIG_BOOTP_BOOTPATH
439 #define CONFIG_BOOTP_GATEWAY
440 #define CONFIG_BOOTP_HOSTNAME
441
442 /*
443 * Command line configuration.
444 */
445 #include <config_cmd_default.h>
446
447 #define CONFIG_CMD_ASKENV
448 #define CONFIG_CMD_DATE
449 #define CONFIG_CMD_DHCP
450 #define CONFIG_CMD_DIAG
451 #define CONFIG_CMD_EEPROM
452 #define CONFIG_CMD_ELF
453 #define CONFIG_CMD_FAT
454 #define CONFIG_CMD_I2C
455 #define CONFIG_CMD_IRQ
456 #define CONFIG_CMD_MII
457 #define CONFIG_CMD_NET
458 #define CONFIG_CMD_NFS
459 #define CONFIG_CMD_PING
460 #define CONFIG_CMD_REGINFO
461 #define CONFIG_CMD_SDRAM
462
463 #ifdef CONFIG_VIDEO
464 #define CONFIG_CMD_BMP
465 #endif
466
467 #ifndef CONFIG_LCD4_LWMON5
468 #ifdef CONFIG_440EPX
469 #define CONFIG_CMD_USB
470 #endif
471 #endif
472
473 /*
474 * Miscellaneous configurable options
475 */
476 #define CONFIG_SUPPORT_VFAT
477
478 #define CONFIG_SYS_LONGHELP /* undef to save memory */
479 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
480
481 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
482
483 #if defined(CONFIG_CMD_KGDB)
484 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
485 #else
486 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
487 #endif
488 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
489 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
490 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
491
492 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
493 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
494
495 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
496 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
497
498 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
499
500 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
501 #define CONFIG_LOOPW 1 /* enable loopw command */
502 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
503 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
504
505 #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
506
507 #ifndef CONFIG_LCD4_LWMON5
508 #ifndef DEBUG
509 #define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
510 #endif
511 #define CONFIG_WD_PERIOD 40000 /* in usec */
512 #define CONFIG_WD_MAX_RATE 66600 /* in ticks */
513 #endif
514
515 /*
516 * For booting Linux, the board info and command line data
517 * have to be in the first 16 MB of memory, since this is
518 * the maximum mapped by the 40x Linux kernel during initialization.
519 */
520 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */
521 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
522
523 /*
524 * External Bus Controller (EBC) Setup
525 */
526 #define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
527
528 /* Memory Bank 0 (NOR-FLASH) initialization */
529 #define CONFIG_SYS_EBC_PB0AP 0x03000280
530 #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xfc000)
531
532 /* Memory Bank 1 (Lime) initialization */
533 #define CONFIG_SYS_EBC_PB1AP 0x01004380
534 #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xbc000)
535
536 /* Memory Bank 2 (FPGA) initialization */
537 #define CONFIG_SYS_EBC_PB2AP 0x01004400
538 #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE_0 | 0x1c000)
539
540 /* Memory Bank 3 (FPGA2) initialization */
541 #define CONFIG_SYS_EBC_PB3AP 0x01004400
542 #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FPGA_BASE_1 | 0x1c000)
543
544 #define CONFIG_SYS_EBC_CFG 0xb8400000
545
546 /*
547 * Graphics (Fujitsu Lime)
548 */
549 /* SDRAM Clock frequency adjustment register */
550 #define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038
551 #if 1 /* 133MHz is not tested enough, use 100MHz for now */
552 /* Lime Clock frequency is to set 100MHz */
553 #define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000
554 #else
555 /* Lime Clock frequency for 133MHz */
556 #define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000
557 #endif
558
559 /* SDRAM Parameter register */
560 #define CONFIG_SYS_LIME_MMR 0xC1FCFFFC
561 /*
562 * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
563 * and pixel flare on display when 133MHz was configured. According to
564 * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed
565 * Grade
566 */
567 #ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
568 #define CONFIG_SYS_MB862xx_MMR 0x414FB7F3
569 #define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ
570 #else
571 #define CONFIG_SYS_MB862xx_MMR 0x414FB7F2
572 #define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ
573 #endif
574
575 /*
576 * GPIO Setup
577 */
578 #define CONFIG_SYS_GPIO_PHY1_RST 12
579 #define CONFIG_SYS_GPIO_FLASH_WP 14
580 #define CONFIG_SYS_GPIO_PHY0_RST 22
581 #define CONFIG_SYS_GPIO_DSPIC_READY 51
582 #define CONFIG_SYS_GPIO_CAN_ENABLE 53
583 #define CONFIG_SYS_GPIO_LSB_ENABLE 54
584 #define CONFIG_SYS_GPIO_EEPROM_EXT_WP 55
585 #define CONFIG_SYS_GPIO_HIGHSIDE 56
586 #define CONFIG_SYS_GPIO_EEPROM_INT_WP 57
587 #define CONFIG_SYS_GPIO_BOARD_RESET 58
588 #define CONFIG_SYS_GPIO_LIME_S 59
589 #define CONFIG_SYS_GPIO_LIME_RST 60
590 #define CONFIG_SYS_GPIO_SYSMON_STATUS 62
591 #define CONFIG_SYS_GPIO_WATCHDOG 63
592
593 /*
594 * PPC440 GPIO Configuration
595 */
596 #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
597 { \
598 /* GPIO Core 0 */ \
599 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
600 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
601 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
602 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
603 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
604 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
605 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
606 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
607 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
608 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
609 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
610 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
611 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
612 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
613 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
614 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \
615 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
616 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
617 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
618 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \
619 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
620 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
621 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
622 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
623 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \
624 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \
625 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
626 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
627 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
628 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
629 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
630 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
631 }, \
632 { \
633 /* GPIO Core 1 */ \
634 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
635 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
636 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
637 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
638 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
639 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
640 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
641 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
642 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
643 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
644 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
645 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
646 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
647 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
648 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
649 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
650 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
651 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \
652 {GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
653 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
654 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
655 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
656 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
657 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
658 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
659 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \
660 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
661 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
662 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
663 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
664 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
665 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
666 } \
667 }
668
669 #if defined(CONFIG_CMD_KGDB)
670 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
671 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
672 #endif
673
674 /*
675 * SPL related defines
676 */
677 #ifdef CONFIG_LCD4_LWMON5
678 #define CONFIG_SPL
679 #define CONFIG_SPL_FRAMEWORK
680 #define CONFIG_SPL_BOARD_INIT
681 #define CONFIG_SPL_NOR_SUPPORT
682 #define CONFIG_SPL_TEXT_BASE 0xffff0000 /* last 64 KiB for SPL */
683 #define CONFIG_SYS_SPL_MAX_LEN (64 << 10)
684 #define CONFIG_UBOOT_PAD_TO 458752 /* decimal for 'dd' */
685 #define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/ppc4xx"
686 #define CONFIG_SPL_LDSCRIPT "arch/powerpc/cpu/ppc4xx/u-boot-spl.lds"
687 #define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
688 #define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
689 #define CONFIG_SPL_SERIAL_SUPPORT
690
691 /* Place BSS for SPL near end of SDRAM */
692 #define CONFIG_SPL_BSS_START_ADDR ((256 - 1) << 20)
693 #define CONFIG_SPL_BSS_MAX_SIZE (64 << 10)
694
695 #define CONFIG_SPL_OS_BOOT
696 /* Place patched DT blob (fdt) at this address */
697 #define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000
698
699 #define CONFIG_SPL_TARGET "u-boot-img-spl-at-end.bin"
700
701 /* Settings for real U-Boot to be loaded from NOR flash */
702 #define CONFIG_SYS_UBOOT_BASE (-CONFIG_SYS_MONITOR_LEN)
703 #define CONFIG_SYS_UBOOT_START 0x01002100
704
705 #define CONFIG_SYS_OS_BASE 0xf8000000
706 #define CONFIG_SYS_FDT_BASE 0xf87c0000
707 #endif
708
709 #endif /* __CONFIG_H */
"Das U-Boot" Source Tree