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1 /*
2 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #ifndef _CONFIG_DB_MV7846MP_GP_H
8 #define _CONFIG_DB_MV7846MP_GP_H
9
10 /*
11 * High Level Configuration Options (easy to change)
12 */
13 #define CONFIG_ARMADA_XP /* SOC Family Name */
14 #define CONFIG_DISPLAY_BOARDINFO_LATE
15
16 /*
17 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
18 * for DDR ECC byte filling in the SPL before loading the main
19 * U-Boot into it.
20 */
21 #define CONFIG_SYS_TEXT_BASE 0x00800000
22 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */
23
24 /*
25 * Commands configuration
26 */
27 #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
28 #define CONFIG_CMD_DHCP
29 #define CONFIG_CMD_ENV
30 #define CONFIG_CMD_I2C
31 #define CONFIG_CMD_PING
32 #define CONFIG_CMD_SF
33 #define CONFIG_CMD_SPI
34 #define CONFIG_CMD_TFTPPUT
35 #define CONFIG_CMD_TIME
36
37 /* I2C */
38 #define CONFIG_SYS_I2C
39 #define CONFIG_SYS_I2C_MVTWSI
40 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
41 #define CONFIG_SYS_I2C_SLAVE 0x0
42 #define CONFIG_SYS_I2C_SPEED 100000
43
44 /* SPI NOR flash default params, used by sf commands */
45 #define CONFIG_SF_DEFAULT_SPEED 1000000
46 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
47
48 /* Environment in SPI NOR flash */
49 #define CONFIG_ENV_IS_IN_SPI_FLASH
50 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
51 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
52 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
53
54 #define CONFIG_PHY_MARVELL /* there is a marvell phy */
55 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
56
57 #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
58 #define CONFIG_SYS_ALT_MEMTEST
59
60 /*
61 * mv-common.h should be defined after CMD configs since it used them
62 * to enable certain macros
63 */
64 #include "mv-common.h"
65
66 /*
67 * Memory layout while starting into the bin_hdr via the
68 * BootROM:
69 *
70 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
71 * 0x4000.4030 bin_hdr start address
72 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
73 * 0x4007.fffc BootROM stack top
74 *
75 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
76 * L2 cache thus cannot be used.
77 */
78
79 /* SPL */
80 /* Defines for SPL */
81 #define CONFIG_SPL_FRAMEWORK
82 #define CONFIG_SPL_TEXT_BASE 0x40004030
83 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
84
85 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
86 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
87
88 #ifdef CONFIG_SPL_BUILD
89 #define CONFIG_SYS_MALLOC_SIMPLE
90 #endif
91
92 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
93 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
94
95 #define CONFIG_SPL_LIBCOMMON_SUPPORT
96 #define CONFIG_SPL_LIBGENERIC_SUPPORT
97 #define CONFIG_SPL_SERIAL_SUPPORT
98 #define CONFIG_SPL_I2C_SUPPORT
99
100 /* SPL related SPI defines */
101 #define CONFIG_SPL_SPI_SUPPORT
102 #define CONFIG_SPL_SPI_FLASH_SUPPORT
103 #define CONFIG_SPL_SPI_LOAD
104 #define CONFIG_SPL_SPI_BUS 0
105 #define CONFIG_SPL_SPI_CS 0
106 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
107
108 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
109 #define CONFIG_SYS_MVEBU_DDR_AXP
110 #define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */
111 #define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
112
113 #endif /* _CONFIG_DB_MV7846MP_GP_H */