include/configs/maxbcm.h

   1 /*
   2  * Copyright (C) 2014 Stefan Roese <sr@denx.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _CONFIG_DB_MV7846MP_GP_H
   8 #define _CONFIG_DB_MV7846MP_GP_H
   9
  10 /*
  11  * High Level Configuration Options (easy to change)
  12  */
  13 #define CONFIG_ARMADA_XP                /* SOC Family Name */
  14 #ifdef CONFIG_SPL_BUILD
  15 #define CONFIG_SKIP_LOWLEVEL_INIT       /* disable board lowlevel_init */
  16 #endif
  17 #define CONFIG_SYS_GENERIC_BOARD
  18 #define CONFIG_DISPLAY_BOARDINFO_LATE
  19
  20 /*
  21  * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
  22  * for DDR ECC byte filling in the SPL before loading the main
  23  * U-Boot into it.
  24  */
  25 #define CONFIG_SYS_TEXT_BASE    0x00800000
  26 #define CONFIG_SYS_TCLK         250000000       /* 250MHz */
  27
  28 /*
  29  * Commands configuration
  30  */
  31 #define CONFIG_SYS_NO_FLASH             /* Declare no flash (NOR/SPI) */
  32 #define CONFIG_CMD_DHCP
  33 #define CONFIG_CMD_ENV
  34 #define CONFIG_CMD_I2C
  35 #define CONFIG_CMD_PING
  36 #define CONFIG_CMD_SF
  37 #define CONFIG_CMD_SPI
  38 #define CONFIG_CMD_TFTPPUT
  39 #define CONFIG_CMD_TIME
  40
  41 /* I2C */
  42 #define CONFIG_SYS_I2C
  43 #define CONFIG_SYS_I2C_MVTWSI
  44 #define CONFIG_I2C_MVTWSI_BASE0         MVEBU_TWSI_BASE
  45 #define CONFIG_SYS_I2C_SLAVE            0x0
  46 #define CONFIG_SYS_I2C_SPEED            100000
  47
  48 /* SPI NOR flash default params, used by sf commands */
  49 #define CONFIG_SF_DEFAULT_SPEED         1000000
  50 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_3
  51 #define CONFIG_SPI_FLASH_STMICRO
  52 #define CONFIG_SPI_FLASH_SPANSION
  53
  54 /* Environment in SPI NOR flash */
  55 #define CONFIG_ENV_IS_IN_SPI_FLASH
  56 #define CONFIG_ENV_OFFSET               (1 << 20) /* 1MiB in */
  57 #define CONFIG_ENV_SIZE                 (64 << 10) /* 64KiB */
  58 #define CONFIG_ENV_SECT_SIZE            (64 << 10) /* 64KiB sectors */
  59
  60 #define CONFIG_PHY_MARVELL              /* there is a marvell phy */
  61 #define CONFIG_PHY_ADDR                 { 0x0, 0x1, 0x2, 0x3 }
  62 #define CONFIG_SYS_NETA_INTERFACE_TYPE  PHY_INTERFACE_MODE_SGMII
  63 #define PHY_ANEG_TIMEOUT        8000    /* PHY needs a longer aneg time */
  64 #define CONFIG_RESET_PHY_R
  65
  66 #define CONFIG_SYS_CONSOLE_INFO_QUIET   /* don't print console @ startup */
  67 #define CONFIG_SYS_ALT_MEMTEST
  68
  69 /*
  70  * mv-common.h should be defined after CMD configs since it used them
  71  * to enable certain macros
  72  */
  73 #include "mv-common.h"
  74
  75 /*
  76  * Memory layout while starting into the bin_hdr via the
  77  * BootROM:
  78  *
  79  * 0x4000.4000 - 0x4003.4000    headers space (192KiB)
  80  * 0x4000.4030                  bin_hdr start address
  81  * 0x4003.4000 - 0x4004.7c00    BootROM memory allocations (15KiB)
  82  * 0x4007.fffc                  BootROM stack top
  83  *
  84  * The address space between 0x4007.fffc and 0x400f.fff is not locked in
  85  * L2 cache thus cannot be used.
  86  */
  87
  88 /* SPL */
  89 /* Defines for SPL */
  90 #define CONFIG_SPL_FRAMEWORK
  91 #define CONFIG_SPL_TEXT_BASE            0x40004030
  92 #define CONFIG_SPL_MAX_SIZE             ((128 << 10) - 0x4030)
  93
  94 #define CONFIG_SPL_BSS_START_ADDR       (0x40000000 + (128 << 10))
  95 #define CONFIG_SPL_BSS_MAX_SIZE         (16 << 10)
  96
  97 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR + \
  98                                          CONFIG_SPL_BSS_MAX_SIZE)
  99 #define CONFIG_SYS_SPL_MALLOC_SIZE      (16 << 10)
 100
 101 #define CONFIG_SPL_STACK                (0x40000000 + ((192 - 16) << 10))
 102 #define CONFIG_SPL_BOOTROM_SAVE         (CONFIG_SPL_STACK + 4)
 103
 104 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 105 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 106 #define CONFIG_SPL_SERIAL_SUPPORT
 107 #define CONFIG_SPL_I2C_SUPPORT
 108
 109 /* SPL related SPI defines */
 110 #define CONFIG_SPL_SPI_SUPPORT
 111 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 112 #define CONFIG_SPL_SPI_LOAD
 113 #define CONFIG_SPL_SPI_BUS              0
 114 #define CONFIG_SPL_SPI_CS               0
 115 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x20000
 116
 117 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
 118 #define CONFIG_SYS_MVEBU_DDR_AXP
 119 #define CONFIG_DDR_FIXED_SIZE           (1 << 20)       /* 1GiB */
 120
 121 #endif /* _CONFIG_DB_MV7846MP_GP_H */