include/configs/mcc200.h

   1 /*
   2  * (C) Copyright 2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * High Level Configuration Options
  29  * (easy to change)
  30  */
  31
  32 #define CONFIG_MPC5200
  33 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU               */
  34 #define CONFIG_MCC200           1       /* ... on MCC200 board                  */
  35
  36 #define CFG_MPC5XXX_CLKIN       33000000 /* ... running at 33MHz                */
  37
  38 #define CONFIG_MISC_INIT_R
  39
  40 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH     */
  41 #define BOOTFLAG_WARM           0x02    /* Software reboot                      */
  42
  43 /*
  44  * Serial console configuration
  45  *
  46  *  To select console on the one of 8 external UARTs,
  47  * define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART,
  48  * or as 5, 6, 7, or 8 for the second Quad UART.
  49  * COM11, COM12, COM13, COM14 are located on the second Quad UART.
  50  *
  51  *  CONFIG_PSC_CONSOLE must be undefined in this case.
  52  */
  53 #if !defined(CONFIG_PRS200)
  54 /* MCC200 configuration: */
  55 #ifdef CONFIG_CONSOLE_COM12
  56 #define CONFIG_QUART_CONSOLE    6       /* console is on UARTF of QUART2        */
  57 #else
  58 #define CONFIG_QUART_CONSOLE    8       /* console is on UARTH of QUART2        */
  59 #endif
  60 #else
  61 /* PRS200 configuration: */
  62 #undef CONFIG_QUART_CONSOLE
  63 #endif /* CONFIG_PRS200 */
  64 /*
  65  *  To select console on PSC1, define CONFIG_PSC_CONSOLE as 1
  66  * and undefine CONFIG_QUART_CONSOLE.
  67  */
  68 #if !defined(CONFIG_PRS200)
  69 /* MCC200 configuration: */
  70 #define CONFIG_SERIAL_MULTI     1
  71 #define CONFIG_PSC_CONSOLE      1       /* PSC1 may be COM */
  72 #define CONFIG_PSC_CONSOLE2     2       /* PSC2 is PSoC */
  73 #else
  74 /* PRS200 configuration: */
  75 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1           */
  76 #endif
  77 #if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE) && \
  78         !defined(CONFIG_SERIAL_MULTI)
  79 #error "Select only one console device!"
  80 #endif
  81 #define CONFIG_BAUDRATE         115200
  82 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
  83
  84 #define CONFIG_MII              1
  85
  86 #define CONFIG_DOS_PARTITION
  87
  88 /* USB */
  89 #define CONFIG_USB_OHCI
  90 #define CONFIG_USB_STORAGE
  91 /* automatic software updates (see board/mcc200/auto_update.c) */
  92 #define CONFIG_AUTO_UPDATE 1
  93
  94
  95 /*
  96  * BOOTP options
  97  */
  98 #define CONFIG_BOOTP_BOOTFILESIZE
  99 #define CONFIG_BOOTP_BOOTPATH
 100 #define CONFIG_BOOTP_GATEWAY
 101 #define CONFIG_BOOTP_HOSTNAME
 102
 103
 104 /*
 105  * Command line configuration.
 106  */
 107 #include <config_cmd_default.h>
 108
 109 #define CONFIG_CMD_BEDBUG
 110 #define CONFIG_CMD_FAT
 111 #define CONFIG_CMD_I2C
 112 #define CONFIG_CMD_USB
 113
 114 #undef  CONFIG_CMD_NET
 115
 116
 117 /*
 118  * Autobooting
 119  */
 120 #define CONFIG_BOOTDELAY        1       /* autoboot after 1 second */
 121
 122 #define CONFIG_PREBOOT  "echo;" \
 123         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 124         "echo"
 125
 126 #undef  CONFIG_BOOTARGS
 127
 128 #define XMK_STR(x)              #x
 129 #define MK_STR(x)               XMK_STR(x)
 130
 131 #ifdef CONFIG_PRS200
 132 # define CFG__BOARDNAME         "prs200"
 133 # define CFG__LINUX_CONSOLE     "ttyS0"
 134 #else
 135 # define CFG__BOARDNAME         "mcc200"
 136 # define CFG__LINUX_CONSOLE     "ttyEU5"
 137 #endif
 138
 139 /* Network */
 140 #define CONFIG_ETHADDR  00:17:17:ff:00:00
 141 #define CONFIG_IPADDR   10.76.9.29
 142 #define CONFIG_SERVERIP 10.76.9.1
 143
 144 #include <version.h> /* For U-Boot version */
 145
 146 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 147         "ubootver=" U_BOOT_VERSION "\0"                                 \
 148         "netdev=eth0\0"                                                 \
 149         "hostname=" CFG__BOARDNAME "\0"                                 \
 150         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 151                 "nfsroot=${serverip}:${rootpath}\0"                     \
 152         "ramargs=setenv bootargs root=/dev/mtdblock2 "                  \
 153                 "rootfstype=cramfs\0"                                   \
 154         "addip=setenv bootargs ${bootargs} "                            \
 155                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 156                 ":${hostname}:${netdev}:off panic=1\0"                  \
 157         "addcons=setenv bootargs ${bootargs} "                          \
 158                 "console=${console},${baudrate} "               \
 159                 "ubootver=${ubootver} board=${board}\0" \
 160         "flash_nfs=run nfsargs addip addcons;"                          \
 161                 "bootm ${kernel_addr}\0"                                \
 162         "flash_self=run ramargs addip addcons;"                         \
 163                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 164         "net_nfs=tftp 200000 ${bootfile};"                              \
 165                 "run nfsargs addip addcons;bootm\0"                     \
 166         "console=" CFG__LINUX_CONSOLE "\0"                              \
 167         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 168         "bootfile=/tftpboot/" CFG__BOARDNAME "/uImage\0"                \
 169         "load=tftp 200000 /tftpboot/" CFG__BOARDNAME "/u-boot.bin\0"    \
 170         "text_base=" MK_STR(TEXT_BASE) "\0"                             \
 171         "kernel_addr=0xFC0C0000\0"                                      \
 172         "update=protect off ${text_base} +${filesize};"                 \
 173                 "era ${text_base} +${filesize};"                        \
 174                 "cp.b 200000 ${text_base} ${filesize}\0"                \
 175         "unlock=yes\0"                                                  \
 176         ""
 177 #undef MK_STR
 178 #undef XMK_STR
 179
 180 #define CONFIG_BOOTCOMMAND      "run flash_self"
 181
 182 #define CFG_HUSH_PARSER         1       /* use "hush" command parser    */
 183 #define CFG_PROMPT_HUSH_PS2     "> "
 184
 185 /*
 186  * IPB Bus clocking configuration.
 187  */
 188 #define CFG_IPBCLK_EQUALS_XLBCLK                /* define for 133MHz speed */
 189
 190 /*
 191  * I2C configuration
 192  */
 193 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 194 #define CFG_I2C_MODULE          2       /* Select I2C module #1 or #2 */
 195
 196 #define CFG_I2C_SPEED           100000 /* 100 kHz */
 197 #define CFG_I2C_SLAVE           0x7F
 198
 199 /*
 200  * Flash configuration (8,16 or 32 MB)
 201  * TEXT base always at 0xFFF00000
 202  * ENV_ADDR always at  0xFFF40000
 203  * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!)
 204  *               0xFE000000 for 32 MB
 205  *               0xFF000000 for 16 MB
 206  *               0xFF800000 for  8 MB
 207  */
 208 #define CFG_FLASH_BASE          0xfc000000
 209 #define CFG_FLASH_SIZE          0x04000000
 210
 211 #define CFG_FLASH_CFI                           /* The flash is CFI compatible  */
 212 #define CFG_FLASH_CFI_DRIVER                    /* Use common CFI driver        */
 213
 214 #define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE }
 215
 216 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 217 #define CFG_MAX_FLASH_SECT      512     /* max number of sectors on one chip    */
 218
 219 #define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
 220 #define CFG_FLASH_PROTECTION    1       /* hardware flash protection            */
 221
 222 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 223 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 224
 225 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 226 #define CFG_FLASH_QUIET_TEST    1       /* don't warn upon unknown flash        */
 227
 228 #define CFG_ENV_IS_IN_FLASH     1       /* use FLASH for environment vars       */
 229
 230 #define CFG_ENV_SECT_SIZE       0x40000 /* size of one complete sector  */
 231 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 232 #define CFG_ENV_SIZE            0x2000  /* Total Size of Environment Sector     */
 233
 234 /* Address and size of Redundant Environment Sector     */
 235 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
 236 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 237
 238 #define CONFIG_ENV_OVERWRITE    1       /* allow modification of vendor params */
 239
 240 #if TEXT_BASE == CFG_FLASH_BASE
 241 #define CFG_LOWBOOT     1
 242 #endif
 243
 244 /*
 245  * Memory map
 246  */
 247 #define CFG_MBAR                0xf0000000
 248 #define CFG_SDRAM_BASE          0x00000000
 249 #define CFG_DEFAULT_MBAR        0x80000000
 250
 251 /* Use SRAM until RAM will be available */
 252 #define CFG_INIT_RAM_ADDR       MPC5XXX_SRAM
 253 #define CFG_INIT_RAM_END        MPC5XXX_SRAM_SIZE       /* End of used area in DPRAM */
 254
 255
 256 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 257 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 258 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 259
 260 #define CFG_MONITOR_BASE        TEXT_BASE
 261 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 262 #   define CFG_RAMBOOT          1
 263 #endif
 264
 265 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 266 #define CFG_MALLOC_LEN          (512 << 10)     /* Reserve 512 kB for malloc()  */
 267 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 268
 269 /*
 270  * Ethernet configuration
 271  */
 272 /*#define CONFIG_MPC5xxx_FEC    1*/
 273 /*
 274  * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 275  */
 276 /* #define CONFIG_FEC_10MBIT 1 */
 277 #define CONFIG_PHY_ADDR         1
 278
 279 /*
 280  * LCD Splash Screen
 281  */
 282 #if !defined(CONFIG_PRS200)
 283 #define CONFIG_LCD              1
 284 #define CONFIG_PROGRESSBAR 1
 285 #endif
 286
 287 #if defined(CONFIG_LCD)
 288 #define CONFIG_SPLASH_SCREEN    1
 289 #define CFG_CONSOLE_IS_IN_ENV   1
 290 #define LCD_BPP                 LCD_MONOCHROME
 291 #endif
 292
 293 /*
 294  * GPIO configuration
 295  */
 296 /* 0x10000004 = 32MB SDRAM */
 297 /* 0x90000004 = 64MB SDRAM */
 298 #if defined(CONFIG_LCD)
 299 /* set PSC2 in UART mode */
 300 #define CFG_GPS_PORT_CONFIG     0x00000044
 301 #else
 302 #define CFG_GPS_PORT_CONFIG     0x00000004
 303 #endif
 304
 305 /*
 306  * Miscellaneous configurable options
 307  */
 308 #define CFG_LONGHELP                    /* undef to save memory         */
 309 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
 310 #if defined(CONFIG_CMD_KGDB)
 311 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size      */
 312 #else
 313 #define CFG_CBSIZE              256     /* Console I/O Buffer Size      */
 314 #endif
 315 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size    */
 316 #define CFG_MAXARGS             16              /* max number of command args   */
 317 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 318
 319 #define CFG_MEMTEST_START       0x00100000      /* memtest works on     */
 320 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM  */
 321
 322 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 323
 324 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 325
 326 #define CFG_CACHELINE_SIZE      32      /* For MPC5xxx CPUs                     */
 327 #if defined(CONFIG_CMD_KGDB)
 328 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value        */
 329 #endif
 330
 331 /*
 332  * Various low-level settings
 333  */
 334 #define CFG_HID0_INIT           HID0_ICE | HID0_ICFI
 335 #define CFG_HID0_FINAL          HID0_ICE
 336
 337 #define CFG_BOOTCS_START        CFG_FLASH_BASE
 338 #define CFG_BOOTCS_SIZE         CFG_FLASH_SIZE
 339 #define CFG_BOOTCS_CFG          0x0004fb00
 340 #define CFG_CS0_START           CFG_FLASH_BASE
 341 #define CFG_CS0_SIZE            CFG_FLASH_SIZE
 342
 343 /* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
 344 #define CFG_CS2_START           0x80000000
 345 #define CFG_CS2_SIZE            0x00001000
 346 #define CFG_CS2_CFG             0x1d300
 347
 348 /* Second Quad UART @0x80010000 */
 349 #define CFG_CS1_START           0x80010000
 350 #define CFG_CS1_SIZE            0x00001000
 351 #define CFG_CS1_CFG             0x1d300
 352
 353 /* Leica - build revision resistors */
 354 /*
 355 #define CFG_CS3_START           0x80020000
 356 #define CFG_CS3_SIZE            0x00000004
 357 #define CFG_CS3_CFG             0x1d300
 358 */
 359
 360 /*
 361  *  Select one of quarts as a default
 362  * console. If undefined - PSC console
 363  * wil be default
 364  */
 365 #define CFG_CS_BURST            0x00000000
 366 #define CFG_CS_DEADCYCLE        0x33333333
 367
 368 #define CFG_RESET_ADDRESS       0xff000000
 369
 370 /*
 371  * QUART Expanders support
 372  */
 373 #if defined(CONFIG_QUART_CONSOLE)
 374 /*
 375  * We'll use NS16550 chip routines,
 376  */
 377 #define CFG_NS16550             1
 378 #define CFG_NS16550_SERIAL      1
 379 #define CONFIG_CONS_INDEX       1
 380 /*
 381  *  To achieve necessary offset on SC16C554
 382  * A0-A2 (register select) pins with NS16550
 383  * functions (in struct NS16550), REG_SIZE
 384  * should be 4, because A0-A2 pins are connected
 385  * to DA2-DA4 address bus lines.
 386  */
 387 #define CFG_NS16550_REG_SIZE    4
 388 /*
 389  * LocalPlus Bus already inited in cpu_init_f(),
 390  * so can work with QUART's chip selects.
 391  * One of four SC16C554 UARTs is selected with
 392  * A3-A4 (DA5-DA6) lines.
 393  */
 394 #if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200)
 395 #define CFG_NS16550_COM1        (CFG_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5)
 396 #elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9)
 397 #define CFG_NS16550_COM1        (CFG_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5)
 398 #elif
 399 #error "Wrong QUART expander number."
 400 #endif
 401
 402 /*
 403  * SC16C554 chip's external crystal oscillator frequency
 404  * is 7.3728 MHz
 405  */
 406 #define CFG_NS16550_CLK         7372800
 407 #endif /* CONFIG_QUART_CONSOLE */
 408 /*-----------------------------------------------------------------------
 409  * USB stuff
 410  *-----------------------------------------------------------------------
 411  */
 412 #define CONFIG_USB_CLOCK        0x0001BBBB
 413 #define CONFIG_USB_CONFIG       0x00005000
 414
 415 #define CONFIG_AUTOBOOT_KEYED           /* use key strings to stop autoboot     */
 416 #define CONFIG_AUTOBOOT_STOP_STR        "432"
 417 #define CONFIG_SILENT_CONSOLE   1
 418
 419 #endif /* __CONFIG_H */