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Move CONFIG_OF_LIBFDT to Kconfig
[people/ms/u-boot.git] / include / configs / mcx.h
1 /*
2 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
3 *
4 * Based on omap3_evm_config.h
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11
12 /*
13 * High Level Configuration Options
14 */
15 #define CONFIG_OMAP /* in a TI OMAP core */
16 #define CONFIG_OMAP3_MCX /* working with mcx */
17 #define CONFIG_OMAP_GPIO
18 #define CONFIG_OMAP_COMMON
19 /* Common ARM Erratas */
20 #define CONFIG_ARM_ERRATA_454179
21 #define CONFIG_ARM_ERRATA_430973
22 #define CONFIG_ARM_ERRATA_621766
23
24 #define MACH_TYPE_MCX 3656
25 #define CONFIG_MACH_TYPE MACH_TYPE_MCX
26 #define CONFIG_BOARD_LATE_INIT
27
28
29 #define CONFIG_SYS_CACHELINE_SIZE 64
30
31 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
32
33 #include <asm/arch/cpu.h> /* get chip and board defs */
34 #include <asm/arch/omap.h>
35
36 #define CONFIG_FIT
37
38 /*
39 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
40 * and older u-boot.bin with the new U-Boot SPL.
41 */
42 #define CONFIG_SYS_TEXT_BASE 0x80008000
43
44 /*
45 * Display CPU and Board information
46 */
47 #define CONFIG_DISPLAY_CPUINFO
48 #define CONFIG_DISPLAY_BOARDINFO
49
50 /* Clock Defines */
51 #define V_OSCK 26000000 /* Clock output from T2 */
52 #define V_SCLK (V_OSCK >> 1)
53
54 #define CONFIG_MISC_INIT_R
55
56 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
57 #define CONFIG_SETUP_MEMORY_TAGS
58 #define CONFIG_INITRD_TAG
59 #define CONFIG_REVISION_TAG
60
61 /*
62 * Size of malloc() pool
63 */
64 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
65 #define CONFIG_SYS_MALLOC_LEN (1024 << 10)
66 /*
67 * DDR related
68 */
69 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
70
71 /*
72 * Hardware drivers
73 */
74
75 /*
76 * NS16550 Configuration
77 */
78 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
79
80 #define CONFIG_SYS_NS16550_SERIAL
81 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
82 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
83
84 /*
85 * select serial console configuration
86 */
87 #define CONFIG_CONS_INDEX 3
88 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
89 #define CONFIG_SERIAL3 3 /* UART3 */
90
91 /* allow to overwrite serial and ethaddr */
92 #define CONFIG_ENV_OVERWRITE
93 #define CONFIG_BAUDRATE 115200
94 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
95 115200}
96 #define CONFIG_MMC
97 #define CONFIG_OMAP_HSMMC
98 #define CONFIG_GENERIC_MMC
99 #define CONFIG_DOS_PARTITION
100
101 /* EHCI */
102 #define CONFIG_USB_STORAGE
103 #define CONFIG_OMAP3_GPIO_2
104 #define CONFIG_OMAP3_GPIO_5
105 #define CONFIG_USB_EHCI
106 #define CONFIG_USB_EHCI_OMAP
107 #define CONFIG_USB_ULPI
108 #define CONFIG_USB_ULPI_VIEWPORT_OMAP
109 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57
110 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
111 #define CONFIG_USB_HOST_ETHER
112 #define CONFIG_USB_ETHER_ASIX
113 #define CONFIG_USB_ETHER_MCS7830
114
115 /* commands to include */
116 #define CONFIG_CMD_EXT2 /* EXT2 Support */
117 #define CONFIG_CMD_FAT /* FAT support */
118 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
119
120 #define CONFIG_CMD_DATE
121 #define CONFIG_CMD_I2C /* I2C serial bus support */
122 #define CONFIG_CMD_MMC /* MMC support */
123 #define CONFIG_CMD_FAT /* FAT support */
124 #define CONFIG_CMD_USB
125 #define CONFIG_CMD_NAND /* NAND support */
126 #define CONFIG_CMD_DHCP
127 #define CONFIG_CMD_PING
128 #define CONFIG_CMD_CACHE
129 #define CONFIG_CMD_UBI
130 #define CONFIG_CMD_UBIFS
131 #define CONFIG_RBTREE
132 #define CONFIG_LZO
133 #define CONFIG_MTD_PARTITIONS
134 #define CONFIG_MTD_DEVICE
135 #define CONFIG_CMD_MTDPARTS
136
137 #define CONFIG_SYS_NO_FLASH
138 #define CONFIG_SYS_I2C
139 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
140 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
141 #define CONFIG_SYS_I2C_OMAP34XX
142
143 /* RTC */
144 #define CONFIG_RTC_DS1337
145 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
146
147 #define CONFIG_CMD_MII
148 /*
149 * Board NAND Info.
150 */
151 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
152 /* to access nand */
153 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
154 /* to access */
155 /* nand at CS0 */
156
157 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
158 /* NAND devices */
159 #define CONFIG_JFFS2_NAND
160 /* nand device jffs2 lives on */
161 #define CONFIG_JFFS2_DEV "nand0"
162 /* start of jffs2 partition */
163 #define CONFIG_JFFS2_PART_OFFSET 0x680000
164 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
165
166 /* Environment information */
167 #define CONFIG_BOOTDELAY 3
168
169 #define CONFIG_BOOTFILE "uImage"
170
171 /* Setup MTD for NAND on the SOM */
172 #define MTDIDS_DEFAULT "nand0=omap2-nand.0"
173 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \
174 "1m(u-boot),256k(env1)," \
175 "256k(env2),6m(kernel),6m(k_recovery)," \
176 "8m(fs_recovery),-(common_data)"
177
178 #define CONFIG_HOSTNAME mcx
179 #define CONFIG_EXTRA_ENV_SETTINGS \
180 "adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \
181 "adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \
182 "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
183 "addfb=setenv bootargs ${bootargs} vram=6M " \
184 "omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \
185 "addip_sta=setenv bootargs ${bootargs} " \
186 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
187 "${netmask}:${hostname}:eth0:off\0" \
188 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
189 "addip=if test -n ${ipdyn};then run addip_dyn;" \
190 "else run addip_sta;fi\0" \
191 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
192 "addtty=setenv bootargs ${bootargs} " \
193 "console=${consoledev},${baudrate}\0" \
194 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
195 "baudrate=115200\0" \
196 "consoledev=ttyO2\0" \
197 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
198 "loadaddr=0x82000000\0" \
199 "load=tftp ${loadaddr} ${u-boot}\0" \
200 "load_k=tftp ${loadaddr} ${bootfile}\0" \
201 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
202 "loadmlo=tftp ${loadaddr} ${mlo}\0" \
203 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \
204 "mmcargs=root=/dev/mmcblk0p2 rw " \
205 "rootfstype=ext3 rootwait\0" \
206 "mmcboot=echo Booting from mmc ...; " \
207 "run mmcargs; " \
208 "run addip addtty addmtd addfb addeth addmisc;" \
209 "run loaduimage; " \
210 "bootm ${loadaddr}\0" \
211 "net_nfs=run load_k; " \
212 "run nfsargs; " \
213 "run addip addtty addmtd addfb addeth addmisc;" \
214 "bootm ${loadaddr}\0" \
215 "nfsargs=setenv bootargs root=/dev/nfs rw " \
216 "nfsroot=${serverip}:${rootpath}\0" \
217 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \
218 "uboot_addr=0x80000\0" \
219 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \
220 "nand write ${loadaddr} ${uboot_addr} 80000\0" \
221 "updatemlo=nandecc hw;nand erase 0 20000;" \
222 "nand write ${loadaddr} 0 20000\0" \
223 "upd=if run load;then echo Updating u-boot;if run update;" \
224 "then echo U-Boot updated;" \
225 "else echo Error updating u-boot !;" \
226 "echo Board without bootloader !!;" \
227 "fi;" \
228 "else echo U-Boot not downloaded..exiting;fi\0" \
229 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
230 "bootscript=echo Running bootscript from mmc ...; " \
231 "source ${loadaddr}\0" \
232 "nandargs=setenv bootargs ubi.mtd=7 " \
233 "root=ubi0:rootfs rootfstype=ubifs\0" \
234 "nandboot=echo Booting from nand ...; " \
235 "run nandargs; " \
236 "ubi part nand0,4;" \
237 "ubi readvol ${loadaddr} kernel;" \
238 "run addtty addmtd addfb addeth addmisc;" \
239 "bootm ${loadaddr}\0" \
240 "preboot=ubi part nand0,7;" \
241 "ubi readvol ${loadaddr} splash;" \
242 "bmp display ${loadaddr};" \
243 "gpio set 55\0" \
244 "swupdate_args=setenv bootargs root=/dev/ram " \
245 "quiet loglevel=1 " \
246 "consoleblank=0 ${swupdate_misc}\0" \
247 "swupdate=echo Running Sw-Update...;" \
248 "if printenv mtdparts;then echo Starting SwUpdate...; " \
249 "else mtdparts default;fi; " \
250 "ubi part nand0,5;" \
251 "ubi readvol 0x82000000 kernel_recovery;" \
252 "ubi part nand0,6;" \
253 "ubi readvol 0x84000000 fs_recovery;" \
254 "run swupdate_args; " \
255 "setenv bootargs ${bootargs} " \
256 "${mtdparts} " \
257 "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \
258 "omapdss.def_disp=lcd;" \
259 "bootm 0x82000000 0x84000000\0" \
260 "bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \
261 "then source 82000000;else run nandboot;fi\0"
262
263 #define CONFIG_AUTO_COMPLETE
264 #define CONFIG_CMDLINE_EDITING
265
266 /*
267 * Miscellaneous configurable options
268 */
269 #define CONFIG_SYS_LONGHELP /* undef to save memory */
270 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
271 #define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */
272 /* Print Buffer Size */
273 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
274 sizeof(CONFIG_SYS_PROMPT) + 16)
275 #define CONFIG_SYS_MAXARGS 16 /* max number of command */
276 /* args */
277 /* Boot Argument Buffer Size */
278 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
279 /* memtest works on */
280 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
281 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
282 0x01F00000) /* 31MB */
283
284 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
285 /* address */
286 #define CONFIG_PREBOOT
287
288 /*
289 * AM3517 has 12 GP timers, they can be driven by the system clock
290 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
291 * This rate is divided by a local divisor.
292 */
293 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
294 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
295
296 /*
297 * Physical Memory Map
298 */
299 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
300 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
301 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
302
303 /*
304 * FLASH and environment organization
305 */
306
307 /* **** PISMO SUPPORT *** */
308 #define CONFIG_NAND
309 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
310 #define CONFIG_NAND_OMAP_GPMC
311 #define CONFIG_NAND_OMAP_GPMC_PREFETCH
312 #define CONFIG_ENV_IS_IN_NAND
313 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
314
315 /* Redundant Environment */
316 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
317 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
318 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
319 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
320 2 * CONFIG_SYS_ENV_SECT_SIZE)
321 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
322
323 /* Flash banks JFFS2 should use */
324 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
325 CONFIG_SYS_MAX_NAND_DEVICE)
326 #define CONFIG_SYS_JFFS2_MEM_NAND
327 /* use flash_info[2] */
328 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
329 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
330
331 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
332 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
333 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
334 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
335 CONFIG_SYS_INIT_RAM_SIZE - \
336 GENERATED_GBL_DATA_SIZE)
337
338 /* Defines for SPL */
339 #define CONFIG_SPL_FRAMEWORK
340 #define CONFIG_SPL_BOARD_INIT
341 #define CONFIG_SPL_NAND_SIMPLE
342
343 #define CONFIG_SPL_LIBCOMMON_SUPPORT
344 #define CONFIG_SPL_LIBDISK_SUPPORT
345 #define CONFIG_SPL_I2C_SUPPORT
346 #define CONFIG_SPL_MMC_SUPPORT
347 #define CONFIG_SPL_FAT_SUPPORT
348 #define CONFIG_SPL_LIBGENERIC_SUPPORT
349 #define CONFIG_SPL_SERIAL_SUPPORT
350 #define CONFIG_SPL_POWER_SUPPORT
351 #define CONFIG_SPL_NAND_SUPPORT
352 #define CONFIG_SPL_NAND_BASE
353 #define CONFIG_SPL_NAND_DRIVERS
354 #define CONFIG_SPL_NAND_ECC
355 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
356
357 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
358 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
359 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
360
361 /* move malloc and bss high to prevent clashing with the main image */
362 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
363 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
364 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
365 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
366
367 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
368 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
369 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
370
371 /* NAND boot config */
372 #define CONFIG_SYS_NAND_PAGE_COUNT 64
373 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
374 #define CONFIG_SYS_NAND_OOBSIZE 64
375 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
376 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
377 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
378 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
379 48, 49, 50, 51, 52, 53, 54, 55,\
380 56, 57, 58, 59, 60, 61, 62, 63}
381 #define CONFIG_SYS_NAND_ECCSIZE 256
382 #define CONFIG_SYS_NAND_ECCBYTES 3
383 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
384 #define CONFIG_SPL_NAND_SOFTECC
385
386 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
387
388 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
389
390 /*
391 * ethernet support
392 *
393 */
394 #if defined(CONFIG_CMD_NET)
395 #define CONFIG_DRIVER_TI_EMAC
396 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
397 #define CONFIG_MII
398 #define CONFIG_BOOTP_DNS
399 #define CONFIG_BOOTP_DNS2
400 #define CONFIG_BOOTP_SEND_HOSTNAME
401 #define CONFIG_NET_RETRY_COUNT 10
402 #endif
403
404 #define CONFIG_VIDEO
405 #define CONFIG_CFB_CONSOLE
406 #define CONFIG_VGA_AS_SINGLE_DEVICE
407 #define CONFIG_SPLASH_SCREEN
408 #define CONFIG_VIDEO_BMP_RLE8
409 #define CONFIG_CMD_BMP
410 #define CONFIG_VIDEO_OMAP3
411 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
412
413 #endif /* __CONFIG_H */