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Convert CONFIG_BOOTP_BOOTPATH et al to Kconfig
[people/ms/u-boot.git] / include / configs / mcx.h
1 /*
2 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
3 *
4 * Based on omap3_evm_config.h
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11
12 /*
13 * High Level Configuration Options
14 */
15
16 #define CONFIG_MACH_TYPE MACH_TYPE_MCX
17
18 #include <asm/arch/cpu.h> /* get chip and board defs */
19 #include <asm/arch/omap.h>
20
21 /*
22 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
23 * and older u-boot.bin with the new U-Boot SPL.
24 */
25
26 /* Clock Defines */
27 #define V_OSCK 26000000 /* Clock output from T2 */
28 #define V_SCLK (V_OSCK >> 1)
29
30 #define CONFIG_MISC_INIT_R
31
32 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
33 #define CONFIG_SETUP_MEMORY_TAGS
34 #define CONFIG_INITRD_TAG
35 #define CONFIG_REVISION_TAG
36
37 /*
38 * Size of malloc() pool
39 */
40 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
41 #define CONFIG_SYS_MALLOC_LEN (1024 << 10)
42 /*
43 * DDR related
44 */
45 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
46
47 /*
48 * Hardware drivers
49 */
50
51 /*
52 * NS16550 Configuration
53 */
54 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
55
56 #define CONFIG_SYS_NS16550_SERIAL
57 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
58 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
59
60 /*
61 * select serial console configuration
62 */
63 #define CONFIG_CONS_INDEX 3
64 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
65 #define CONFIG_SERIAL3 3 /* UART3 */
66
67 /* allow to overwrite serial and ethaddr */
68 #define CONFIG_ENV_OVERWRITE
69 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
70 115200}
71
72 /* EHCI */
73 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57
74
75 /* commands to include */
76
77 #define CONFIG_MTD_PARTITIONS
78 #define CONFIG_MTD_DEVICE
79
80 #define CONFIG_SYS_I2C
81
82 /* RTC */
83 #define CONFIG_RTC_DS1337
84 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
85
86 /*
87 * Board NAND Info.
88 */
89 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
90 /* to access nand */
91 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
92 /* to access */
93 /* nand at CS0 */
94
95 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
96 /* NAND devices */
97 #define CONFIG_JFFS2_NAND
98 /* nand device jffs2 lives on */
99 #define CONFIG_JFFS2_DEV "nand0"
100 /* start of jffs2 partition */
101 #define CONFIG_JFFS2_PART_OFFSET 0x680000
102 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
103
104 /* Environment information */
105
106 #define CONFIG_BOOTFILE "uImage"
107
108 /* Setup MTD for NAND on the SOM */
109
110 #define CONFIG_HOSTNAME mcx
111 #define CONFIG_EXTRA_ENV_SETTINGS \
112 "adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \
113 "adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \
114 "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
115 "addfb=setenv bootargs ${bootargs} vram=6M " \
116 "omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \
117 "addip_sta=setenv bootargs ${bootargs} " \
118 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
119 "${netmask}:${hostname}:eth0:off\0" \
120 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
121 "addip=if test -n ${ipdyn};then run addip_dyn;" \
122 "else run addip_sta;fi\0" \
123 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
124 "addtty=setenv bootargs ${bootargs} " \
125 "console=${consoledev},${baudrate}\0" \
126 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
127 "baudrate=115200\0" \
128 "consoledev=ttyO2\0" \
129 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
130 "loadaddr=0x82000000\0" \
131 "load=tftp ${loadaddr} ${u-boot}\0" \
132 "load_k=tftp ${loadaddr} ${bootfile}\0" \
133 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
134 "loadmlo=tftp ${loadaddr} ${mlo}\0" \
135 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \
136 "mmcargs=root=/dev/mmcblk0p2 rw " \
137 "rootfstype=ext3 rootwait\0" \
138 "mmcboot=echo Booting from mmc ...; " \
139 "run mmcargs; " \
140 "run addip addtty addmtd addfb addeth addmisc;" \
141 "run loaduimage; " \
142 "bootm ${loadaddr}\0" \
143 "net_nfs=run load_k; " \
144 "run nfsargs; " \
145 "run addip addtty addmtd addfb addeth addmisc;" \
146 "bootm ${loadaddr}\0" \
147 "nfsargs=setenv bootargs root=/dev/nfs rw " \
148 "nfsroot=${serverip}:${rootpath}\0" \
149 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \
150 "uboot_addr=0x80000\0" \
151 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \
152 "nand write ${loadaddr} ${uboot_addr} 80000\0" \
153 "updatemlo=nandecc hw;nand erase 0 20000;" \
154 "nand write ${loadaddr} 0 20000\0" \
155 "upd=if run load;then echo Updating u-boot;if run update;" \
156 "then echo U-Boot updated;" \
157 "else echo Error updating u-boot !;" \
158 "echo Board without bootloader !!;" \
159 "fi;" \
160 "else echo U-Boot not downloaded..exiting;fi\0" \
161 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
162 "bootscript=echo Running bootscript from mmc ...; " \
163 "source ${loadaddr}\0" \
164 "nandargs=setenv bootargs ubi.mtd=7 " \
165 "root=ubi0:rootfs rootfstype=ubifs\0" \
166 "nandboot=echo Booting from nand ...; " \
167 "run nandargs; " \
168 "ubi part nand0,4;" \
169 "ubi readvol ${loadaddr} kernel;" \
170 "run addtty addmtd addfb addeth addmisc;" \
171 "bootm ${loadaddr}\0" \
172 "preboot=ubi part nand0,7;" \
173 "ubi readvol ${loadaddr} splash;" \
174 "bmp display ${loadaddr};" \
175 "gpio set 55\0" \
176 "swupdate_args=setenv bootargs root=/dev/ram " \
177 "quiet loglevel=1 " \
178 "consoleblank=0 ${swupdate_misc}\0" \
179 "swupdate=echo Running Sw-Update...;" \
180 "if printenv mtdparts;then echo Starting SwUpdate...; " \
181 "else mtdparts default;fi; " \
182 "ubi part nand0,5;" \
183 "ubi readvol 0x82000000 kernel_recovery;" \
184 "ubi part nand0,6;" \
185 "ubi readvol 0x84000000 fs_recovery;" \
186 "run swupdate_args; " \
187 "setenv bootargs ${bootargs} " \
188 "${mtdparts} " \
189 "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \
190 "omapdss.def_disp=lcd;" \
191 "bootm 0x82000000 0x84000000\0" \
192 "bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \
193 "then source 82000000;else run nandboot;fi\0"
194
195 /*
196 * Miscellaneous configurable options
197 */
198 #define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */
199 /* Boot Argument Buffer Size */
200 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
201 /* memtest works on */
202 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
203 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
204 0x01F00000) /* 31MB */
205
206 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
207 /* address */
208 #define CONFIG_PREBOOT
209
210 /*
211 * AM3517 has 12 GP timers, they can be driven by the system clock
212 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
213 * This rate is divided by a local divisor.
214 */
215 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
216 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
217
218 /*
219 * Physical Memory Map
220 */
221 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
222 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
223 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
224
225 /*
226 * FLASH and environment organization
227 */
228
229 /* **** PISMO SUPPORT *** */
230
231 /* Redundant Environment */
232 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
233 #define CONFIG_ENV_OFFSET 0x180000
234 #define CONFIG_ENV_ADDR 0x180000
235 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
236 2 * CONFIG_SYS_ENV_SECT_SIZE)
237 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
238
239 /* Flash banks JFFS2 should use */
240 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
241 CONFIG_SYS_MAX_NAND_DEVICE)
242 #define CONFIG_SYS_JFFS2_MEM_NAND
243 /* use flash_info[2] */
244 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
245 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
246
247 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
248 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
249 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
250 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
251 CONFIG_SYS_INIT_RAM_SIZE - \
252 GENERATED_GBL_DATA_SIZE)
253
254 /* Defines for SPL */
255
256 #define CONFIG_SPL_NAND_BASE
257 #define CONFIG_SPL_NAND_DRIVERS
258 #define CONFIG_SPL_NAND_ECC
259
260 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
261 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
262 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
263
264 /* move malloc and bss high to prevent clashing with the main image */
265 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
266 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
267 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
268 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
269
270 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
271 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
272
273 /* NAND boot config */
274 #define CONFIG_SYS_NAND_PAGE_COUNT 64
275 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
276 #define CONFIG_SYS_NAND_OOBSIZE 64
277 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
278 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
279 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
280 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
281 48, 49, 50, 51, 52, 53, 54, 55,\
282 56, 57, 58, 59, 60, 61, 62, 63}
283 #define CONFIG_SYS_NAND_ECCSIZE 256
284 #define CONFIG_SYS_NAND_ECCBYTES 3
285 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
286 #define CONFIG_SPL_NAND_SOFTECC
287
288 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
289
290 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
291
292 /*
293 * ethernet support
294 *
295 */
296 #if defined(CONFIG_CMD_NET)
297 #define CONFIG_DRIVER_TI_EMAC
298 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
299 #define CONFIG_MII
300 #define CONFIG_BOOTP_DNS2
301 #define CONFIG_BOOTP_SEND_HOSTNAME
302 #define CONFIG_NET_RETRY_COUNT 10
303 #endif
304
305 #define CONFIG_SPLASH_SCREEN
306 #define CONFIG_VIDEO_BMP_RLE8
307 #define CONFIG_VIDEO_OMAP3
308
309 #endif /* __CONFIG_H */