include/configs/mcx.h

   1 /*
   2  * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
   3  *
   4  * Based on omap3_evm_config.h
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_OMAP                     /* in a TI OMAP core */
  16 #define CONFIG_OMAP3_MCX                /* working with mcx */
  17 #define CONFIG_OMAP_GPIO
  18
  19 #define CONFIG_MACH_TYPE        MACH_TYPE_MCX
  20
  21 #define CONFIG_EMIF4    /* The chip has EMIF4 controller */
  22
  23 #include <asm/arch/cpu.h>               /* get chip and board defs */
  24 #include <asm/arch/omap.h>
  25
  26 /*
  27  * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
  28  * and older u-boot.bin with the new U-Boot SPL.
  29  */
  30 #define CONFIG_SYS_TEXT_BASE            0x80008000
  31
  32 /* Clock Defines */
  33 #define V_OSCK                  26000000        /* Clock output from T2 */
  34 #define V_SCLK                  (V_OSCK >> 1)
  35
  36 #define CONFIG_MISC_INIT_R
  37
  38 #define CONFIG_CMDLINE_TAG                      /* enable passing of ATAGs */
  39 #define CONFIG_SETUP_MEMORY_TAGS
  40 #define CONFIG_INITRD_TAG
  41 #define CONFIG_REVISION_TAG
  42
  43 /*
  44  * Size of malloc() pool
  45  */
  46 #define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB sector */
  47 #define CONFIG_SYS_MALLOC_LEN           (1024 << 10)
  48 /*
  49  * DDR related
  50  */
  51 #define CONFIG_SYS_CS0_SIZE             (256 * 1024 * 1024)
  52
  53 /*
  54  * Hardware drivers
  55  */
  56
  57 /*
  58  * NS16550 Configuration
  59  */
  60 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  61
  62 #define CONFIG_SYS_NS16550_SERIAL
  63 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  64 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  65
  66 /*
  67  * select serial console configuration
  68  */
  69 #define CONFIG_CONS_INDEX               3
  70 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  71 #define CONFIG_SERIAL3                  3       /* UART3 */
  72
  73 /* allow to overwrite serial and ethaddr */
  74 #define CONFIG_ENV_OVERWRITE
  75 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  76                                         115200}
  77
  78 /* EHCI */
  79 #define CONFIG_OMAP3_GPIO_2
  80 #define CONFIG_OMAP3_GPIO_5
  81 #define CONFIG_USB_EHCI
  82 #define CONFIG_USB_EHCI_OMAP
  83 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO        57
  84 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
  85 #define CONFIG_USB_HOST_ETHER
  86 #define CONFIG_USB_ETHER_ASIX
  87 #define CONFIG_USB_ETHER_MCS7830
  88
  89 /* commands to include */
  90 #define CONFIG_CMD_JFFS2        /* JFFS2 Support                */
  91
  92 #define CONFIG_CMD_NAND         /* NAND support                 */
  93 #define CONFIG_CMD_UBIFS
  94 #define CONFIG_RBTREE
  95 #define CONFIG_LZO
  96 #define CONFIG_MTD_PARTITIONS
  97 #define CONFIG_MTD_DEVICE
  98 #define CONFIG_CMD_MTDPARTS
  99
 100 #define CONFIG_SYS_I2C
 101 #define CONFIG_SYS_OMAP24_I2C_SPEED     100000
 102 #define CONFIG_SYS_OMAP24_I2C_SLAVE     1
 103 #define CONFIG_SYS_I2C_OMAP34XX
 104
 105 /* RTC */
 106 #define CONFIG_RTC_DS1337
 107 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 108
 109 /*
 110  * Board NAND Info.
 111  */
 112 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 113                                                         /* to access nand */
 114 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 115                                                         /* to access */
 116                                                         /* nand at CS0 */
 117
 118 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of */
 119                                                         /* NAND devices */
 120 #define CONFIG_JFFS2_NAND
 121 /* nand device jffs2 lives on */
 122 #define CONFIG_JFFS2_DEV                "nand0"
 123 /* start of jffs2 partition */
 124 #define CONFIG_JFFS2_PART_OFFSET        0x680000
 125 #define CONFIG_JFFS2_PART_SIZE          0xf980000       /* sz of jffs2 part */
 126
 127 /* Environment information */
 128
 129 #define CONFIG_BOOTFILE         "uImage"
 130
 131 /* Setup MTD for NAND on the SOM */
 132 #define MTDIDS_DEFAULT          "nand0=omap2-nand.0"
 133 #define MTDPARTS_DEFAULT        "mtdparts=omap2-nand.0:512k(MLO),"      \
 134                                 "1m(u-boot),256k(env1),"                \
 135                                 "256k(env2),6m(kernel),6m(k_recovery)," \
 136                                 "8m(fs_recovery),-(common_data)"
 137
 138 #define CONFIG_HOSTNAME mcx
 139 #define CONFIG_EXTRA_ENV_SETTINGS \
 140         "adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0"       \
 141         "adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0"     \
 142         "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0"       \
 143         "addfb=setenv bootargs ${bootargs} vram=6M "                    \
 144                 "omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0"     \
 145         "addip_sta=setenv bootargs ${bootargs} "                        \
 146                 "ip=${ipaddr}:${serverip}:${gatewayip}:"                \
 147                 "${netmask}:${hostname}:eth0:off\0"                     \
 148         "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"               \
 149         "addip=if test -n ${ipdyn};then run addip_dyn;"                 \
 150                 "else run addip_sta;fi\0"                               \
 151         "addmisc=setenv bootargs ${bootargs} ${misc}\0"                 \
 152         "addtty=setenv bootargs ${bootargs} "                           \
 153                 "console=${consoledev},${baudrate}\0"                   \
 154         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
 155         "baudrate=115200\0"                                             \
 156         "consoledev=ttyO2\0"                                            \
 157         "hostname=" __stringify(CONFIG_HOSTNAME) "\0"                   \
 158         "loadaddr=0x82000000\0"                                         \
 159         "load=tftp ${loadaddr} ${u-boot}\0"                             \
 160         "load_k=tftp ${loadaddr} ${bootfile}\0"                         \
 161         "loaduimage=fatload mmc 0 ${loadaddr} uImage\0"                 \
 162         "loadmlo=tftp ${loadaddr} ${mlo}\0"                             \
 163         "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0"                    \
 164         "mmcargs=root=/dev/mmcblk0p2 rw "                               \
 165                 "rootfstype=ext3 rootwait\0"                            \
 166         "mmcboot=echo Booting from mmc ...; "                           \
 167                 "run mmcargs; "                                         \
 168                 "run addip addtty addmtd addfb addeth addmisc;"         \
 169                 "run loaduimage; "                                      \
 170                 "bootm ${loadaddr}\0"                                   \
 171         "net_nfs=run load_k; "                                          \
 172                 "run nfsargs; "                                         \
 173                 "run addip addtty addmtd addfb addeth addmisc;"         \
 174                 "bootm ${loadaddr}\0"                                   \
 175         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 176                 "nfsroot=${serverip}:${rootpath}\0"                     \
 177         "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0"          \
 178         "uboot_addr=0x80000\0"                                          \
 179         "update=nandecc sw;nand erase ${uboot_addr} 100000;"            \
 180                 "nand write ${loadaddr} ${uboot_addr} 80000\0"          \
 181         "updatemlo=nandecc hw;nand erase 0 20000;"                      \
 182                 "nand write ${loadaddr} 0 20000\0"                      \
 183         "upd=if run load;then echo Updating u-boot;if run update;"      \
 184                 "then echo U-Boot updated;"                             \
 185                         "else echo Error updating u-boot !;"            \
 186                         "echo Board without bootloader !!;"             \
 187                 "fi;"                                                   \
 188                 "else echo U-Boot not downloaded..exiting;fi\0"         \
 189         "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0"           \
 190         "bootscript=echo Running bootscript from mmc ...; "             \
 191                 "source ${loadaddr}\0"                                  \
 192         "nandargs=setenv bootargs ubi.mtd=7 "                           \
 193                 "root=ubi0:rootfs rootfstype=ubifs\0"                   \
 194         "nandboot=echo Booting from nand ...; "                         \
 195                 "run nandargs; "                                        \
 196                 "ubi part nand0,4;"                                     \
 197                 "ubi readvol ${loadaddr} kernel;"                       \
 198                 "run addtty addmtd addfb addeth addmisc;"               \
 199                 "bootm ${loadaddr}\0"                                   \
 200         "preboot=ubi part nand0,7;"                                     \
 201                 "ubi readvol ${loadaddr} splash;"                       \
 202                 "bmp display ${loadaddr};"                              \
 203                 "gpio set 55\0"                                         \
 204         "swupdate_args=setenv bootargs root=/dev/ram "                  \
 205                 "quiet loglevel=1 "                                     \
 206                 "consoleblank=0 ${swupdate_misc}\0"                     \
 207         "swupdate=echo Running Sw-Update...;"                           \
 208                 "if printenv mtdparts;then echo Starting SwUpdate...; " \
 209                 "else mtdparts default;fi; "                            \
 210                 "ubi part nand0,5;"                                     \
 211                 "ubi readvol 0x82000000 kernel_recovery;"               \
 212                 "ubi part nand0,6;"                                     \
 213                 "ubi readvol 0x84000000 fs_recovery;"                   \
 214                 "run swupdate_args; "                                   \
 215                 "setenv bootargs ${bootargs} "                          \
 216                         "${mtdparts} "                                  \
 217                         "vram=6M omapfb.vram=1:2M,2:2M,3:2M "           \
 218                         "omapdss.def_disp=lcd;"                         \
 219                 "bootm 0x82000000 0x84000000\0"                         \
 220         "bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \
 221                 "then source 82000000;else run nandboot;fi\0"
 222
 223 #define CONFIG_AUTO_COMPLETE
 224 #define CONFIG_CMDLINE_EDITING
 225
 226 /*
 227  * Miscellaneous configurable options
 228  */
 229 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 230 #define CONFIG_SYS_CBSIZE               1024/* Console I/O Buffer Size */
 231 /* Print Buffer Size */
 232 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 233                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 234 #define CONFIG_SYS_MAXARGS              16      /* max number of command */
 235                                                 /* args */
 236 /* Boot Argument Buffer Size */
 237 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 238 /* memtest works on */
 239 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0)
 240 #define CONFIG_SYS_MEMTEST_END          (OMAP34XX_SDRC_CS0 + \
 241                                         0x01F00000) /* 31MB */
 242
 243 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0) /* default load */
 244                                                                 /* address */
 245 #define CONFIG_PREBOOT
 246
 247 /*
 248  * AM3517 has 12 GP timers, they can be driven by the system clock
 249  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 250  * This rate is divided by a local divisor.
 251  */
 252 #define CONFIG_SYS_TIMERBASE            OMAP34XX_GPT2
 253 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 254
 255 /*
 256  * Physical Memory Map
 257  */
 258 #define CONFIG_NR_DRAM_BANKS    2       /* CS1 may or may not be populated */
 259 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 260 #define PHYS_SDRAM_2            OMAP34XX_SDRC_CS1
 261
 262 /*
 263  * FLASH and environment organization
 264  */
 265
 266 /* **** PISMO SUPPORT *** */
 267 #define CONFIG_NAND
 268 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
 269 #define CONFIG_NAND_OMAP_GPMC
 270 #define CONFIG_NAND_OMAP_GPMC_PREFETCH
 271 #define CONFIG_ENV_IS_IN_NAND
 272 #define SMNAND_ENV_OFFSET               0x180000 /* environment starts here */
 273
 274 /* Redundant Environment */
 275 #define CONFIG_SYS_ENV_SECT_SIZE        (128 << 10)     /* 128 KiB */
 276 #define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
 277 #define CONFIG_ENV_ADDR                 SMNAND_ENV_OFFSET
 278 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 279                                                 2 * CONFIG_SYS_ENV_SECT_SIZE)
 280 #define CONFIG_ENV_SIZE_REDUND          CONFIG_ENV_SIZE
 281
 282 /* Flash banks JFFS2 should use */
 283 #define CONFIG_SYS_MAX_MTD_BANKS        (CONFIG_SYS_MAX_FLASH_BANKS + \
 284                                         CONFIG_SYS_MAX_NAND_DEVICE)
 285 #define CONFIG_SYS_JFFS2_MEM_NAND
 286 /* use flash_info[2] */
 287 #define CONFIG_SYS_JFFS2_FIRST_BANK     CONFIG_SYS_MAX_FLASH_BANKS
 288 #define CONFIG_SYS_JFFS2_NUM_BANKS      1
 289
 290 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 291 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 292 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 293 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + \
 294                                          CONFIG_SYS_INIT_RAM_SIZE - \
 295                                          GENERATED_GBL_DATA_SIZE)
 296
 297 /* Defines for SPL */
 298 #define CONFIG_SPL_FRAMEWORK
 299 #define CONFIG_SPL_BOARD_INIT
 300 #define CONFIG_SPL_NAND_SIMPLE
 301
 302 #define CONFIG_SPL_NAND_BASE
 303 #define CONFIG_SPL_NAND_DRIVERS
 304 #define CONFIG_SPL_NAND_ECC
 305 #define CONFIG_SPL_LDSCRIPT             "arch/arm/mach-omap2/u-boot-spl.lds"
 306
 307 #define CONFIG_SPL_TEXT_BASE            0x40200000 /*CONFIG_SYS_SRAM_START*/
 308 #define CONFIG_SPL_MAX_SIZE             (54 * 1024)     /* 8 KB for stack */
 309 #define CONFIG_SPL_STACK                LOW_LEVEL_SRAM_STACK
 310
 311 /* move malloc and bss high to prevent clashing with the main image */
 312 #define CONFIG_SYS_SPL_MALLOC_START     0x8f000000
 313 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x80000
 314 #define CONFIG_SPL_BSS_START_ADDR       0x8f080000 /* end of RAM */
 315 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
 316
 317 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 318 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
 319
 320 /* NAND boot config */
 321 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 322 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 323 #define CONFIG_SYS_NAND_OOBSIZE         64
 324 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128*1024)
 325 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 326 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 327 #define CONFIG_SYS_NAND_ECCPOS          {40, 41, 42, 43, 44, 45, 46, 47,\
 328                                          48, 49, 50, 51, 52, 53, 54, 55,\
 329                                          56, 57, 58, 59, 60, 61, 62, 63}
 330 #define CONFIG_SYS_NAND_ECCSIZE         256
 331 #define CONFIG_SYS_NAND_ECCBYTES        3
 332 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_SW
 333 #define CONFIG_SPL_NAND_SOFTECC
 334
 335 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
 336
 337 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 338
 339 /*
 340  * ethernet support
 341  *
 342  */
 343 #if defined(CONFIG_CMD_NET)
 344 #define CONFIG_DRIVER_TI_EMAC
 345 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
 346 #define CONFIG_MII
 347 #define CONFIG_BOOTP_DNS
 348 #define CONFIG_BOOTP_DNS2
 349 #define CONFIG_BOOTP_SEND_HOSTNAME
 350 #define CONFIG_NET_RETRY_COUNT 10
 351 #endif
 352
 353 #define CONFIG_SPLASH_SCREEN
 354 #define CONFIG_VIDEO_BMP_RLE8
 355 #define CONFIG_VIDEO_OMAP3
 356
 357 #endif /* __CONFIG_H */