include/configs/mecp5123.h

   1 /*
   2  * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
   3  * (C) Copyright 2009, DAVE Srl <www.dave.eu>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  * modifications for the MECP5123 by reinhard.arlt@esd-electronics.com
   7  *
   8  */
   9
  10 /*
  11  * MECP5123 board configuration file
  12  */
  13
  14 #ifndef __CONFIG_H
  15 #define __CONFIG_H
  16
  17 #define CONFIG_MECP5123 1
  18
  19 /*
  20  * Memory map for the MECP5123 board:
  21  *
  22  * 0x0000_0000 - 0x1FFF_FFFF    DDR RAM (512 MB)
  23  * 0x3000_0000 - 0x3001_FFFF    SRAM (128 KB)
  24  * 0x8000_0000 - 0x803F_FFFF    IMMR (4 MB)
  25  * 0x8200_0000 - 0x8200_FFFF    VPC-3 (64 KB)
  26  * 0xFFC0_0000 - 0xFFFF_FFFF    NOR Boot FLASH (64 MB)
  27  */
  28
  29 /*
  30  * High Level Configuration Options
  31  */
  32 #define CONFIG_E300             1       /* E300 Family */
  33
  34 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  35
  36 #define CONFIG_SYS_MPC512X_CLKIN        33333333        /* in Hz */
  37
  38 #define CONFIG_MISC_INIT_R
  39
  40 #define CONFIG_SYS_IMMR                 0x80000000
  41 #define CONFIG_SYS_DIU_ADDR             (CONFIG_SYS_IMMR+0x2100)
  42
  43 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  44 #define CONFIG_SYS_MEMTEST_END          0x00400000
  45
  46 /*
  47  * DDR Setup - manually set all parameters as there's no SPD etc.
  48  */
  49 #define CONFIG_SYS_DDR_SIZE             512             /* MB */
  50
  51 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is sys memory*/
  52 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  53 #define CONFIG_SYS_MAX_RAM_SIZE         0x20000000
  54
  55 #define CONFIG_SYS_IOCTRL_MUX_DDR       0x00000036
  56
  57 /* DDR Controller Configuration
  58  *
  59  * SYS_CFG:
  60  *      [31:31] MDDRC Soft Reset:       Diabled
  61  *      [30:30] DRAM CKE pin:           Enabled
  62  *      [29:29] DRAM CLK:               Enabled
  63  *      [28:28] Command Mode:           Enabled (For initialization only)
  64  *      [27:25] DRAM Row Select:        dram_row[15:0] = magenta_address[25:10]
  65  *      [24:21] DRAM Bank Select:       dram_bank[1:0] = magenta_address[11:10]
  66  *      [20:19] Read Test:              DON'T USE
  67  *      [18:18] Self Refresh:           Enabled
  68  *      [17:17] 16bit Mode:             Disabled
  69  *      [16:13] Ready Delay:            2
  70  *      [12:12] Half DQS Delay:         Disabled
  71  *      [11:11] Quarter DQS Delay:      Disabled
  72  *      [10:08] Write Delay:            2
  73  *      [07:07] Early ODT:              Disabled
  74  *      [06:06] On DIE Termination:     Disabled
  75  *      [05:05] FIFO Overflow Clear:    DON'T USE here
  76  *      [04:04] FIFO Underflow Clear:   DON'T USE here
  77  *      [03:03] FIFO Overflow Pending:  DON'T USE here
  78  *      [02:02] FIFO Underlfow Pending: DON'T USE here
  79  *      [01:01] FIFO Overlfow Enabled:  Enabled
  80  *      [00:00] FIFO Underflow Enabled: Enabled
  81  * TIME_CFG0
  82  *      [31:16] DRAM Refresh Time:      0 CSB clocks
  83  *      [15:8]  DRAM Command Time:      0 CSB clocks
  84  *      [07:00] DRAM Precharge Time:    0 CSB clocks
  85  * TIME_CFG1
  86  *      [31:26] DRAM tRFC:
  87  *      [25:21] DRAM tWR1:
  88  *      [20:17] DRAM tWRT1:
  89  *      [16:11] DRAM tDRR:
  90  *      [10:05] DRAM tRC:
  91  *      [04:00] DRAM tRAS:
  92  * TIME_CFG2
  93  *      [31:28] DRAM tRCD:
  94  *      [27:23] DRAM tFAW:
  95  *      [22:19] DRAM tRTW1:
  96  *      [18:15] DRAM tCCD:
  97  *      [14:10] DRAM tRTP:
  98  *      [09:05] DRAM tRP:
  99  *      [04:00] DRAM tRPA
 100  */
 101 #define CONFIG_SYS_MDDRC_SYS_CFG         0xEA804A00
 102 #define CONFIG_SYS_MDDRC_TIME_CFG0       0x06183D2E
 103 #define CONFIG_SYS_MDDRC_TIME_CFG1       0x68EC1168
 104 #define CONFIG_SYS_MDDRC_TIME_CFG2       0x34310864
 105
 106 #define CONFIG_SYS_DDRCMD_NOP           0x01380000
 107 #define CONFIG_SYS_DDRCMD_PCHG_ALL      0x01100400
 108 #define CONFIG_SYS_DDRCMD_EM2           0x01020000
 109 #define CONFIG_SYS_DDRCMD_EM3           0x01030000
 110 #define CONFIG_SYS_DDRCMD_EN_DLL        0x01010000
 111 #define CONFIG_SYS_DDRCMD_RFSH          0x01080000
 112 #define CONFIG_SYS_MICRON_INIT_DEV_OP   0x01000432
 113 #define CONFIG_SYS_DDRCMD_OCD_DEFAULT   0x01010780
 114
 115 /* DDR Priority Manager Configuration */
 116 #define CONFIG_SYS_MDDRCGRP_PM_CFG1     0x00077777
 117 #define CONFIG_SYS_MDDRCGRP_PM_CFG2     0x00000000
 118 #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG  0x00000001
 119 #define CONFIG_SYS_MDDRCGRP_LUT0_MU     0xFFEEDDCC
 120 #define CONFIG_SYS_MDDRCGRP_LUT0_ML     0xBBAAAAAA
 121 #define CONFIG_SYS_MDDRCGRP_LUT1_MU     0x66666666
 122 #define CONFIG_SYS_MDDRCGRP_LUT1_ML     0x55555555
 123 #define CONFIG_SYS_MDDRCGRP_LUT2_MU     0x44444444
 124 #define CONFIG_SYS_MDDRCGRP_LUT2_ML     0x44444444
 125 #define CONFIG_SYS_MDDRCGRP_LUT3_MU     0x55555555
 126 #define CONFIG_SYS_MDDRCGRP_LUT3_ML     0x55555558
 127 #define CONFIG_SYS_MDDRCGRP_LUT4_MU     0x11111111
 128 #define CONFIG_SYS_MDDRCGRP_LUT4_ML     0x11111122
 129 #define CONFIG_SYS_MDDRCGRP_LUT0_AU     0xaaaaaaaa
 130 #define CONFIG_SYS_MDDRCGRP_LUT0_AL     0xaaaaaaaa
 131 #define CONFIG_SYS_MDDRCGRP_LUT1_AU     0x66666666
 132 #define CONFIG_SYS_MDDRCGRP_LUT1_AL     0x66666666
 133 #define CONFIG_SYS_MDDRCGRP_LUT2_AU     0x11111111
 134 #define CONFIG_SYS_MDDRCGRP_LUT2_AL     0x11111111
 135 #define CONFIG_SYS_MDDRCGRP_LUT3_AU     0x11111111
 136 #define CONFIG_SYS_MDDRCGRP_LUT3_AL     0x11111111
 137 #define CONFIG_SYS_MDDRCGRP_LUT4_AU     0x11111111
 138 #define CONFIG_SYS_MDDRCGRP_LUT4_AL     0x11111111
 139
 140 /*
 141  * NOR FLASH on the Local Bus
 142  */
 143 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 144 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 145
 146 #define CONFIG_SYS_FLASH_BASE           0xFFC00000      /* start of FLASH */
 147 #define CONFIG_SYS_FLASH_SIZE           0x00400000      /* max flash size */
 148
 149 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 150 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 151 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
 152 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max sectors per device */
 153
 154 #undef CONFIG_SYS_FLASH_CHECKSUM
 155
 156 /*
 157  * NAND FLASH
 158  * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
 159  */
 160 #define CONFIG_CMD_NAND
 161 #define CONFIG_NAND_MPC5121_NFC
 162 #define CONFIG_SYS_NAND_BASE            0x40000000
 163 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 164
 165 /*
 166  * Configuration parameters for MPC5121 NAND driver
 167  */
 168 #define CONFIG_FSL_NFC_WIDTH            1
 169 #define CONFIG_FSL_NFC_WRITE_SIZE       2048
 170 #define CONFIG_FSL_NFC_SPARE_SIZE       64
 171 #define CONFIG_FSL_NFC_CHIPS            1
 172
 173 #define CONFIG_SYS_SRAM_BASE            0x30000000
 174 #define CONFIG_SYS_SRAM_SIZE            0x00020000      /* 128 KB */
 175
 176 /* Initialize Local Window for NOR FLASH access */
 177 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 178 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 179
 180 /* ALE active low, data size 4bytes */
 181 #define CONFIG_SYS_CS0_CFG              0x05051150
 182
 183 /* Use not alternative CS timing */
 184 #define CONFIG_SYS_CS_ALETIMING         0x00000000
 185
 186 /* ALE active low, data size 4bytes */
 187 #define CONFIG_SYS_CS1_CFG              0x1f1f3090
 188 #define CONFIG_SYS_VPC3_BASE            0x82000000      /* start of VPC3 space */
 189 #define CONFIG_SYS_VPC3_SIZE            0x00010000      /* max VPC3 size */
 190 /* Initialize Local Window for VPC3 access */
 191 #define CONFIG_SYS_CS1_START            CONFIG_SYS_VPC3_BASE
 192 #define CONFIG_SYS_CS1_SIZE             CONFIG_SYS_VPC3_SIZE
 193
 194 /* Use SRAM for initial stack */
 195 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_SRAM_BASE /* Init RAM addr */
 196 #define CONFIG_SYS_INIT_RAM_SIZE                CONFIG_SYS_SRAM_SIZE
 197
 198 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 199 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 200
 201 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* Start of monitor */
 202 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Monitor length */
 203 #define CONFIG_SYS_MALLOC_LEN           (6 * 1024 * 1024) /* Malloc size */
 204
 205 /*
 206  * Serial Port
 207  */
 208 #define CONFIG_CONS_INDEX     1
 209
 210 /*
 211  * Serial console configuration
 212  */
 213 #define CONFIG_PSC_CONSOLE      3       /* console is on PSC3 */
 214 #define CONFIG_SYS_PSC3
 215 #if CONFIG_PSC_CONSOLE != 3
 216 #error CONFIG_PSC_CONSOLE must be 3
 217 #endif
 218 #define CONFIG_SYS_BAUDRATE_TABLE  \
 219         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 220
 221 #define CONSOLE_FIFO_TX_SIZE    FIFOC_PSC3_TX_SIZE
 222 #define CONSOLE_FIFO_TX_ADDR    FIFOC_PSC3_TX_ADDR
 223 #define CONSOLE_FIFO_RX_SIZE    FIFOC_PSC3_RX_SIZE
 224 #define CONSOLE_FIFO_RX_ADDR    FIFOC_PSC3_RX_ADDR
 225
 226 /*
 227  * Clocks in use
 228  */
 229 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN |                           \
 230                          CLOCK_SCCR1_LPC_EN |                           \
 231                          CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |       \
 232                          CLOCK_SCCR1_PSCFIFO_EN |                       \
 233                          CLOCK_SCCR1_DDR_EN |                           \
 234                          CLOCK_SCCR1_FEC_EN |                           \
 235                          CLOCK_SCCR1_NFC_EN |                           \
 236                          CLOCK_SCCR1_PCI_EN |                           \
 237                          CLOCK_SCCR1_TPR_EN)
 238
 239 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN |   \
 240                          CLOCK_SCCR2_I2C_EN)
 241
 242 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 243
 244 /* I2C */
 245 #define CONFIG_HARD_I2C                 /* I2C with hardware support */
 246 #define CONFIG_I2C_MULTI_BUS
 247 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed */
 248 #define CONFIG_SYS_I2C_SLAVE            0x7F    /* slave address */
 249
 250 /*
 251  * IIM - IC Identification Module
 252  */
 253 #undef CONFIG_FSL_IIM
 254
 255 /*
 256  * EEPROM configuration
 257  */
 258 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2       /* 16-bit EEPROM address */
 259 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* Atmel: AT24C32A-10TQ-2.7 */
 260 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10        /* 10ms of delay */
 261 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5     /* 32-Byte Page Write Mode */
 262 #define CONFIG_SYS_EEPROM_WREN                  /* Use EEPROM write protect */
 263
 264 /*
 265  * Ethernet configuration
 266  */
 267 #define CONFIG_MPC512x_FEC      1
 268 #define CONFIG_PHY_ADDR         0x1
 269 #define CONFIG_MII              1       /* MII PHY management           */
 270 #define CONFIG_FEC_AN_TIMEOUT   1
 271 #define CONFIG_HAS_ETH0
 272
 273 /*
 274  * Configure on-board RTC
 275  */
 276 #define CONFIG_SYS_RTC_BUS_NUM  0x01
 277 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
 278 #define CONFIG_RTC_RX8025
 279
 280 /*
 281  * Environment
 282  */
 283 #define CONFIG_ENV_IS_IN_EEPROM         /* Store env in I2C EEPROM      */
 284 #define CONFIG_ENV_SIZE         0x1000
 285 #define CONFIG_ENV_OFFSET       0x0000  /* environment starts here      */
 286
 287 #define CONFIG_LOADS_ECHO               /* echo on for serial download  */
 288 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change        */
 289
 290 #define CONFIG_CMD_REGINFO
 291 #define CONFIG_CMD_EEPROM
 292 #define CONFIG_CMD_DATE
 293 #undef CONFIG_CMD_FUSE
 294 #undef CONFIG_CMD_IDE
 295 #define CONFIG_CMD_JFFS2
 296
 297 /*
 298  * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
 299  * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
 300  * to 0xFFFF, watchdog timeouts after about 64s. For details refer
 301  * to chapter 36 of the MPC5121e Reference Manual.
 302  */
 303 /* #define CONFIG_WATCHDOG */           /* enable watchdog */
 304 #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
 305
 306  /*
 307  * Miscellaneous configurable options
 308  */
 309 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 310 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 311
 312 #ifdef CONFIG_CMD_KGDB
 313 # define CONFIG_SYS_CBSIZE      1024            /* Console I/O Buffer Size */
 314 #else
 315 # define CONFIG_SYS_CBSIZE      256             /* Console I/O Buffer Size */
 316 #endif
 317
 318 /* Print Buffer Size */
 319 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + \
 320                                  sizeof(CONFIG_SYS_PROMPT) + 16)
 321 /* max number of command args */
 322 #define CONFIG_SYS_MAXARGS      32
 323 /* Boot Argument Buffer Size */
 324 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 325
 326 /*
 327  * For booting Linux, the board info and command line data
 328  * have to be in the first 256 MB of memory, since this is
 329  * the maximum mapped by the Linux kernel during initialization.
 330  */
 331 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Linux initial memory map */
 332
 333 /* Cache Configuration */
 334 #define CONFIG_SYS_DCACHE_SIZE          32768
 335 #define CONFIG_SYS_CACHELINE_SIZE       32
 336 #ifdef CONFIG_CMD_KGDB
 337 #define CONFIG_SYS_CACHELINE_SHIFT      5
 338 #endif
 339
 340 #define CONFIG_SYS_HID0_INIT    0x000000000
 341 #define CONFIG_SYS_HID0_FINAL   HID0_ENABLE_MACHINE_CHECK
 342 #define CONFIG_SYS_HID2         HID2_HBE
 343
 344 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 345
 346 #ifdef CONFIG_CMD_KGDB
 347 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 348 #endif
 349
 350 /*
 351  * Environment Configuration
 352  */
 353 #define CONFIG_TIMESTAMP
 354
 355 #define CONFIG_HOSTNAME         mecp512x
 356 #define CONFIG_BOOTFILE         "/tftpboot/mecp512x/uImage"
 357 #define CONFIG_ROOTPATH         "/tftpboot/mecp512x/target_root"
 358
 359 #define CONFIG_LOADADDR         400000  /* def. location for tftp and bootm */
 360
 361 #undef  CONFIG_BOOTARGS                 /* the boot command will set bootargs*/
 362
 363 #define CONFIG_PREBOOT  "echo;" \
 364         "echo Welcome to MECP5123" \
 365         "echo"
 366
 367 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 368         "u-boot_addr_r=200000\0"                                        \
 369         "kernel_addr_r=600000\0"                                        \
 370         "fdt_addr_r=880000\0"                                           \
 371         "ramdisk_addr_r=900000\0"                                       \
 372         "u-boot_addr=FFF00000\0"                                        \
 373         "kernel_addr=FFC40000\0"                                        \
 374         "fdt_addr=FFEC0000\0"                                           \
 375         "ramdisk_addr=FC040000\0"                                       \
 376         "ramdiskfile=/tftpboot/mecp512x/uRamdisk\0"                     \
 377         "u-boot=/tftpboot/mecp512x/u-boot.bin\0"                        \
 378         "bootfile=/tftpboot/mecp512x/uImage\0"                          \
 379         "fdtfile=/tftpboot/mecp512x/mecp512x.dtb\0"                     \
 380         "rootpath=/tftpboot/mecp512x/target_root\n"                     \
 381         "netdev=eth0\0"                                                 \
 382         "consdev=ttyPSC0\0"                                             \
 383         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 384                 "nfsroot=${serverip}:${rootpath}\0"                     \
 385         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 386         "addip=setenv bootargs ${bootargs} "                            \
 387                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 388                 ":${hostname}:${netdev}:off panic=1\0"                  \
 389         "addtty=setenv bootargs ${bootargs} "                           \
 390                 "console=${consdev},${baudrate}\0"                      \
 391         "flash_nfs=run nfsargs addip addtty;"                           \
 392                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 393         "flash_self=run ramargs addip addtty;"                          \
 394                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 395         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
 396                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 397                 "run nfsargs addip addtty;"                             \
 398                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 399         "net_self=tftp ${kernel_addr_r} ${bootfile};"                   \
 400                 "tftp ${ramdisk_addr_r} ${ramdiskfile};"                \
 401                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 402                 "run ramargs addip addtty;"                             \
 403                 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
 404         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                        \
 405         "update=protect off ${u-boot_addr} +${filesize};"               \
 406                 "era ${u-boot_addr} +${filesize};"                      \
 407                 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"    \
 408         "upd=run load update\0"                                         \
 409         ""
 410
 411 #define CONFIG_BOOTCOMMAND      "run flash_self"
 412
 413 #define OF_CPU                  "PowerPC,5121@0"
 414 #define OF_SOC_COMPAT           "fsl,mpc5121-immr"
 415 #define OF_TBCLK                (bd->bi_busfreq / 4)
 416 #define OF_STDOUT_PATH          "/soc@80000000/serial@11300"
 417
 418 #endif  /* __CONFIG_H */