include/configs/meesc.h

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian@popies.net>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * (C) Copyright 2009-2015
   7  * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
   8  * esd electronic system design gmbh <www.esd.eu>
   9  *
  10  * Configuation settings for the esd MEESC board.
  11  *
  12  * SPDX-License-Identifier:     GPL-2.0+
  13  */
  14
  15 #ifndef __CONFIG_H
  16 #define __CONFIG_H
  17
  18 /*
  19  * SoC must be defined first, before hardware.h is included.
  20  * In this case SoC is defined in boards.cfg.
  21  */
  22 #include <asm/hardware.h>
  23
  24 /*
  25  * Warning: changing CONFIG_SYS_TEXT_BASE requires
  26  * adapting the initial boot program.
  27  * Since the linker has to swallow that define, we must use a pure
  28  * hex number here!
  29  */
  30 #define CONFIG_SYS_TEXT_BASE            0x21F00000
  31
  32 /* ARM asynchronous clock */
  33 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768   /* 32.768 kHz crystal */
  34 #define CONFIG_SYS_AT91_MAIN_CLOCK      16000000/* 16.0 MHz crystal */
  35
  36 /* Misc CPU related */
  37 #define CONFIG_SKIP_LOWLEVEL_INIT
  38 #define CONFIG_ARCH_CPU_INIT
  39 #define CONFIG_SETUP_MEMORY_TAGS
  40 #define CONFIG_INITRD_TAG
  41 #define CONFIG_SERIAL_TAG
  42 #define CONFIG_REVISION_TAG
  43 #define CONFIG_CMDLINE_TAG                      /* enable passing of ATAGs */
  44 #define CONFIG_MISC_INIT_R                      /* Call misc_init_r */
  45
  46 #define CONFIG_PREBOOT                          /* enable preboot variable */
  47
  48 /*
  49  * Hardware drivers
  50  */
  51
  52 /* general purpose I/O */
  53 #define CONFIG_AT91_GPIO
  54
  55 /* Console output */
  56 #define CONFIG_ATMEL_USART
  57 #define CONFIG_USART_BASE               ATMEL_BASE_DBGU
  58 #define CONFIG_USART_ID                 ATMEL_ID_SYS
  59
  60 /*
  61  * BOOTP options
  62  */
  63 #define CONFIG_BOOTP_BOOTFILESIZE
  64 #define CONFIG_BOOTP_BOOTPATH
  65 #define CONFIG_BOOTP_GATEWAY
  66 #define CONFIG_BOOTP_HOSTNAME
  67
  68 /* LED */
  69 #define CONFIG_AT91_LED
  70
  71 /*
  72  * SDRAM: 1 bank, min 32, max 128 MB
  73  * Initialized before u-boot gets started.
  74  */
  75 #define PHYS_SDRAM                                      ATMEL_BASE_CS1 /* 0x20000000 */
  76 #define PHYS_SDRAM_SIZE                         0x02000000     /* 32 MByte */
  77
  78 #define CONFIG_NR_DRAM_BANKS            1
  79 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM
  80 #define CONFIG_SYS_SDRAM_SIZE           PHYS_SDRAM_SIZE
  81
  82 #define CONFIG_SYS_MEMTEST_START        (CONFIG_SYS_SDRAM_BASE + 0x00100000)
  83 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_SDRAM_BASE + 0x01E00000)
  84 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 0x00100000)
  85
  86 /*
  87  * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
  88  * leaving the correct space for initial global data structure above
  89  * that address while providing maximum stack area below.
  90  */
  91 #define CONFIG_SYS_INIT_SP_ADDR \
  92         (ATMEL_BASE_SRAM0 + 0x1000 - GENERATED_GBL_DATA_SIZE)
  93
  94 /* DataFlash */
  95 #ifdef CONFIG_SYS_USE_DATAFLASH
  96 # define CONFIG_ATMEL_DATAFLASH_SPI
  97 # define CONFIG_HAS_DATAFLASH
  98 # define CONFIG_SYS_MAX_DATAFLASH_BANKS         1
  99 # define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0    0xC0000000      /* CS0 */
 100 # define AT91_SPI_CLK                           15000000
 101 # define DATAFLASH_TCSS                         (0x1a << 16)
 102 # define DATAFLASH_TCHS                         (0x1 << 24)
 103 #endif
 104
 105 /* NAND flash */
 106 #ifdef CONFIG_CMD_NAND
 107 # define CONFIG_NAND_ATMEL
 108 # define CONFIG_SYS_MAX_NAND_DEVICE             1
 109 # define CONFIG_SYS_NAND_BASE                   ATMEL_BASE_CS3 /* 0x40000000 */
 110 # define CONFIG_SYS_NAND_DBW_8
 111 # define CONFIG_SYS_NAND_MASK_ALE               (1 << 21)
 112 # define CONFIG_SYS_NAND_MASK_CLE               (1 << 22)
 113 # define CONFIG_SYS_NAND_ENABLE_PIN             GPIO_PIN_PD(15)
 114 # define CONFIG_SYS_NAND_READY_PIN              GPIO_PIN_PA(22)
 115 #endif
 116
 117 /* Ethernet */
 118 #define CONFIG_MACB
 119 #define CONFIG_RMII
 120 #define CONFIG_NET_RETRY_COUNT                  20
 121 #undef CONFIG_RESET_PHY_R
 122
 123 /* hw-controller addresses */
 124 #define CONFIG_ET1100_BASE              0x70000000
 125
 126 #ifdef CONFIG_SYS_USE_DATAFLASH
 127
 128 /* bootstrap + u-boot + env in dataflash on CS0 */
 129 # define CONFIG_SYS_MONITOR_BASE        (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \
 130                                         0x8400)
 131 # define CONFIG_ENV_OFFSET              0x4200
 132 # define CONFIG_ENV_ADDR                (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \
 133                                         CONFIG_ENV_OFFSET)
 134 # define CONFIG_ENV_SIZE                0x4200
 135
 136 #elif CONFIG_SYS_USE_NANDFLASH
 137
 138 /* bootstrap + u-boot + env + linux in nandflash */
 139 # define CONFIG_ENV_OFFSET              0xC0000
 140 # define CONFIG_ENV_SIZE                0x20000
 141
 142 #endif
 143
 144 #define CONFIG_SYS_CBSIZE               512
 145 #define CONFIG_SYS_MAXARGS              16
 146 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 147                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 148 #define CONFIG_SYS_LONGHELP
 149 #define CONFIG_CMDLINE_EDITING
 150 #define CONFIG_AUTO_COMPLETE
 151
 152 /*
 153  * Size of malloc() pool
 154  */
 155 #define CONFIG_SYS_MALLOC_LEN           ROUND(3 * CONFIG_ENV_SIZE + \
 156                                         128*1024, 0x1000)
 157
 158 #endif