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git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/microblaze-generic.h
6e3c80b1435014a7c424112fcb71e091d786b8cf
2 * (C) Copyright 2007-2010 Michal Simek
4 * Michal SIMEK <monstr@monstr.eu>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include "../board/xilinx/microblaze-generic/xparameters.h"
15 #define MICROBLAZE_V5 1
17 /* linear and spi flash memory */
18 #ifdef XILINX_FLASH_START
21 #undef RAMENV /* hold environment in flash */
23 #ifdef XILINX_SPI_FLASH_BASEADDR
26 #undef RAMENV /* hold environment in flash */
30 #define RAMENV /* hold environment in RAM */
35 # define CONFIG_BAUDRATE 115200
36 /* The following table includes the supported baudrates */
37 # define CONFIG_SYS_BAUDRATE_TABLE \
38 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
40 #if XILINX_UART16550_BASEADDR
41 # define CONFIG_SYS_NS16550_SERIAL
42 # if defined(__MICROBLAZEEL__)
43 # define CONFIG_SYS_NS16550_REG_SIZE -4
45 # define CONFIG_SYS_NS16550_REG_SIZE 4
47 # define CONFIG_CONS_INDEX 1
48 # define CONFIG_SYS_NS16550_COM1 \
49 ((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000)
50 # define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ
53 /* setting reset address */
54 /*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/
57 #undef CONFIG_SYS_ENET
58 #if defined(XILINX_EMACLITE_BASEADDR) || defined(CONFIG_OF_CONTROL)
59 # define CONFIG_XILINX_EMACLITE 1
60 # define CONFIG_SYS_ENET
62 #if defined(XILINX_AXIEMAC_BASEADDR)
63 # define CONFIG_XILINX_AXIEMAC 1
64 # define CONFIG_SYS_ENET
70 #ifdef XILINX_GPIO_BASEADDR
71 # define CONFIG_XILINX_GPIO
72 # define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
75 /* interrupt controller */
76 #ifdef XILINX_INTC_BASEADDR
77 # define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR
78 # define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
82 #if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ)
83 # define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR
84 # define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ
88 #if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
89 # define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR
90 # define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ
91 # ifndef CONFIG_SPL_BUILD
92 # define CONFIG_HW_WATCHDOG
93 # define CONFIG_XILINX_TB_WATCHDOG
97 #if !defined(CONFIG_OF_CONTROL) || \
98 (defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_OF_CONTROL))
99 /* ddr sdram - main memory */
100 # define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START
101 # define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE
104 #define CONFIG_SYS_MALLOC_LEN 0xC0000
106 /* Stack location before relocation */
107 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \
108 CONFIG_SYS_MALLOC_F_LEN)
111 * CFI flash memory layout - Example
112 * CONFIG_SYS_FLASH_BASE = 0x2200_0000;
113 * CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB
115 * SECT_SIZE = 0x20000; 128kB is one sector
116 * CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store
118 * 0x2200_0000 CONFIG_SYS_FLASH_BASE
120 * 0x2204_0000 CONFIG_ENV_ADDR
124 * 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
129 # define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START
130 # define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE
131 # define CONFIG_SYS_FLASH_CFI 1
132 # define CONFIG_FLASH_CFI_DRIVER 1
134 # define CONFIG_SYS_FLASH_EMPTY_INFO 1
135 /* max number of memory banks */
136 # define CONFIG_SYS_MAX_FLASH_BANKS 1
137 /* max number of sectors on one chip */
138 # define CONFIG_SYS_MAX_FLASH_SECT 512
139 /* hardware flash protection */
140 # define CONFIG_SYS_FLASH_PROTECTION
141 /* use buffered writes (20x faster) */
142 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
144 # define CONFIG_ENV_IS_NOWHERE 1
145 # define CONFIG_ENV_SIZE 0x1000
146 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
148 # else /* FLASH && !RAMENV */
149 # define CONFIG_ENV_IS_IN_FLASH 1
150 /* 128K(one sector) for env */
151 # define CONFIG_ENV_SECT_SIZE 0x20000
152 # define CONFIG_ENV_ADDR \
153 (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
154 # define CONFIG_ENV_SIZE 0x20000
155 # endif /* FLASH && !RAMBOOT */
159 # define CONFIG_SYS_NO_FLASH 1
160 # define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR
161 # define CONFIG_SPI 1
162 # define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
163 # define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ
164 # define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS
167 # define CONFIG_ENV_IS_NOWHERE 1
168 # define CONFIG_ENV_SIZE 0x1000
169 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
171 # else /* SPIFLASH && !RAMENV */
172 # define CONFIG_ENV_IS_IN_SPI_FLASH 1
173 # define CONFIG_ENV_SPI_MODE SPI_MODE_3
174 # define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
175 # define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
176 /* 128K(two sectors) for env */
177 # define CONFIG_ENV_SECT_SIZE 0x10000
178 # define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE)
179 /* Warning: adjust the offset in respect of other flash content and size */
180 # define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
181 # endif /* SPIFLASH && !RAMBOOT */
182 #else /* !SPIFLASH */
185 # define CONFIG_SYS_NO_FLASH 1
186 # define CONFIG_ENV_IS_NOWHERE 1
187 # define CONFIG_ENV_SIZE 0x1000
188 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
189 #endif /* !SPIFLASH */
193 #ifdef XILINX_SYSACE_BASEADDR
194 # define CONFIG_SYSTEMACE
195 /* #define DEBUG_SYSTEMACE */
196 # define SYSTEMACE_CONFIG_FPGA
197 # define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
198 # define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
199 # define CONFIG_DOS_PARTITION
202 #if defined(XILINX_USE_ICACHE)
203 # define CONFIG_ICACHE
205 # undef CONFIG_ICACHE
208 #if defined(XILINX_USE_DCACHE)
209 # define CONFIG_DCACHE
211 # undef CONFIG_DCACHE
214 #ifndef XILINX_DCACHE_BYTE_SIZE
215 #define XILINX_DCACHE_BYTE_SIZE 32768
221 #define CONFIG_BOOTP_BOOTFILESIZE
222 #define CONFIG_BOOTP_BOOTPATH
223 #define CONFIG_BOOTP_GATEWAY
224 #define CONFIG_BOOTP_HOSTNAME
227 * Command line configuration.
229 #define CONFIG_CMD_ASKENV
230 #define CONFIG_CMD_IRQ
231 #define CONFIG_CMD_MFSL
233 #if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE)
234 # define CONFIG_CMD_CACHE
236 # undef CONFIG_CMD_CACHE
239 #ifdef CONFIG_SYS_ENET
240 # define CONFIG_CMD_PING
241 # define CONFIG_CMD_DHCP
242 # define CONFIG_CMD_TFTPPUT
245 #if defined(CONFIG_SYSTEMACE)
246 # define CONFIG_CMD_EXT2
247 # define CONFIG_CMD_FAT
251 # define CONFIG_CMD_JFFS2
252 # define CONFIG_CMD_UBI
253 # undef CONFIG_CMD_UBIFS
255 # if !defined(RAMENV)
256 # define CONFIG_CMD_SAVES
260 #if defined(SPIFLASH)
261 # define CONFIG_CMD_SF
263 # if !defined(RAMENV)
264 # define CONFIG_CMD_SAVES
267 # undef CONFIG_CMD_JFFS2
268 # undef CONFIG_CMD_UBI
269 # undef CONFIG_CMD_UBIFS
273 #if defined(CONFIG_CMD_JFFS2)
274 # define CONFIG_MTD_PARTITIONS
277 #if defined(CONFIG_CMD_UBIFS)
278 # define CONFIG_CMD_UBI
282 #if defined(CONFIG_CMD_UBI)
283 # define CONFIG_MTD_PARTITIONS
284 # define CONFIG_RBTREE
287 #if defined(CONFIG_MTD_PARTITIONS)
289 #define CONFIG_CMD_MTDPARTS /* mtdparts command line support */
290 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
291 #define CONFIG_FLASH_CFI_MTD
292 #define MTDIDS_DEFAULT "nor0=flash-0"
294 /* default mtd partition table */
295 #define MTDPARTS_DEFAULT "mtdparts=flash-0:256k(u-boot),"\
296 "256k(env),3m(kernel),1m(romfs),"\
297 "1m(cramfs),-(jffs2)"
300 /* size of console buffer */
301 #define CONFIG_SYS_CBSIZE 512
302 /* print buffer size */
303 #define CONFIG_SYS_PBSIZE \
304 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
305 /* max number of command args */
306 #define CONFIG_SYS_MAXARGS 15
307 #define CONFIG_SYS_LONGHELP
308 /* default load address */
309 #define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START
311 #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
312 #define CONFIG_BOOTARGS "root=romfs"
313 #define CONFIG_HOSTNAME XILINX_BOARD_NAME
314 #define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
315 #define CONFIG_IPADDR 192.168.0.3
316 #define CONFIG_SERVERIP 192.168.0.5
317 #define CONFIG_GATEWAYIP 192.168.0.1
319 /* architecture dependent code */
320 #define CONFIG_SYS_USR_EXCEP /* user exception */
322 #define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo"
324 #define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \
326 "mtdparts=mtdparts=flash-0:"\
327 "256k(u-boot),256k(env),3m(kernel),"\
328 "1m(romfs),1m(cramfs),-(jffs2)\0"\
329 "nc=setenv stdout nc;"\
330 "setenv stdin nc\0" \
331 "serial=setenv stdout serial;"\
332 "setenv stdin serial\0"
334 #define CONFIG_CMDLINE_EDITING
336 #define CONFIG_NETCONSOLE
337 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
339 /* Use the HUSH parser */
340 #define CONFIG_SYS_HUSH_PARSER
342 /* Enable flat device tree support */
345 #define CONFIG_OF_LIBFDT 1
347 #if defined(CONFIG_XILINX_AXIEMAC)
348 # define CONFIG_MII 1
349 # define CONFIG_CMD_MII 1
350 # define CONFIG_PHY_GIGE 1
351 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1
352 # define CONFIG_PHYLIB 1
353 # define CONFIG_PHY_ATHEROS 1
354 # define CONFIG_PHY_BROADCOM 1
355 # define CONFIG_PHY_DAVICOM 1
356 # define CONFIG_PHY_LXT 1
357 # define CONFIG_PHY_MARVELL 1
358 # define CONFIG_PHY_MICREL 1
359 # define CONFIG_PHY_NATSEMI 1
360 # define CONFIG_PHY_REALTEK 1
361 # define CONFIG_PHY_VITESSE 1
364 # undef CONFIG_CMD_MII
365 # undef CONFIG_PHYLIB
369 #define CONFIG_CMD_SPL
370 #define CONFIG_SPL_FRAMEWORK
371 #define CONFIG_SPL_LIBCOMMON_SUPPORT
372 #define CONFIG_SPL_LIBGENERIC_SUPPORT
373 #define CONFIG_SPL_SERIAL_SUPPORT
374 #define CONFIG_SPL_BOARD_INIT
376 #define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds"
378 #define CONFIG_SPL_RAM_DEVICE
379 #ifdef CONFIG_SYS_FLASH_BASE
380 # define CONFIG_SPL_NOR_SUPPORT
381 # define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE
384 /* for booting directly linux */
385 #define CONFIG_SPL_OS_BOOT
387 #define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + \
389 #define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \
391 #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \
394 /* SP location before relocation, must use scratch RAM */
396 #define CONFIG_SYS_INIT_RAM_ADDR 0x0
397 /* BRAM size - will be generated */
398 #define CONFIG_SYS_INIT_RAM_SIZE 0x100000
400 # define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
401 CONFIG_SYS_INIT_RAM_SIZE - \
402 CONFIG_SYS_MALLOC_F_LEN)
404 /* Just for sure that there is a space for stack */
405 #define CONFIG_SPL_STACK_SIZE 0x100
407 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
409 #define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \
410 CONFIG_SYS_INIT_RAM_ADDR - \
411 CONFIG_SYS_MALLOC_F_LEN - \
412 CONFIG_SPL_STACK_SIZE)
414 #endif /* __CONFIG_H */