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1 /*
2 * Copyright (C) 2006 Atmel Corporation
3 *
4 * Configuration settings for the AVR32 Network Gateway
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8 #ifndef __CONFIG_H
9 #define __CONFIG_H
10
11 #include <asm/arch/hardware.h>
12
13 #define CONFIG_AVR32
14 #define CONFIG_AT32AP
15 #define CONFIG_AT32AP7000
16 #define CONFIG_MIMC200
17
18 #define CONFIG_MIMC200_EXT_FLASH
19
20 #define CONFIG_SYS_HZ 1000
21
22 /*
23 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
24 * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
25 * and the PBA bus to run at 1/4 the PLL frequency.
26 */
27 #define CONFIG_PLL
28 #define CONFIG_SYS_POWER_MANAGER
29 #define CONFIG_SYS_OSC0_HZ 10000000
30 #define CONFIG_SYS_PLL0_DIV 1
31 #define CONFIG_SYS_PLL0_MUL 15
32 #define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
33 #define CONFIG_SYS_CLKDIV_CPU 0
34 #define CONFIG_SYS_CLKDIV_HSB 1
35 #define CONFIG_SYS_CLKDIV_PBA 2
36 #define CONFIG_SYS_CLKDIV_PBB 1
37
38 /* Reserve VM regions for SDRAM, NOR flash and FRAM */
39 #define CONFIG_SYS_NR_VM_REGIONS 3
40
41 /*
42 * The PLLOPT register controls the PLL like this:
43 * icp = PLLOPT<2>
44 * ivco = PLLOPT<1:0>
45 *
46 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
47 */
48 #define CONFIG_SYS_PLL0_OPT 0x04
49
50 #define CONFIG_USART_BASE ATMEL_BASE_USART1
51 #define CONFIG_USART_ID 1
52
53 #define CONFIG_MIMC200_DBGLINK 1
54
55 /* User serviceable stuff */
56 #define CONFIG_DOS_PARTITION
57
58 #define CONFIG_CMDLINE_TAG
59 #define CONFIG_SETUP_MEMORY_TAGS
60 #define CONFIG_INITRD_TAG
61
62 #define CONFIG_STACKSIZE (2048)
63
64 #define CONFIG_BAUDRATE 115200
65 #define CONFIG_BOOTARGS \
66 "root=/dev/mtdblock1 rootfstype=jffs2 fbmem=512k console=ttyS1"
67 #define CONFIG_BOOTCOMMAND \
68 "fsload boot/uImage; bootm"
69
70 #define CONFIG_SILENT_CONSOLE /* enable silent startup */
71 #define CONFIG_DISABLE_CONSOLE /* disable console */
72 #define CONFIG_SYS_DEVICE_NULLDEV /* include nulldev device */
73
74 #define CONFIG_LCD 1
75
76 /*
77 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
78 * data on the serial line may interrupt the boot sequence.
79 */
80 #define CONFIG_BOOTDELAY 0
81 #define CONFIG_ZERO_BOOTDELAY_CHECK
82 #define CONFIG_AUTOBOOT
83
84 /*
85 * After booting the board for the first time, new ethernet addresses
86 * should be generated and assigned to the environment variables
87 * "ethaddr" and "eth1addr". This is normally done during production.
88 */
89 #define CONFIG_OVERWRITE_ETHADDR_ONCE
90
91 /*
92 * BOOTP/DHCP options
93 */
94 #define CONFIG_BOOTP_SUBNETMASK
95 #define CONFIG_BOOTP_GATEWAY
96
97 /*
98 * Command line configuration.
99 */
100 #include <config_cmd_default.h>
101
102 #define CONFIG_CMD_ASKENV
103 #define CONFIG_CMD_DHCP
104 #define CONFIG_CMD_EXT2
105 #define CONFIG_CMD_FAT
106 #define CONFIG_CMD_JFFS2
107 #define CONFIG_CMD_MMC
108 #define CONFIG_CMD_NET
109
110 #define CONFIG_ATMEL_USART
111 #define CONFIG_MACB
112 #define CONFIG_PORTMUX_PIO
113 #define CONFIG_SYS_NR_PIOS 5
114 #define CONFIG_SYS_HSDRAMC
115 #define CONFIG_MMC
116 #define CONFIG_GENERIC_ATMEL_MCI
117 #define CONFIG_GENERIC_MMC
118
119 #if defined(CONFIG_LCD)
120 #define CONFIG_CMD_BMP
121 #define CONFIG_ATMEL_LCD 1
122 #define LCD_BPP LCD_COLOR16
123 #define CONFIG_BMP_16BPP 1
124 #define CONFIG_FB_ADDR 0x10600000
125 #define CONFIG_WHITE_ON_BLACK 1
126 #define CONFIG_VIDEO_BMP_GZIP 1
127 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE 262144
128 #define CONFIG_ATMEL_LCD_BGR555 1
129 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
130 #define CONFIG_SPLASH_SCREEN 1
131 #endif
132
133 #define CONFIG_SYS_DCACHE_LINESZ 32
134 #define CONFIG_SYS_ICACHE_LINESZ 32
135
136 #define CONFIG_NR_DRAM_BANKS 1
137
138 #define CONFIG_SYS_FLASH_CFI
139 #define CONFIG_FLASH_CFI_DRIVER
140
141 #define CONFIG_SYS_FLASH_BASE 0x00000000
142 #define CONFIG_SYS_FLASH_SIZE 0x800000
143 #define CONFIG_SYS_MAX_FLASH_BANKS 1
144 #define CONFIG_SYS_MAX_FLASH_SECT 135
145
146 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
147 #define CONFIG_SYS_TEXT_BASE 0x00000000
148
149 #define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
150 #define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
151 #define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
152
153 #define CONFIG_SYS_FRAM_BASE 0x08000000
154 #define CONFIG_SYS_FRAM_SIZE 0x20000
155
156 #define CONFIG_ENV_IS_IN_FLASH
157 #define CONFIG_ENV_SIZE 65536
158 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
159
160 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
161
162 #define CONFIG_SYS_MALLOC_LEN (1024*1024)
163 #define CONFIG_SYS_DMA_ALLOC_LEN (16384)
164
165 /* Allow 4MB for the kernel run-time image */
166 #define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
167 #define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
168
169 /* Other configuration settings that shouldn't have to change all that often */
170 #define CONFIG_SYS_PROMPT "U-Boot> "
171 #define CONFIG_SYS_CBSIZE 256
172 #define CONFIG_SYS_MAXARGS 16
173 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
174 #define CONFIG_SYS_LONGHELP
175
176 #define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
177 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
178
179 #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
180
181 #endif /* __CONFIG_H */