include/configs/mpc5121ads.h

   1 /*
   2  * (C) Copyright 2007-2009 DENX Software Engineering
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * MPC5121ADS board configuration file
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #define CONFIG_MPC5121ADS 1
  15
  16 /*
  17  * Memory map for the MPC5121ADS board:
  18  *
  19  * 0x0000_0000 - 0x0FFF_FFFF    DDR RAM (256 MB)
  20  * 0x3000_0000 - 0x3001_FFFF    SRAM (128 KB)
  21  * 0x8000_0000 - 0x803F_FFFF    IMMR (4 MB)
  22  * 0x8200_0000 - 0x8200_001F    CPLD (32 B)
  23  * 0x8400_0000 - 0x82FF_FFFF    PCI I/O space (16 MB)
  24  * 0xA000_0000 - 0xAFFF_FFFF    PCI memory space (256 MB)
  25  * 0xB000_0000 - 0xBFFF_FFFF    PCI memory mapped I/O space (256 MB)
  26  * 0xFC00_0000 - 0xFFFF_FFFF    NOR Boot FLASH (64 MB)
  27  */
  28
  29 /*
  30  * High Level Configuration Options
  31  */
  32 #define CONFIG_E300             1       /* E300 Family */
  33
  34 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  35
  36 /* video */
  37 #ifdef CONFIG_FSL_DIU_FB
  38 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_IMMR + 0x2100)
  39 #define CONFIG_VIDEO_LOGO
  40 #define CONFIG_VIDEO_BMP_LOGO
  41 #endif
  42
  43 /* CONFIG_PCI is defined at config time */
  44
  45 #ifdef CONFIG_MPC5121ADS_REV2
  46 #define CONFIG_SYS_MPC512X_CLKIN        66000000        /* in Hz */
  47 #else
  48 #define CONFIG_SYS_MPC512X_CLKIN        33333333        /* in Hz */
  49 #endif
  50
  51 #define CONFIG_MISC_INIT_R
  52
  53 #define CONFIG_SYS_IMMR         0x80000000
  54
  55 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  56 #define CONFIG_SYS_MEMTEST_END          0x00400000
  57
  58 /*
  59  * DDR Setup - manually set all parameters as there's no SPD etc.
  60  */
  61 #ifdef CONFIG_MPC5121ADS_REV2
  62 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
  63 #else
  64 #define CONFIG_SYS_DDR_SIZE             512             /* MB */
  65 #endif
  66 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is system memory*/
  67 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  68 #define CONFIG_SYS_MAX_RAM_SIZE         0x20000000
  69
  70 #define CONFIG_SYS_IOCTRL_MUX_DDR       0x00000036
  71
  72 /* DDR Controller Configuration
  73  *
  74  * SYS_CFG:
  75  *      [31:31] MDDRC Soft Reset:       Diabled
  76  *      [30:30] DRAM CKE pin:           Enabled
  77  *      [29:29] DRAM CLK:               Enabled
  78  *      [28:28] Command Mode:           Enabled (For initialization only)
  79  *      [27:25] DRAM Row Select:        dram_row[15:0] = magenta_address[25:10]
  80  *      [24:21] DRAM Bank Select:       dram_bank[1:0] = magenta_address[11:10]
  81  *      [20:19] Read Test:              DON'T USE
  82  *      [18:18] Self Refresh:           Enabled
  83  *      [17:17] 16bit Mode:             Disabled
  84  *      [16:13] Ready Delay:            2
  85  *      [12:12] Half DQS Delay:         Disabled
  86  *      [11:11] Quarter DQS Delay:      Disabled
  87  *      [10:08] Write Delay:            2
  88  *      [07:07] Early ODT:              Disabled
  89  *      [06:06] On DIE Termination:     Disabled
  90  *      [05:05] FIFO Overflow Clear:    DON'T USE here
  91  *      [04:04] FIFO Underflow Clear:   DON'T USE here
  92  *      [03:03] FIFO Overflow Pending:  DON'T USE here
  93  *      [02:02] FIFO Underlfow Pending: DON'T USE here
  94  *      [01:01] FIFO Overlfow Enabled:  Enabled
  95  *      [00:00] FIFO Underflow Enabled: Enabled
  96  * TIME_CFG0
  97  *      [31:16] DRAM Refresh Time:      0 CSB clocks
  98  *      [15:8]  DRAM Command Time:      0 CSB clocks
  99  *      [07:00] DRAM Precharge Time:    0 CSB clocks
 100  * TIME_CFG1
 101  *      [31:26] DRAM tRFC:
 102  *      [25:21] DRAM tWR1:
 103  *      [20:17] DRAM tWRT1:
 104  *      [16:11] DRAM tDRR:
 105  *      [10:05] DRAM tRC:
 106  *      [04:00] DRAM tRAS:
 107  * TIME_CFG2
 108  *      [31:28] DRAM tRCD:
 109  *      [27:23] DRAM tFAW:
 110  *      [22:19] DRAM tRTW1:
 111  *      [18:15] DRAM tCCD:
 112  *      [14:10] DRAM tRTP:
 113  *      [09:05] DRAM tRP:
 114  *      [04:00] DRAM tRPA
 115  */
 116 #ifdef CONFIG_MPC5121ADS_REV2
 117 #define CONFIG_SYS_MDDRC_SYS_CFG        0xE8604A00
 118 #define CONFIG_SYS_MDDRC_TIME_CFG1      0x54EC1168
 119 #define CONFIG_SYS_MDDRC_TIME_CFG2      0x35210864
 120 #else
 121 #define CONFIG_SYS_MDDRC_SYS_CFG        0xEA804A00
 122 #define CONFIG_SYS_MDDRC_TIME_CFG1      0x68EC1168
 123 #define CONFIG_SYS_MDDRC_TIME_CFG2      0x34310864
 124 #endif
 125 #define CONFIG_SYS_MDDRC_TIME_CFG0      0x06183D2E
 126
 127 #define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA         0xEA802B00
 128 #define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA       0x690e1189
 129 #define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA       0x35310864
 130
 131 #define CONFIG_SYS_DDRCMD_NOP           0x01380000
 132 #define CONFIG_SYS_DDRCMD_PCHG_ALL      0x01100400
 133 #define CONFIG_SYS_DDRCMD_EM2           0x01020000
 134 #define CONFIG_SYS_DDRCMD_EM3           0x01030000
 135 #define CONFIG_SYS_DDRCMD_EN_DLL        0x01010000
 136 #define CONFIG_SYS_DDRCMD_RFSH          0x01080000
 137
 138 #define DDRCMD_EMR_OCD(pr, ohm) ( \
 139         (1 << 24)          | /* MDDRC Command Request   */ \
 140         (1 << 16)          | /* MODE Reg BA[2:0]        */ \
 141         (0 << 12)          | /* Outputs 0=Enabled       */ \
 142         (0 << 11)          | /* RDQS                    */ \
 143         (1 << 10)          | /* DQS#                    */ \
 144         (pr <<  7)         | /* OCD prog 7=deflt,0=exit */ \
 145                     /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \
 146         ((ohm & 0x2) <<  5)| /* Rtt1                    */ \
 147         (0 <<  3)          | /* additive posted CAS#    */ \
 148         ((ohm & 0x1) <<  2)| /* Rtt0                    */ \
 149         (0 <<  0)          | /* Output Drive Strength   */ \
 150         (0 <<  0))           /* DLL Enable 0=Normal     */
 151
 152 #define CONFIG_SYS_DDRCMD_OCD_DEFAULT   DDRCMD_EMR_OCD(7, 0)
 153 #define CONFIG_SYS_ELPIDA_OCD_EXIT      DDRCMD_EMR_OCD(0, 0)
 154
 155 #define DDRCMD_MODE_REG(cas, wr) ( \
 156         (1 << 24)    | /* MDDRC Command Request                 */ \
 157         (0 << 16)    | /* MODE Reg BA[2:0]                      */ \
 158         ((wr-1) << 9)| /* Write Recovery                        */ \
 159         (cas << 4)   | /* CAS                                   */ \
 160         (0 << 3)     | /* Burst Type:0=Sequential,1=Interleaved */ \
 161         (2 << 0))      /* 4 or 8 Burst Length:0x2=4 0x3=8       */
 162
 163 #define CONFIG_SYS_MICRON_INIT_DEV_OP   DDRCMD_MODE_REG(3, 3)
 164 #define CONFIG_SYS_ELPIDA_INIT_DEV_OP   DDRCMD_MODE_REG(4, 4)
 165 #define CONFIG_SYS_ELPIDA_RES_DLL       (DDRCMD_MODE_REG(4, 4) | (1 << 8))
 166
 167 /* DDR Priority Manager Configuration */
 168 #define CONFIG_SYS_MDDRCGRP_PM_CFG1     0x00077777
 169 #define CONFIG_SYS_MDDRCGRP_PM_CFG2     0x00000000
 170 #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG  0x00000001
 171 #define CONFIG_SYS_MDDRCGRP_LUT0_MU     0xFFEEDDCC
 172 #define CONFIG_SYS_MDDRCGRP_LUT0_ML     0xBBAAAAAA
 173 #define CONFIG_SYS_MDDRCGRP_LUT1_MU     0x66666666
 174 #define CONFIG_SYS_MDDRCGRP_LUT1_ML     0x55555555
 175 #define CONFIG_SYS_MDDRCGRP_LUT2_MU     0x44444444
 176 #define CONFIG_SYS_MDDRCGRP_LUT2_ML     0x44444444
 177 #define CONFIG_SYS_MDDRCGRP_LUT3_MU     0x55555555
 178 #define CONFIG_SYS_MDDRCGRP_LUT3_ML     0x55555558
 179 #define CONFIG_SYS_MDDRCGRP_LUT4_MU     0x11111111
 180 #define CONFIG_SYS_MDDRCGRP_LUT4_ML     0x11111122
 181 #define CONFIG_SYS_MDDRCGRP_LUT0_AU     0xaaaaaaaa
 182 #define CONFIG_SYS_MDDRCGRP_LUT0_AL     0xaaaaaaaa
 183 #define CONFIG_SYS_MDDRCGRP_LUT1_AU     0x66666666
 184 #define CONFIG_SYS_MDDRCGRP_LUT1_AL     0x66666666
 185 #define CONFIG_SYS_MDDRCGRP_LUT2_AU     0x11111111
 186 #define CONFIG_SYS_MDDRCGRP_LUT2_AL     0x11111111
 187 #define CONFIG_SYS_MDDRCGRP_LUT3_AU     0x11111111
 188 #define CONFIG_SYS_MDDRCGRP_LUT3_AL     0x11111111
 189 #define CONFIG_SYS_MDDRCGRP_LUT4_AU     0x11111111
 190 #define CONFIG_SYS_MDDRCGRP_LUT4_AL     0x11111111
 191
 192 /*
 193  * NOR FLASH on the Local Bus
 194  */
 195 #undef CONFIG_BKUP_FLASH
 196 #define CONFIG_SYS_FLASH_CFI                            /* use the Common Flash Interface */
 197 #define CONFIG_FLASH_CFI_DRIVER                 /* use the CFI driver */
 198 #ifdef CONFIG_BKUP_FLASH
 199 #define CONFIG_SYS_FLASH_BASE           0xFF800000      /* start of FLASH   */
 200 #define CONFIG_SYS_FLASH_SIZE           0x00800000      /* max flash size in bytes */
 201 #else
 202 #define CONFIG_SYS_FLASH_BASE           0xFC000000      /* start of FLASH   */
 203 #define CONFIG_SYS_FLASH_SIZE           0x04000000      /* max flash size in bytes */
 204 #endif
 205 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 206 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 207 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
 208 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* max sectors per device */
 209
 210 #undef CONFIG_SYS_FLASH_CHECKSUM
 211
 212 /*
 213  * NAND FLASH
 214  * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
 215  */
 216 #define CONFIG_CMD_NAND                                 /* enable NAND support */
 217 #define CONFIG_JFFS2_NAND                               /* with JFFS2 on it */
 218 #define CONFIG_NAND_MPC5121_NFC
 219 #define CONFIG_SYS_NAND_BASE            0x40000000
 220
 221 #define CONFIG_SYS_MAX_NAND_DEVICE      2
 222 #define CONFIG_SYS_NAND_SELECT_DEVICE   /* driver supports mutipl. chips */
 223
 224 /*
 225  * Configuration parameters for MPC5121 NAND driver
 226  */
 227 #define CONFIG_FSL_NFC_WIDTH 1
 228 #define CONFIG_FSL_NFC_WRITE_SIZE 2048
 229 #define CONFIG_FSL_NFC_SPARE_SIZE 64
 230 #define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
 231
 232 /*
 233  * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
 234  * window is 64KB
 235  */
 236 #define CONFIG_SYS_CPLD_BASE            0x82000000
 237 #define CONFIG_SYS_CPLD_SIZE            0x00010000      /* 64 KB */
 238 #define CONFIG_SYS_CS2_START            CONFIG_SYS_CPLD_BASE
 239 #define CONFIG_SYS_CS2_SIZE             CONFIG_SYS_CPLD_SIZE
 240
 241 #define CONFIG_SYS_SRAM_BASE            0x30000000
 242 #define CONFIG_SYS_SRAM_SIZE            0x00020000      /* 128 KB */
 243
 244 #define CONFIG_SYS_CS0_CFG              0x05059310      /* ALE active low, data size 4bytes */
 245 #define CONFIG_SYS_CS2_CFG              0x05059010      /* ALE active low, data size 1byte */
 246 #define CONFIG_SYS_CS_ALETIMING 0x00000005      /* Use alternative CS timing for CS0 and CS2 */
 247
 248 /* Use SRAM for initial stack */
 249 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_SRAM_BASE            /* Initial RAM address */
 250 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_SRAM_SIZE            /* Size of used area in RAM */
 251
 252 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 253 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 254
 255 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE            /* Start of monitor */
 256 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)            /* Reserve 512 kB for Mon */
 257 #ifdef  CONFIG_FSL_DIU_FB
 258 #define CONFIG_SYS_MALLOC_LEN           (6 * 1024 * 1024)       /* Reserved for malloc */
 259 #else
 260 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
 261 #endif
 262
 263 /*
 264  * Serial Port
 265  */
 266 #define CONFIG_CONS_INDEX     1
 267
 268 /*
 269  * Serial console configuration
 270  */
 271 #define CONFIG_PSC_CONSOLE      3       /* console is on PSC3 */
 272 #define CONFIG_SYS_PSC3
 273 #if CONFIG_PSC_CONSOLE != 3
 274 #error CONFIG_PSC_CONSOLE must be 3
 275 #endif
 276 #define CONFIG_SYS_BAUDRATE_TABLE  \
 277         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 278
 279 #define CONSOLE_FIFO_TX_SIZE    FIFOC_PSC3_TX_SIZE
 280 #define CONSOLE_FIFO_TX_ADDR    FIFOC_PSC3_TX_ADDR
 281 #define CONSOLE_FIFO_RX_SIZE    FIFOC_PSC3_RX_SIZE
 282 #define CONSOLE_FIFO_RX_ADDR    FIFOC_PSC3_RX_ADDR
 283
 284 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 285
 286 /*
 287  * Clocks in use
 288  */
 289 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN |                           \
 290                          CLOCK_SCCR1_DDR_EN |                           \
 291                          CLOCK_SCCR1_FEC_EN |                           \
 292                          CLOCK_SCCR1_LPC_EN |                           \
 293                          CLOCK_SCCR1_NFC_EN |                           \
 294                          CLOCK_SCCR1_PATA_EN |                          \
 295                          CLOCK_SCCR1_PCI_EN |                           \
 296                          CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |       \
 297                          CLOCK_SCCR1_PSCFIFO_EN |                       \
 298                          CLOCK_SCCR1_TPR_EN)
 299
 300 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN |           \
 301                          CLOCK_SCCR2_I2C_EN |           \
 302                          CLOCK_SCCR2_MEM_EN |           \
 303                          CLOCK_SCCR2_SPDIF_EN |         \
 304                          CLOCK_SCCR2_USB1_EN |          \
 305                          CLOCK_SCCR2_USB2_EN)
 306
 307 /*
 308  * PCI
 309  */
 310 #ifdef CONFIG_PCI
 311 #define CONFIG_PCI_INDIRECT_BRIDGE
 312
 313 /*
 314  * General PCI
 315  */
 316 #define CONFIG_SYS_PCI_MEM_BASE 0xA0000000
 317 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
 318 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000      /* 256M */
 319 #define CONFIG_SYS_PCI_MMIO_BASE        (CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE)
 320 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 321 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000      /* 256M */
 322 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 323 #define CONFIG_SYS_PCI_IO_PHYS          0x84000000
 324 #define CONFIG_SYS_PCI_IO_SIZE          0x01000000      /* 16M */
 325
 326 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 327
 328 #endif
 329
 330 /* I2C */
 331 #define CONFIG_HARD_I2C                 /* I2C with hardware support */
 332 #define CONFIG_I2C_MULTI_BUS
 333 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address */
 334 #define CONFIG_SYS_I2C_SLAVE            0x7F
 335 #if 0
 336 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}}      /* Don't probe these addrs */
 337 #endif
 338
 339 /*
 340  * IIM - IC Identification Module
 341  */
 342 #undef CONFIG_FSL_IIM
 343
 344 /*
 345  * EEPROM configuration
 346  */
 347 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2       /* 16-bit EEPROM address */
 348 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* Atmel: AT24C32A-10TQ-2.7 */
 349 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* 10ms of delay */
 350 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* 32-Byte Page Write Mode */
 351
 352 /*
 353  * Ethernet configuration
 354  */
 355 #define CONFIG_MPC512x_FEC      1
 356 #define CONFIG_PHY_ADDR         0x1
 357 #define CONFIG_MII              1       /* MII PHY management           */
 358 #define CONFIG_FEC_AN_TIMEOUT   1
 359 #define CONFIG_HAS_ETH0
 360
 361 /*
 362  * Configure on-board RTC
 363  */
 364 #define CONFIG_RTC_M41T62                       /* use M41T62 rtc via i2 */
 365 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* at address 0x68              */
 366
 367 /*
 368  * USB  Support
 369  */
 370
 371 #if defined(CONFIG_CMD_USB)
 372 #define CONFIG_USB_EHCI                         /* Enable EHCI Support  */
 373 #define CONFIG_USB_EHCI_FSL                     /* On a FSL platform    */
 374 #define CONFIG_EHCI_MMIO_BIG_ENDIAN             /* With big-endian regs */
 375 #define CONFIG_EHCI_DESC_BIG_ENDIAN
 376 #define CONFIG_EHCI_IS_TDI
 377 #endif
 378
 379 /*
 380  * Environment
 381  */
 382 #define CONFIG_ENV_IS_IN_FLASH  1
 383 /* This has to be a multiple of the Flash sector size */
 384 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 385 #define CONFIG_ENV_SIZE         0x2000
 386 #ifdef CONFIG_BKUP_FLASH
 387 #define CONFIG_ENV_SECT_SIZE    0x20000 /* one sector (256K) for env */
 388 #else
 389 #define CONFIG_ENV_SECT_SIZE    0x40000 /* one sector (256K) for env */
 390 #endif
 391
 392 /* Address and size of Redundant Environment Sector     */
 393 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 394 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 395
 396 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 397 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 398
 399 #define CONFIG_CMD_EEPROM
 400 #define CONFIG_CMD_IDE
 401 #define CONFIG_CMD_JFFS2
 402 #define CONFIG_CMD_REGINFO
 403
 404 #undef CONFIG_CMD_FUSE
 405
 406 #if defined(CONFIG_PCI)
 407 #define CONFIG_CMD_PCI
 408 #endif
 409
 410 /*
 411  * Dynamic MTD partition support
 412  */
 413 #define CONFIG_CMD_MTDPARTS
 414 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 415 #define CONFIG_FLASH_CFI_MTD
 416 #define MTDIDS_DEFAULT          "nor0=fc000000.flash,nand0=mpc5121.nand"
 417
 418 /*
 419  * NOR flash layout:
 420  *
 421  * FC000000 - FEABFFFF 42.75 MiB        User Data
 422  * FEAC0000 - FFABFFFF  16 MiB          Root File System
 423  * FFAC0000 - FFEBFFFF   4 MiB          Linux Kernel
 424  * FFEC0000 - FFEFFFFF 256 KiB          Device Tree
 425  * FFF00000 - FFFFFFFF   1 MiB          U-Boot (up to 512 KiB) and 2 x * env
 426  *
 427  * NAND flash layout: one big partition
 428  */
 429 #define MTDPARTS_DEFAULT        "mtdparts=fc000000.flash:43776k(user)," \
 430                                                 "16m(rootfs),"          \
 431                                                 "4m(kernel),"           \
 432                                                 "256k(dtb),"            \
 433                                                 "1m(u-boot);"           \
 434                                         "mpc5121.nand:-(data)"
 435
 436 #if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2) || defined(CONFIG_CMD_USB)
 437 #define CONFIG_SUPPORT_VFAT
 438
 439 #endif /* defined(CONFIG_CMD_IDE) */
 440
 441 /*
 442  * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
 443  * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
 444  * to 0xFFFF, watchdog timeouts after about 64s. For details refer
 445  * to chapter 36 of the MPC5121e Reference Manual.
 446  */
 447 /* #define CONFIG_WATCHDOG */           /* enable watchdog */
 448 #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
 449
 450  /*
 451  * Miscellaneous configurable options
 452  */
 453 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 454 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 455
 456 #ifdef CONFIG_CMD_KGDB
 457         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 458 #else
 459         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 460 #endif
 461
 462 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
 463 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 464 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 465
 466 /*
 467  * For booting Linux, the board info and command line data
 468  * have to be in the first 256 MB of memory, since this is
 469  * the maximum mapped by the Linux kernel during initialization.
 470  */
 471 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Initial Memory map for Linux*/
 472
 473 /* Cache Configuration */
 474 #define CONFIG_SYS_DCACHE_SIZE          32768
 475 #define CONFIG_SYS_CACHELINE_SIZE       32
 476 #ifdef CONFIG_CMD_KGDB
 477 #define CONFIG_SYS_CACHELINE_SHIFT      5       /*log base 2 of the above value*/
 478 #endif
 479
 480 #define CONFIG_SYS_HID0_INIT    0x000000000
 481 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
 482 #define CONFIG_SYS_HID2 HID2_HBE
 483
 484 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 485
 486 #ifdef CONFIG_CMD_KGDB
 487 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 488 #endif
 489
 490 /*
 491  * Environment Configuration
 492  */
 493 #define CONFIG_TIMESTAMP
 494
 495 #define CONFIG_HOSTNAME         mpc5121ads
 496 #define CONFIG_BOOTFILE         "mpc5121ads/uImage"
 497 #define CONFIG_ROOTPATH         "/opt/eldk/ppc_6xx"
 498
 499 #define CONFIG_LOADADDR         400000  /* default location for tftp and bootm */
 500
 501 #undef  CONFIG_BOOTARGS                 /* the boot command will set bootargs */
 502
 503 #define CONFIG_PREBOOT  "echo;" \
 504         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 505         "echo"
 506
 507 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 508         "u-boot_addr_r=200000\0"                                        \
 509         "kernel_addr_r=600000\0"                                        \
 510         "fdt_addr_r=880000\0"                                           \
 511         "ramdisk_addr_r=900000\0"                                       \
 512         "u-boot_addr=FFF00000\0"                                        \
 513         "kernel_addr=FFAC0000\0"                                        \
 514         "fdt_addr=FFEC0000\0"                                           \
 515         "ramdisk_addr=FEAC0000\0"                                       \
 516         "ramdiskfile=mpc5121ads/uRamdisk\0"                             \
 517         "u-boot=mpc5121ads/u-boot.bin\0"                                \
 518         "bootfile=mpc5121ads/uImage\0"                                  \
 519         "fdtfile=mpc5121ads/mpc5121ads.dtb\0"                           \
 520         "rootpath=/opt/eldk/ppc_6xx\n"                                  \
 521         "netdev=eth0\0"                                                 \
 522         "consdev=ttyPSC0\0"                                             \
 523         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 524                 "nfsroot=${serverip}:${rootpath}\0"                     \
 525         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 526         "addip=setenv bootargs ${bootargs} "                            \
 527                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 528                 ":${hostname}:${netdev}:off panic=1\0"                  \
 529         "addtty=setenv bootargs ${bootargs} "                           \
 530                 "console=${consdev},${baudrate}\0"                      \
 531         "flash_nfs=run nfsargs addip addtty;"                           \
 532                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 533         "flash_self=run ramargs addip addtty;"                          \
 534                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 535         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
 536                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 537                 "run nfsargs addip addtty;"                             \
 538                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 539         "net_self=tftp ${kernel_addr_r} ${bootfile};"                   \
 540                 "tftp ${ramdisk_addr_r} ${ramdiskfile};"                \
 541                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 542                 "run ramargs addip addtty;"                             \
 543                 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
 544         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                        \
 545         "update=protect off ${u-boot_addr} +${filesize};"               \
 546                 "era ${u-boot_addr} +${filesize};"                      \
 547                 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"    \
 548         "upd=run load update\0"                                         \
 549         ""
 550
 551 #define CONFIG_BOOTCOMMAND      "run flash_self"
 552
 553 #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES      1
 554
 555 #define OF_CPU                  "PowerPC,5121@0"
 556 #define OF_SOC_COMPAT           "fsl,mpc5121-immr"
 557 #define OF_TBCLK                (bd->bi_busfreq / 4)
 558 #define OF_STDOUT_PATH          "/soc@80000000/serial@11300"
 559
 560 /*-----------------------------------------------------------------------
 561  * IDE/ATA stuff
 562  *-----------------------------------------------------------------------
 563  */
 564
 565 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 566 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 567 #undef  CONFIG_IDE_LED                  /* LED   for IDE not supported  */
 568
 569 #define CONFIG_IDE_RESET                /* reset for IDE supported      */
 570 #define CONFIG_IDE_PREINIT
 571
 572 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 573 #define CONFIG_SYS_IDE_MAXDEVICE        2       /* max. 1 drive per IDE bus     */
 574
 575 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 576 #define CONFIG_SYS_ATA_BASE_ADDR        get_pata_base()
 577
 578 /* Offset for data I/O                  RefMan MPC5121EE Table 28-10    */
 579 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x00A0)
 580
 581 /* Offset for normal register accesses  */
 582 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 583
 584 /* Offset for alternate registers       RefMan MPC5121EE Table 28-23    */
 585 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x00D8)
 586
 587 /* Interval between registers   */
 588 #define CONFIG_SYS_ATA_STRIDE           4
 589
 590 #define ATA_BASE_ADDR                   get_pata_base()
 591
 592 /*
 593  * Control register bit definitions
 594  */
 595 #define FSL_ATA_CTRL_FIFO_RST_B         0x80000000
 596 #define FSL_ATA_CTRL_ATA_RST_B          0x40000000
 597 #define FSL_ATA_CTRL_FIFO_TX_EN         0x20000000
 598 #define FSL_ATA_CTRL_FIFO_RCV_EN        0x10000000
 599 #define FSL_ATA_CTRL_DMA_PENDING        0x08000000
 600 #define FSL_ATA_CTRL_DMA_ULTRA          0x04000000
 601 #define FSL_ATA_CTRL_DMA_WRITE          0x02000000
 602 #define FSL_ATA_CTRL_IORDY_EN           0x01000000
 603
 604 #endif  /* __CONFIG_H */