include/configs/mpc5121ads.h

   1 /*
   2  * (C) Copyright 2007-2009 DENX Software Engineering
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * MPC5121ADS board configuration file
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 #define CONFIG_MPC5121ADS 1
  31 /*
  32  * Memory map for the MPC5121ADS board:
  33  *
  34  * 0x0000_0000 - 0x0FFF_FFFF    DDR RAM (256 MB)
  35  * 0x3000_0000 - 0x3001_FFFF    SRAM (128 KB)
  36  * 0x8000_0000 - 0x803F_FFFF    IMMR (4 MB)
  37  * 0x8200_0000 - 0x8200_001F    CPLD (32 B)
  38  * 0x8400_0000 - 0x82FF_FFFF    PCI I/O space (16 MB)
  39  * 0xA000_0000 - 0xAFFF_FFFF    PCI memory space (256 MB)
  40  * 0xB000_0000 - 0xBFFF_FFFF    PCI memory mapped I/O space (256 MB)
  41  * 0xFC00_0000 - 0xFFFF_FFFF    NOR Boot FLASH (64 MB)
  42  */
  43
  44 /*
  45  * High Level Configuration Options
  46  */
  47 #define CONFIG_E300             1       /* E300 Family */
  48 #define CONFIG_MPC512X          1       /* MPC512X family */
  49 #define CONFIG_FSL_DIU_FB       1       /* FSL DIU */
  50
  51 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  52
  53 /* video */
  54 #undef CONFIG_VIDEO
  55
  56 #ifdef CONFIG_VIDEO
  57 #define CONFIG_CMD_BMP
  58 #define CONFIG_CFB_CONSOLE
  59 #define CONFIG_VGA_AS_SINGLE_DEVICE
  60 #define CONFIG_VIDEO_LOGO
  61 #define CONFIG_VIDEO_BMP_LOGO
  62 #endif
  63
  64 /* CONFIG_PCI is defined at config time */
  65
  66 #ifdef CONFIG_MPC5121ADS_REV2
  67 #define CONFIG_SYS_MPC512X_CLKIN        66000000        /* in Hz */
  68 #else
  69 #define CONFIG_SYS_MPC512X_CLKIN        33333333        /* in Hz */
  70 #define CONFIG_PCI
  71 #endif
  72
  73 #define CONFIG_BOARD_EARLY_INIT_F               /* call board_early_init_f() */
  74 #define CONFIG_MISC_INIT_R
  75
  76 #define CONFIG_SYS_IMMR         0x80000000
  77 #define CONFIG_SYS_DIU_ADDR             (CONFIG_SYS_IMMR+0x2100)
  78
  79 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  80 #define CONFIG_SYS_MEMTEST_END          0x00400000
  81
  82 /*
  83  * DDR Setup - manually set all parameters as there's no SPD etc.
  84  */
  85 #ifdef CONFIG_MPC5121ADS_REV2
  86 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
  87 #else
  88 #define CONFIG_SYS_DDR_SIZE             512             /* MB */
  89 #endif
  90 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is system memory*/
  91 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  92 #define CONFIG_SYS_MAX_RAM_SIZE         0x20000000
  93
  94 #define CONFIG_SYS_IOCTRL_MUX_DDR       0x00000036
  95
  96 /* DDR Controller Configuration
  97  *
  98  * SYS_CFG:
  99  *      [31:31] MDDRC Soft Reset:       Diabled
 100  *      [30:30] DRAM CKE pin:           Enabled
 101  *      [29:29] DRAM CLK:               Enabled
 102  *      [28:28] Command Mode:           Enabled (For initialization only)
 103  *      [27:25] DRAM Row Select:        dram_row[15:0] = magenta_address[25:10]
 104  *      [24:21] DRAM Bank Select:       dram_bank[1:0] = magenta_address[11:10]
 105  *      [20:19] Read Test:              DON'T USE
 106  *      [18:18] Self Refresh:           Enabled
 107  *      [17:17] 16bit Mode:             Disabled
 108  *      [16:13] Ready Delay:            2
 109  *      [12:12] Half DQS Delay:         Disabled
 110  *      [11:11] Quarter DQS Delay:      Disabled
 111  *      [10:08] Write Delay:            2
 112  *      [07:07] Early ODT:              Disabled
 113  *      [06:06] On DIE Termination:     Disabled
 114  *      [05:05] FIFO Overflow Clear:    DON'T USE here
 115  *      [04:04] FIFO Underflow Clear:   DON'T USE here
 116  *      [03:03] FIFO Overflow Pending:  DON'T USE here
 117  *      [02:02] FIFO Underlfow Pending: DON'T USE here
 118  *      [01:01] FIFO Overlfow Enabled:  Enabled
 119  *      [00:00] FIFO Underflow Enabled: Enabled
 120  * TIME_CFG0
 121  *      [31:16] DRAM Refresh Time:      0 CSB clocks
 122  *      [15:8]  DRAM Command Time:      0 CSB clocks
 123  *      [07:00] DRAM Precharge Time:    0 CSB clocks
 124  * TIME_CFG1
 125  *      [31:26] DRAM tRFC:
 126  *      [25:21] DRAM tWR1:
 127  *      [20:17] DRAM tWRT1:
 128  *      [16:11] DRAM tDRR:
 129  *      [10:05] DRAM tRC:
 130  *      [04:00] DRAM tRAS:
 131  * TIME_CFG2
 132  *      [31:28] DRAM tRCD:
 133  *      [27:23] DRAM tFAW:
 134  *      [22:19] DRAM tRTW1:
 135  *      [18:15] DRAM tCCD:
 136  *      [14:10] DRAM tRTP:
 137  *      [09:05] DRAM tRP:
 138  *      [04:00] DRAM tRPA
 139  */
 140 #ifdef CONFIG_MPC5121ADS_REV2
 141 #define CONFIG_SYS_MDDRC_SYS_CFG        0xE8604A00
 142 #define CONFIG_SYS_MDDRC_TIME_CFG1      0x54EC1168
 143 #define CONFIG_SYS_MDDRC_TIME_CFG2      0x35210864
 144 #else
 145 #define CONFIG_SYS_MDDRC_SYS_CFG        0xEA804A00
 146 #define CONFIG_SYS_MDDRC_TIME_CFG1      0x68EC1168
 147 #define CONFIG_SYS_MDDRC_TIME_CFG2      0x34310864
 148 #endif
 149 #define CONFIG_SYS_MDDRC_TIME_CFG0      0x06183D2E
 150
 151 #define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA         0xEA802B00
 152 #define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA       0x690e1189
 153 #define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA       0x35310864
 154
 155 #define CONFIG_SYS_DDRCMD_NOP           0x01380000
 156 #define CONFIG_SYS_DDRCMD_PCHG_ALL      0x01100400
 157 #define CONFIG_SYS_DDRCMD_EM2           0x01020000
 158 #define CONFIG_SYS_DDRCMD_EM3           0x01030000
 159 #define CONFIG_SYS_DDRCMD_EN_DLL        0x01010000
 160 #define CONFIG_SYS_DDRCMD_RFSH          0x01080000
 161
 162 #define DDRCMD_EMR_OCD(pr, ohm) ( \
 163         (1 << 24)          | /* MDDRC Command Request   */ \
 164         (1 << 16)          | /* MODE Reg BA[2:0]        */ \
 165         (0 << 12)          | /* Outputs 0=Enabled       */ \
 166         (0 << 11)          | /* RDQS                    */ \
 167         (1 << 10)          | /* DQS#                    */ \
 168         (pr <<  7)         | /* OCD prog 7=deflt,0=exit */ \
 169                     /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \
 170         ((ohm & 0x2) <<  5)| /* Rtt1                    */ \
 171         (0 <<  3)          | /* additive posted CAS#    */ \
 172         ((ohm & 0x1) <<  2)| /* Rtt0                    */ \
 173         (0 <<  0)          | /* Output Drive Strength   */ \
 174         (0 <<  0))           /* DLL Enable 0=Normal     */
 175
 176 #define CONFIG_SYS_DDRCMD_OCD_DEFAULT   DDRCMD_EMR_OCD(7, 0)
 177 #define CONFIG_SYS_ELPIDA_OCD_EXIT      DDRCMD_EMR_OCD(0, 0)
 178
 179 #define DDRCMD_MODE_REG(cas, wr) ( \
 180         (1 << 24)    | /* MDDRC Command Request                 */ \
 181         (0 << 16)    | /* MODE Reg BA[2:0]                      */ \
 182         ((wr-1) << 9)| /* Write Recovery                        */ \
 183         (cas << 4)   | /* CAS                                   */ \
 184         (0 << 3)     | /* Burst Type:0=Sequential,1=Interleaved */ \
 185         (2 << 0))      /* 4 or 8 Burst Length:0x2=4 0x3=8       */
 186
 187 #define CONFIG_SYS_MICRON_INIT_DEV_OP   DDRCMD_MODE_REG(3, 3)
 188 #define CONFIG_SYS_ELPIDA_INIT_DEV_OP   DDRCMD_MODE_REG(4, 4)
 189 #define CONFIG_SYS_ELPIDA_RES_DLL       (DDRCMD_MODE_REG(4, 4) | (1 << 8))
 190
 191 /* DDR Priority Manager Configuration */
 192 #define CONFIG_SYS_MDDRCGRP_PM_CFG1     0x00077777
 193 #define CONFIG_SYS_MDDRCGRP_PM_CFG2     0x00000000
 194 #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG  0x00000001
 195 #define CONFIG_SYS_MDDRCGRP_LUT0_MU     0xFFEEDDCC
 196 #define CONFIG_SYS_MDDRCGRP_LUT0_ML     0xBBAAAAAA
 197 #define CONFIG_SYS_MDDRCGRP_LUT1_MU     0x66666666
 198 #define CONFIG_SYS_MDDRCGRP_LUT1_ML     0x55555555
 199 #define CONFIG_SYS_MDDRCGRP_LUT2_MU     0x44444444
 200 #define CONFIG_SYS_MDDRCGRP_LUT2_ML     0x44444444
 201 #define CONFIG_SYS_MDDRCGRP_LUT3_MU     0x55555555
 202 #define CONFIG_SYS_MDDRCGRP_LUT3_ML     0x55555558
 203 #define CONFIG_SYS_MDDRCGRP_LUT4_MU     0x11111111
 204 #define CONFIG_SYS_MDDRCGRP_LUT4_ML     0x11111122
 205 #define CONFIG_SYS_MDDRCGRP_LUT0_AU     0xaaaaaaaa
 206 #define CONFIG_SYS_MDDRCGRP_LUT0_AL     0xaaaaaaaa
 207 #define CONFIG_SYS_MDDRCGRP_LUT1_AU     0x66666666
 208 #define CONFIG_SYS_MDDRCGRP_LUT1_AL     0x66666666
 209 #define CONFIG_SYS_MDDRCGRP_LUT2_AU     0x11111111
 210 #define CONFIG_SYS_MDDRCGRP_LUT2_AL     0x11111111
 211 #define CONFIG_SYS_MDDRCGRP_LUT3_AU     0x11111111
 212 #define CONFIG_SYS_MDDRCGRP_LUT3_AL     0x11111111
 213 #define CONFIG_SYS_MDDRCGRP_LUT4_AU     0x11111111
 214 #define CONFIG_SYS_MDDRCGRP_LUT4_AL     0x11111111
 215
 216 /*
 217  * NOR FLASH on the Local Bus
 218  */
 219 #undef CONFIG_BKUP_FLASH
 220 #define CONFIG_SYS_FLASH_CFI                            /* use the Common Flash Interface */
 221 #define CONFIG_FLASH_CFI_DRIVER                 /* use the CFI driver */
 222 #ifdef CONFIG_BKUP_FLASH
 223 #define CONFIG_SYS_FLASH_BASE           0xFF800000      /* start of FLASH   */
 224 #define CONFIG_SYS_FLASH_SIZE           0x00800000      /* max flash size in bytes */
 225 #else
 226 #define CONFIG_SYS_FLASH_BASE           0xFC000000      /* start of FLASH   */
 227 #define CONFIG_SYS_FLASH_SIZE           0x04000000      /* max flash size in bytes */
 228 #endif
 229 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 230 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 231 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
 232 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* max sectors per device */
 233
 234 #undef CONFIG_SYS_FLASH_CHECKSUM
 235
 236 /*
 237  * NAND FLASH
 238  * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
 239  */
 240 #define CONFIG_CMD_NAND                                 /* enable NAND support */
 241 #define CONFIG_JFFS2_NAND                               /* with JFFS2 on it */
 242 #define CONFIG_NAND_MPC5121_NFC
 243 #define CONFIG_SYS_NAND_BASE            0x40000000
 244
 245 #define CONFIG_SYS_MAX_NAND_DEVICE      2
 246 #define NAND_MAX_CHIPS                  CONFIG_SYS_MAX_NAND_DEVICE
 247 #define CONFIG_SYS_NAND_SELECT_DEVICE   /* driver supports mutipl. chips */
 248
 249 /*
 250  * Configuration parameters for MPC5121 NAND driver
 251  */
 252 #define CONFIG_FSL_NFC_WIDTH 1
 253 #define CONFIG_FSL_NFC_WRITE_SIZE 2048
 254 #define CONFIG_FSL_NFC_SPARE_SIZE 64
 255 #define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
 256
 257 /*
 258  * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
 259  * window is 64KB
 260  */
 261 #define CONFIG_SYS_CPLD_BASE            0x82000000
 262 #define CONFIG_SYS_CPLD_SIZE            0x00010000      /* 64 KB */
 263
 264 #define CONFIG_SYS_SRAM_BASE            0x30000000
 265 #define CONFIG_SYS_SRAM_SIZE            0x00020000      /* 128 KB */
 266
 267 #define CONFIG_SYS_CS0_CFG              0x05059310      /* ALE active low, data size 4bytes */
 268 #define CONFIG_SYS_CS2_CFG              0x05059010      /* ALE active low, data size 1byte */
 269 #define CONFIG_SYS_CS_ALETIMING 0x00000005      /* Use alternative CS timing for CS0 and CS2 */
 270
 271 /* Use SRAM for initial stack */
 272 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_SRAM_BASE            /* Initial RAM address */
 273 #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE            /* End of used area in RAM */
 274
 275 #define CONFIG_SYS_GBL_DATA_SIZE        0x100                   /* num bytes initial data */
 276 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 277 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 278
 279 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE            /* Start of monitor */
 280 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)            /* Reserve 512 kB for Mon */
 281 #ifdef  CONFIG_FSL_DIU_FB
 282 #define CONFIG_SYS_MALLOC_LEN           (6 * 1024 * 1024)       /* Reserved for malloc */
 283 #else
 284 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
 285 #endif
 286
 287 /*
 288  * Serial Port
 289  */
 290 #define CONFIG_CONS_INDEX     1
 291
 292 /*
 293  * Serial console configuration
 294  */
 295 #define CONFIG_PSC_CONSOLE      3       /* console is on PSC3 */
 296 #if CONFIG_PSC_CONSOLE != 3
 297 #error CONFIG_PSC_CONSOLE must be 3
 298 #endif
 299 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
 300 #define CONFIG_SYS_BAUDRATE_TABLE  \
 301         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 302
 303 #define CONSOLE_FIFO_TX_SIZE    FIFOC_PSC3_TX_SIZE
 304 #define CONSOLE_FIFO_TX_ADDR    FIFOC_PSC3_TX_ADDR
 305 #define CONSOLE_FIFO_RX_SIZE    FIFOC_PSC3_RX_SIZE
 306 #define CONSOLE_FIFO_RX_ADDR    FIFOC_PSC3_RX_ADDR
 307
 308 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 309 /* Use the HUSH parser */
 310 #define CONFIG_SYS_HUSH_PARSER
 311 #ifdef  CONFIG_SYS_HUSH_PARSER
 312 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 313 #endif
 314
 315 /*
 316  * PCI
 317  */
 318 #ifdef CONFIG_PCI
 319
 320 /*
 321  * General PCI
 322  */
 323 #define CONFIG_SYS_PCI_MEM_BASE 0xA0000000
 324 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
 325 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000      /* 256M */
 326 #define CONFIG_SYS_PCI_MMIO_BASE        (CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE)
 327 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 328 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000      /* 256M */
 329 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 330 #define CONFIG_SYS_PCI_IO_PHYS          0x84000000
 331 #define CONFIG_SYS_PCI_IO_SIZE          0x01000000      /* 16M */
 332
 333
 334 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 335
 336 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 337
 338 #endif
 339
 340 /* I2C */
 341 #define CONFIG_HARD_I2C                 /* I2C with hardware support */
 342 #undef CONFIG_SOFT_I2C                  /* so disable bit-banged I2C */
 343 #define CONFIG_I2C_MULTI_BUS
 344 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address */
 345 #define CONFIG_SYS_I2C_SLAVE            0x7F
 346 #if 0
 347 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}}      /* Don't probe these addrs */
 348 #endif
 349
 350 /*
 351  * IIM - IC Identification Module
 352  */
 353 #undef CONFIG_IIM
 354
 355 /*
 356  * EEPROM configuration
 357  */
 358 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2       /* 16-bit EEPROM address */
 359 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* Atmel: AT24C32A-10TQ-2.7 */
 360 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* 10ms of delay */
 361 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* 32-Byte Page Write Mode */
 362
 363 /*
 364  * Ethernet configuration
 365  */
 366 #define CONFIG_MPC512x_FEC      1
 367 #define CONFIG_NET_MULTI
 368 #define CONFIG_PHY_ADDR         0x1
 369 #define CONFIG_MII              1       /* MII PHY management           */
 370 #define CONFIG_FEC_AN_TIMEOUT   1
 371 #define CONFIG_HAS_ETH0
 372
 373 /*
 374  * Configure on-board RTC
 375  */
 376 #define CONFIG_RTC_M41T62                       /* use M41T62 rtc via i2 */
 377 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* at address 0x68              */
 378
 379 /*
 380  * Environment
 381  */
 382 #define CONFIG_ENV_IS_IN_FLASH  1
 383 /* This has to be a multiple of the Flash sector size */
 384 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 385 #define CONFIG_ENV_SIZE         0x2000
 386 #ifdef CONFIG_BKUP_FLASH
 387 #define CONFIG_ENV_SECT_SIZE    0x20000 /* one sector (256K) for env */
 388 #else
 389 #define CONFIG_ENV_SECT_SIZE    0x40000 /* one sector (256K) for env */
 390 #endif
 391
 392 /* Address and size of Redundant Environment Sector     */
 393 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 394 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 395
 396 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 397 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 398
 399 #include <config_cmd_default.h>
 400
 401 #define CONFIG_CMD_ASKENV
 402 #define CONFIG_CMD_DATE
 403 #define CONFIG_CMD_DHCP
 404 #define CONFIG_CMD_EEPROM
 405 #define CONFIG_CMD_EXT2
 406 #define CONFIG_CMD_I2C
 407 #define CONFIG_CMD_IDE
 408 #define CONFIG_CMD_JFFS2
 409 #define CONFIG_CMD_MII
 410 #define CONFIG_CMD_NFS
 411 #define CONFIG_CMD_PING
 412 #define CONFIG_CMD_REGINFO
 413
 414 #undef CONFIG_CMD_FUSE
 415
 416 #if defined(CONFIG_PCI)
 417 #define CONFIG_CMD_PCI
 418 #endif
 419
 420 /*
 421  * Dynamic MTD partition support
 422  */
 423 #define CONFIG_CMD_MTDPARTS
 424 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 425 #define CONFIG_FLASH_CFI_MTD
 426 #define MTDIDS_DEFAULT          "nor0=fc000000.flash,nand0=mpc5121.nand"
 427
 428 /*
 429  * NOR flash layout:
 430  *
 431  * FC000000 - FEABFFFF 42.75 MiB        User Data
 432  * FEAC0000 - FFABFFFF  16 MiB          Root File System
 433  * FFAC0000 - FFEBFFFF   4 MiB          Linux Kernel
 434  * FFEC0000 - FFEFFFFF 256 KiB          Device Tree
 435  * FFF00000 - FFFFFFFF   1 MiB          U-Boot (up to 512 KiB) and 2 x * env
 436  *
 437  * NAND flash layout: one big partition
 438  */
 439 #define MTDPARTS_DEFAULT        "mtdparts=fc000000.flash:43776k(user)," \
 440                                                 "16m(rootfs),"          \
 441                                                 "4m(kernel),"           \
 442                                                 "256k(dtb),"            \
 443                                                 "1m(u-boot);"           \
 444                                         "mpc5121.nand:-(data)"
 445
 446
 447 #if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2)
 448 #define CONFIG_DOS_PARTITION
 449 #define CONFIG_MAC_PARTITION
 450 #define CONFIG_ISO_PARTITION
 451 #endif /* defined(CONFIG_CMD_IDE) */
 452
 453 /*
 454  * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
 455  * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
 456  * to 0xFFFF, watchdog timeouts after about 64s. For details refer
 457  * to chapter 36 of the MPC5121e Reference Manual.
 458  */
 459 /* #define CONFIG_WATCHDOG */           /* enable watchdog */
 460 #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
 461
 462  /*
 463  * Miscellaneous configurable options
 464  */
 465 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 466 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 467 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 468
 469 #ifdef CONFIG_CMD_KGDB
 470         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 471 #else
 472         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 473 #endif
 474
 475
 476 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
 477 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 478 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 479 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 480
 481 /*
 482  * For booting Linux, the board info and command line data
 483  * have to be in the first 256 MB of memory, since this is
 484  * the maximum mapped by the Linux kernel during initialization.
 485  */
 486 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Initial Memory map for Linux*/
 487
 488 /* Cache Configuration */
 489 #define CONFIG_SYS_DCACHE_SIZE          32768
 490 #define CONFIG_SYS_CACHELINE_SIZE       32
 491 #ifdef CONFIG_CMD_KGDB
 492 #define CONFIG_SYS_CACHELINE_SHIFT      5       /*log base 2 of the above value*/
 493 #endif
 494
 495 #define CONFIG_SYS_HID0_INIT    0x000000000
 496 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
 497 #define CONFIG_SYS_HID2 HID2_HBE
 498
 499 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 500
 501 /*
 502  * Internal Definitions
 503  *
 504  * Boot Flags
 505  */
 506 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
 507 #define BOOTFLAG_WARM           0x02    /* Software reboot */
 508
 509 #ifdef CONFIG_CMD_KGDB
 510 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 511 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 512 #endif
 513
 514 /*
 515  * Environment Configuration
 516  */
 517 #define CONFIG_TIMESTAMP
 518
 519 #define CONFIG_HOSTNAME         mpc5121ads
 520 #define CONFIG_BOOTFILE         mpc5121ads/uImage
 521 #define CONFIG_ROOTPATH         /opt/eldk/ppc_6xx
 522
 523 #define CONFIG_LOADADDR         400000  /* default location for tftp and bootm */
 524
 525 #define CONFIG_BOOTDELAY        5       /* -1 disables auto-boot */
 526 #undef  CONFIG_BOOTARGS                 /* the boot command will set bootargs */
 527
 528 #define CONFIG_BAUDRATE         115200
 529
 530 #define CONFIG_PREBOOT  "echo;" \
 531         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 532         "echo"
 533
 534 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 535         "u-boot_addr_r=200000\0"                                        \
 536         "kernel_addr_r=600000\0"                                        \
 537         "fdt_addr_r=880000\0"                                           \
 538         "ramdisk_addr_r=900000\0"                                       \
 539         "u-boot_addr=FFF00000\0"                                        \
 540         "kernel_addr=FFAC0000\0"                                        \
 541         "fdt_addr=FFEC0000\0"                                           \
 542         "ramdisk_addr=FEAC0000\0"                                       \
 543         "ramdiskfile=mpc5121ads/uRamdisk\0"                             \
 544         "u-boot=mpc5121ads/u-boot.bin\0"                                \
 545         "bootfile=mpc5121ads/uImage\0"                                  \
 546         "fdtfile=mpc5121ads/mpc5121ads.dtb\0"                           \
 547         "rootpath=/opt/eldk/ppc_6xx\n"                                  \
 548         "netdev=eth0\0"                                                 \
 549         "consdev=ttyPSC0\0"                                             \
 550         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 551                 "nfsroot=${serverip}:${rootpath}\0"                     \
 552         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 553         "addip=setenv bootargs ${bootargs} "                            \
 554                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 555                 ":${hostname}:${netdev}:off panic=1\0"                  \
 556         "addtty=setenv bootargs ${bootargs} "                           \
 557                 "console=${consdev},${baudrate}\0"                      \
 558         "flash_nfs=run nfsargs addip addtty;"                           \
 559                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 560         "flash_self=run ramargs addip addtty;"                          \
 561                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 562         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
 563                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 564                 "run nfsargs addip addtty;"                             \
 565                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 566         "net_self=tftp ${kernel_addr_r} ${bootfile};"                   \
 567                 "tftp ${ramdisk_addr_r} ${ramdiskfile};"                \
 568                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 569                 "run ramargs addip addtty;"                             \
 570                 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
 571         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                        \
 572         "update=protect off ${u-boot_addr} +${filesize};"               \
 573                 "era ${u-boot_addr} +${filesize};"                      \
 574                 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"    \
 575         "upd=run load update\0"                                         \
 576         ""
 577
 578 #define CONFIG_BOOTCOMMAND      "run flash_self"
 579
 580 #define CONFIG_OF_LIBFDT        1
 581 #define CONFIG_OF_BOARD_SETUP   1
 582 #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES      1
 583
 584 #define OF_CPU                  "PowerPC,5121@0"
 585 #define OF_SOC_COMPAT           "fsl,mpc5121-immr"
 586 #define OF_TBCLK                (bd->bi_busfreq / 4)
 587 #define OF_STDOUT_PATH          "/soc@80000000/serial@11300"
 588
 589 /*-----------------------------------------------------------------------
 590  * IDE/ATA stuff
 591  *-----------------------------------------------------------------------
 592  */
 593
 594 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 595 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 596 #undef  CONFIG_IDE_LED                  /* LED   for IDE not supported  */
 597
 598 #define CONFIG_IDE_RESET                /* reset for IDE supported      */
 599 #define CONFIG_IDE_PREINIT
 600
 601 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 602 #define CONFIG_SYS_IDE_MAXDEVICE        2       /* max. 1 drive per IDE bus     */
 603
 604 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 605 #define CONFIG_SYS_ATA_BASE_ADDR        get_pata_base()
 606
 607 /* Offset for data I/O                  RefMan MPC5121EE Table 28-10    */
 608 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x00A0)
 609
 610 /* Offset for normal register accesses  */
 611 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 612
 613 /* Offset for alternate registers       RefMan MPC5121EE Table 28-23    */
 614 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x00D8)
 615
 616 /* Interval between registers   */
 617 #define CONFIG_SYS_ATA_STRIDE           4
 618
 619 #define ATA_BASE_ADDR                   get_pata_base()
 620
 621 /*
 622  * Control register bit definitions
 623  */
 624 #define FSL_ATA_CTRL_FIFO_RST_B         0x80000000
 625 #define FSL_ATA_CTRL_ATA_RST_B          0x40000000
 626 #define FSL_ATA_CTRL_FIFO_TX_EN         0x20000000
 627 #define FSL_ATA_CTRL_FIFO_RCV_EN        0x10000000
 628 #define FSL_ATA_CTRL_DMA_PENDING        0x08000000
 629 #define FSL_ATA_CTRL_DMA_ULTRA          0x04000000
 630 #define FSL_ATA_CTRL_DMA_WRITE          0x02000000
 631 #define FSL_ATA_CTRL_IORDY_EN           0x01000000
 632
 633 #endif  /* __CONFIG_H */