include/configs/mpr2.h

   1 /*
   2  * Configuation settings for MPR2
   3  *
   4  * Copyright (C) 2008
   5  * Mark Jonas <mark.jonas@de.bosch.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __MPR2_H
  11 #define __MPR2_H
  12
  13 /* Supported commands */
  14
  15 /* Default environment variables */
  16 #define CONFIG_BOOTFILE         "/boot/zImage"
  17 #define CONFIG_LOADADDR         0x8E000000
  18
  19 /* CPU and platform */
  20 #define CONFIG_CPU_SH7720       1
  21
  22 #define CONFIG_DISPLAY_BOARDINFO
  23
  24 /* U-Boot internals */
  25 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
  26 #define CONFIG_SYS_BAUDRATE_TABLE       { 115200 }      /* List of legal baudrate settings for this board */
  27 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
  28 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  29 #define CONFIG_SYS_MONITOR_LEN          (128 * 1024)
  30 #define CONFIG_SYS_MALLOC_LEN           (256 * 1024)
  31
  32 /* Memory */
  33 #define CONFIG_SYS_SDRAM_BASE           0x8C000000
  34 #define CONFIG_SYS_SDRAM_SIZE           (64 * 1024 * 1024)
  35 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
  36 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
  37
  38 /* Flash */
  39 #define CONFIG_SYS_FLASH_CFI
  40 #define CONFIG_FLASH_CFI_DRIVER
  41 #define CONFIG_SYS_FLASH_EMPTY_INFO
  42 #define CONFIG_SYS_FLASH_BASE           0xA0000000
  43 #define CONFIG_SYS_MAX_FLASH_SECT       256
  44 #define CONFIG_SYS_MAX_FLASH_BANKS      1
  45 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
  46 #define CONFIG_ENV_SECT_SIZE    (128 * 1024)
  47 #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
  48 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
  49 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000
  50 #define CONFIG_SYS_FLASH_WRITE_TOUT     500
  51
  52 /* Clocks */
  53 #define CONFIG_SYS_CLK_FREQ     24000000
  54 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
  55 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
  56 #define CONFIG_SYS_TMU_CLK_DIV          4       /* 4 (default), 16, 64, 256 or 1024 */
  57
  58 /* UART */
  59 #define CONFIG_CONS_SCIF0       1
  60
  61 #endif  /* __MPR2_H */