include/configs/ms7720se.h

   1 /*
   2  * Configuation settings for the Hitachi Solution Engine 7720
   3  *
   4  * Copyright (C) 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __MS7720SE_H
  10 #define __MS7720SE_H
  11
  12 #define CONFIG_CPU_SH7720       1
  13 #define CONFIG_MS7720SE         1
  14
  15 #define CONFIG_CMD_SDRAM
  16 #define CONFIG_CMD_CACHE
  17 #define CONFIG_CMD_PCMCIA
  18 #define CONFIG_CMD_IDE
  19 #define CONFIG_CMD_EXT2
  20
  21 #define CONFIG_BAUDRATE         115200
  22 #define CONFIG_BOOTARGS         "console=ttySC0,115200"
  23 #define CONFIG_BOOTFILE         "/boot/zImage"
  24 #define CONFIG_LOADADDR         0x8E000000
  25
  26 #define CONFIG_VERSION_VARIABLE
  27 #undef  CONFIG_SHOW_BOOT_PROGRESS
  28
  29 /* MEMORY */
  30 #define MS7720SE_SDRAM_BASE             0x8C000000
  31 #define MS7720SE_FLASH_BASE_1           0xA0000000
  32 #define MS7720SE_FLASH_BANK_SIZE        (8 * 1024 * 1024)
  33
  34 #define CONFIG_SYS_TEXT_BASE    0x8FFC0000
  35 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
  36 #define CONFIG_SYS_CBSIZE       256     /* Buffer size for input from the Console */
  37 #define CONFIG_SYS_PBSIZE       256     /* Buffer size for Console output */
  38 #define CONFIG_SYS_MAXARGS      16      /* max args accepted for monitor commands */
  39 /* Buffer size for Boot Arguments passed to kernel */
  40 #define CONFIG_SYS_BARGSIZE     512
  41 /* List of legal baudrate settings for this board */
  42 #define CONFIG_SYS_BAUDRATE_TABLE       { 115200 }
  43
  44 /* SCIF */
  45 #define CONFIG_SCIF_CONSOLE     1
  46 #define CONFIG_CONS_SCIF0       1
  47
  48 #define CONFIG_SYS_MEMTEST_START        MS7720SE_SDRAM_BASE
  49 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
  50
  51 #define CONFIG_SYS_SDRAM_BASE           MS7720SE_SDRAM_BASE
  52 #define CONFIG_SYS_SDRAM_SIZE           (64 * 1024 * 1024)
  53
  54 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
  55 #define CONFIG_SYS_MONITOR_BASE MS7720SE_FLASH_BASE_1
  56 #define CONFIG_SYS_MONITOR_LEN          (128 * 1024)
  57 #define CONFIG_SYS_MALLOC_LEN           (256 * 1024)
  58 #define CONFIG_SYS_BOOTMAPSZ            (8 * 1024 * 1024)
  59
  60 /* FLASH */
  61 #define CONFIG_SYS_FLASH_CFI
  62 #define CONFIG_FLASH_CFI_DRIVER
  63 #undef  CONFIG_SYS_FLASH_QUIET_TEST
  64 #define CONFIG_SYS_FLASH_EMPTY_INFO     /* print 'E' for empty sector on flinfo */
  65
  66 #define CONFIG_SYS_FLASH_BASE           MS7720SE_FLASH_BASE_1
  67
  68 #define CONFIG_SYS_MAX_FLASH_SECT       150
  69 #define CONFIG_SYS_MAX_FLASH_BANKS      1
  70 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
  71
  72 #define CONFIG_ENV_IS_IN_FLASH
  73 #define CONFIG_ENV_SECT_SIZE    (64 * 1024)
  74 #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
  75 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
  76 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000
  77 #define CONFIG_SYS_FLASH_WRITE_TOUT     500
  78
  79 /* Board Clock */
  80 #define CONFIG_SYS_CLK_FREQ     33333333
  81 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
  82 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
  83 #define CONFIG_SYS_TMU_CLK_DIV          4       /* 4 (default), 16, 64, 256 or 1024 */
  84
  85 /* PCMCIA */
  86 #define CONFIG_IDE_PCMCIA       1
  87 #define CONFIG_MARUBUN_PCCARD   1
  88 #define CONFIG_PCMCIA_SLOT_A    1
  89 #define CONFIG_SYS_IDE_MAXDEVICE        1
  90 #define CONFIG_SYS_MARUBUN_MRSHPC       0xb83fffe0
  91 #define CONFIG_SYS_MARUBUN_MW1          0xb8400000
  92 #define CONFIG_SYS_MARUBUN_MW2          0xb8500000
  93 #define CONFIG_SYS_MARUBUN_IO           0xb8600000
  94
  95 #define CONFIG_SYS_PIO_MODE             1
  96 #define CONFIG_SYS_IDE_MAXBUS           1
  97 #define CONFIG_DOS_PARTITION    1
  98 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_MARUBUN_IO   /* base address */
  99 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x01F0          /* ide0 offste */
 100 #define CONFIG_SYS_ATA_DATA_OFFSET      0               /* data reg offset */
 101 #define CONFIG_SYS_ATA_REG_OFFSET       0               /* reg offset */
 102 #define CONFIG_SYS_ATA_ALT_OFFSET       0x200           /* alternate register offset */
 103 #define CONFIG_IDE_SWAP_IO
 104
 105 #endif  /* __MS7720SE_H */