include/configs/muas3001.h

   1 /*
   2  * (C) Copyright 2008
   3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * High Level Configuration Options
  29  * (easy to change)
  30  */
  31
  32 #define CONFIG_8260             1
  33 #define CONFIG_MPC8260          1
  34 #define CONFIG_MUAS3001         1
  35
  36 #define CONFIG_CPM2             1       /* Has a CPM2 */
  37
  38 /* Do boardspecific init */
  39 #define CONFIG_BOARD_EARLY_INIT_R       1
  40
  41 /* enable Watchdog */
  42 #define CONFIG_WATCHDOG         1
  43
  44 /*
  45  * Select serial console configuration
  46  *
  47  * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  48  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  49  * for SCC).
  50  */
  51 #define CONFIG_CONS_ON_SMC              /* Console is on SMC         */
  52 #undef  CONFIG_CONS_ON_SCC              /* It's not on SCC           */
  53 #undef  CONFIG_CONS_NONE                /* It's not on external UART */
  54 #if defined(CONFIG_MUAS_DEV_BOARD)
  55 #define CONFIG_CONS_INDEX       2       /* SMC2 is used for console  */
  56 #else
  57 #define CONFIG_CONS_INDEX       1       /* SMC1 is used for console  */
  58 #endif
  59
  60 /*
  61  * Select ethernet configuration
  62  *
  63  * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
  64  * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
  65  * SCC, 1-3 for FCC)
  66  *
  67  * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
  68  * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
  69  * must be unset.
  70  */
  71 #undef  CONFIG_ETHER_ON_SCC             /* Ethernet is not on SCC */
  72 #define CONFIG_ETHER_ON_FCC             /* Ethernet is on FCC     */
  73 #undef  CONFIG_ETHER_NONE               /* No external Ethernet   */
  74
  75 #define CONFIG_ETHER_INDEX      1
  76 #define CONFIG_ETHER_ON_FCC1
  77 #define FCC_ENET
  78
  79 /*
  80  * - Rx-CLK is CLK11
  81  * - Tx-CLK is CLK12
  82  */
  83 # define CFG_CMXFCR_VALUE       (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
  84 # define CFG_CMXFCR_MASK        (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
  85 /*
  86  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  87  */
  88 # define CFG_CPMFCR_RAMTYPE     (0)
  89 /* know on local Bus */
  90 /* define CFG_CPMFCR_RAMTYPE    (CPMFCR_DTB | CPMFCR_BDB) */
  91 /*
  92  * - Enable Full Duplex in FSMR
  93  */
  94 # define CFG_FCC_PSMR           (FCC_PSMR_FDE|FCC_PSMR_LPB)
  95
  96 #define CONFIG_MII                      /* MII PHY management           */
  97 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management  */
  98 # define CFG_PHY_ADDR           1
  99 /*
 100  * GPIO pins used for bit-banged MII communications
 101  */
 102 #define MDIO_PORT       0               /* Port A */
 103
 104 #define CFG_MDIO_PIN    0x00200000      /* PA10 */
 105 #define CFG_MDC_PIN     0x00400000      /* PA9  */
 106
 107 #define MDIO_ACTIVE     (iop->pdir |=  CFG_MDIO_PIN)
 108 #define MDIO_TRISTATE   (iop->pdir &= ~CFG_MDIO_PIN)
 109 #define MDIO_READ       ((iop->pdat &  CFG_MDIO_PIN) != 0)
 110
 111 #define MDIO(bit)       if(bit) iop->pdat |=  CFG_MDIO_PIN; \
 112                         else    iop->pdat &= ~CFG_MDIO_PIN
 113
 114 #define MDC(bit)        if(bit) iop->pdat |=  CFG_MDC_PIN; \
 115                         else    iop->pdat &= ~CFG_MDC_PIN
 116
 117 #define MIIDELAY        udelay(1)
 118
 119 #ifndef CONFIG_8260_CLKIN
 120 #define CONFIG_8260_CLKIN       66000000        /* in Hz */
 121 #endif
 122
 123 #define CONFIG_BAUDRATE         115200
 124
 125 /*
 126  * Command line configuration.
 127  */
 128 #include <config_cmd_default.h>
 129
 130 #define CONFIG_CMD_DTT
 131 #define CONFIG_CMD_ECHO
 132 #define CONFIG_CMD_IMMAP
 133 #define CONFIG_CMD_MII
 134 #define CONFIG_CMD_PING
 135 #define CONFIG_CMD_I2C
 136
 137 /*
 138  * Default environment settings
 139  */
 140 #define CONFIG_EXTRA_ENV_SETTINGS                                               \
 141         "netdev=eth0\0"                                                         \
 142         "u-boot_addr_r=100000\0"                                                \
 143         "kernel_addr_r=200000\0"                                                \
 144         "fdt_addr_r=400000\0"                                                   \
 145         "rootpath=/opt/eldk/ppc_6xx\0"                                          \
 146         "u-boot=muas3001/u-boot.bin\0"                                          \
 147         "bootfile=muas3001/uImage\0"                                            \
 148         "fdt_file=muas3001/muas3001.dtb\0"                                      \
 149         "ramdisk_file=uRamdisk\0"                                               \
 150         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                                \
 151         "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; "            \
 152                 "cp.b ${u-boot_addr_r} ff000000 ${filesize};"                   \
 153                 "prot on ff000000 ff03ffff\0"                                   \
 154         "ramargs=setenv bootargs root=/dev/ram rw\0"                            \
 155         "nfsargs=setenv bootargs root=/dev/nfs rw "                             \
 156                 "nfsroot=${serverip}:${rootpath}\0"                             \
 157         "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0"     \
 158         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"                      \
 159         "addip=setenv bootargs ${bootargs} "                                    \
 160                 "ip=${ipaddr}:${serverip}:${gatewayip}:"                        \
 161                 "${netmask}:${hostname}:${netdev}:off panic=1\0"                \
 162         "net_nfs=tftp ${kernel_addr_r} ${bootfile}; "                           \
 163                 "tftp ${fdt_addr_r} ${fdt_file}; run nfsargs addip addcons;"    \
 164                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"                      \
 165         "net_self=tftp ${kernel_addr_r} ${bootfile}; "                          \
 166                 "tftp ${fdt_addr_r} ${fdt_file}; "                              \
 167                 "tftp ${ramdisk_addr} ${ramdisk_file}; "                        \
 168                 "run ramargs addip; "                                           \
 169                 "bootm ${kernel_addr_r} ${ramdisk_addr} ${fdt_addr_r}\0"        \
 170         "ramdisk_addr=ff210000\0"                                               \
 171         "kernel_addr=ff050000\0"                                                \
 172         "fdt_addr=ff200000\0"                                                   \
 173         "flash_self=run ramargs addip addcons;bootm ${kernel_addr}"             \
 174         " ${ramdisk_addr} ${fdt_addr}\0"                                        \
 175         "updateramdisk=era ${ramdisk_addr} +1f0000;tftpb ${kernel_addr_r}"      \
 176         " ${ramdisk_file};"                                                     \
 177         "cp.b ${kernel_addr_r} ${ramdisk_addr} ${filesize}\0"                   \
 178         "updatekernel=era ${kernel_addr} +1b0000;tftpb ${kernel_addr_r}"        \
 179         " ${bootfile};"                                                         \
 180         "cp.b ${kernel_addr_r} ${kernel_addr} ${filesize}\0"                    \
 181         "updatefdt=era ${fdt_addr} +10000;tftpb ${fdt_addr_r} ${fdt_file};"     \
 182         "cp.b ${fdt_addr_r} ${fdt_addr} ${filesize}\0"                          \
 183         ""
 184
 185 #define CONFIG_BOOTCOMMAND      "run net_nfs"
 186 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 187
 188 /*
 189  * Miscellaneous configurable options
 190  */
 191 #define CFG_HUSH_PARSER
 192 #define CFG_PROMPT_HUSH_PS2     "> "
 193 #define CFG_LONGHELP                    /* undef to save memory     */
 194 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt   */
 195 #if defined(CONFIG_CMD_KGDB)
 196 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size  */
 197 #else
 198 #define CFG_CBSIZE              256     /* Console I/O Buffer Size  */
 199 #endif
 200 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size  */
 201 #define CFG_MAXARGS             16              /* max number of command args */
 202 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size  */
 203
 204 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 205 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM  */
 206
 207 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 208
 209 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 210
 211 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
 212
 213 #define CFG_SDRAM_BASE          0x00000000
 214 #define CFG_FLASH_BASE          0xFF000000
 215 #define CFG_FLASH_SIZE          32
 216 #define CFG_FLASH_CFI
 217 #define CONFIG_FLASH_CFI_DRIVER
 218 #define CFG_MAX_FLASH_BANKS     1       /* max num of flash banks       */
 219 #define CFG_MAX_FLASH_SECT      512     /* max num of sects on one chip */
 220
 221 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
 222
 223 #define CFG_MONITOR_BASE        TEXT_BASE
 224 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 225 #define CFG_RAMBOOT
 226 #endif
 227
 228 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256KB for Monitor */
 229
 230 #define CONFIG_ENV_IS_IN_FLASH
 231
 232 #ifdef CONFIG_ENV_IS_IN_FLASH
 233 #define CONFIG_ENV_SECT_SIZE    0x10000
 234 #define CONFIG_ENV_ADDR         (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 235 #endif /* CONFIG_ENV_IS_IN_FLASH */
 236
 237 /*
 238  * I2C Bus
 239  */
 240 #define CONFIG_HARD_I2C         1       /* To enable I2C support        */
 241 #define CFG_I2C_SPEED           100000  /* I2C speed and slave address  */
 242 #define CFG_I2C_SLAVE           0x7F
 243
 244 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 245 #define CFG_EEPROM_PAGE_WRITE_BITS 3
 246 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 247 #define CONFIG_DTT_LM75         1       /* ON Semi's LM75               */
 248 #define CONFIG_DTT_SENSORS      {0}     /* Sensor addresses             */
 249 #define CFG_DTT_MAX_TEMP        70
 250 #define CFG_DTT_LOW_TEMP        -30
 251 #define CFG_DTT_HYSTERESIS      3
 252
 253 #define CFG_IMMR                0xF0000000
 254 #define CFG_DEFAULT_IMMR        0x0F010000
 255
 256 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 257 #define CFG_INIT_RAM_END        0x2000  /* End of used area in DPRAM    */
 258 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 259 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 260 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 261
 262 /* Hard reset configuration word */
 263 #define CFG_HRCW_MASTER         0x0E028200      /* BPS=11 CIP=1 ISB=010 BMS=1 */
 264
 265 /* No slaves */
 266 #define CFG_HRCW_SLAVE1         0
 267 #define CFG_HRCW_SLAVE2         0
 268 #define CFG_HRCW_SLAVE3         0
 269 #define CFG_HRCW_SLAVE4         0
 270 #define CFG_HRCW_SLAVE5         0
 271 #define CFG_HRCW_SLAVE6         0
 272 #define CFG_HRCW_SLAVE7         0
 273
 274 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
 275 #define BOOTFLAG_WARM           0x02    /* Software reboot                  */
 276
 277 #define CFG_MALLOC_LEN          (4096 << 10)    /* Reserve 4 MB for malloc()    */
 278 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 279
 280 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPUs */
 281 #if defined(CONFIG_CMD_KGDB)
 282 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
 283 #endif
 284
 285 #define CFG_HID0_INIT           0
 286 #define CFG_HID0_FINAL          (HID0_ICE | HID0_IFEM | HID0_ABE)
 287
 288 #define CFG_HID2                0
 289
 290 #define CFG_SIUMCR              0x00200000
 291 #define CFG_BCR                 0x004c0000
 292 #define CFG_SCCR                0x0
 293
 294 /*-----------------------------------------------------------------------
 295  * SYPCR - System Protection Control                             4-35
 296  * SYPCR can only be written once after reset!
 297  *-----------------------------------------------------------------------
 298  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 299  */
 300 #if defined(CONFIG_WATCHDOG)
 301 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 302                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 303 #else
 304 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 305                          SYPCR_SWRI|SYPCR_SWP)
 306 #endif /* CONFIG_WATCHDOG */
 307
 308 /*-----------------------------------------------------------------------
 309  * RMR - Reset Mode Register                                     5-5
 310  *-----------------------------------------------------------------------
 311  * turn on Checkstop Reset Enable
 312  */
 313 #define CFG_RMR         0
 314
 315 /*-----------------------------------------------------------------------
 316  * TMCNTSC - Time Counter Status and Control                     4-40
 317  *-----------------------------------------------------------------------
 318  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 319  * and enable Time Counter
 320  */
 321 #define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 322
 323 /*-----------------------------------------------------------------------
 324  * PISCR - Periodic Interrupt Status and Control                 4-42
 325  *-----------------------------------------------------------------------
 326  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 327  * Periodic timer
 328  */
 329 #define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 330
 331 /*-----------------------------------------------------------------------
 332  * RCCR - RISC Controller Configuration                         13-7
 333  *-----------------------------------------------------------------------
 334  */
 335 #define CFG_RCCR        0
 336
 337 /*
 338  * Init Memory Controller:
 339  *
 340  * Bank Bus     Machine PortSz  Device
 341  * ---- ---     ------- ------  ------
 342  *  0   60x     GPCM    32 bit  FLASH
 343  *  1   60x     SDRAM   64 bit  SDRAM
 344  *  4   60x     GPCM    16 bit  I/O Ctrl
 345  *
 346  */
 347 /* Bank 0 - FLASH
 348  */
 349 #define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
 350                          BRx_PS_32                      |\
 351                          BRx_MS_GPCM_P                  |\
 352                          BRx_V)
 353
 354 #define CFG_OR0_PRELIM (0xff000020)
 355
 356 /* Bank 1 - 60x bus SDRAM
 357  */
 358 #define CFG_GLOBAL_SDRAM_LIMIT  (256 << 20)     /* less than 256 MB */
 359
 360 #define CFG_MPTPR       0x2800
 361
 362 /*-----------------------------------------------------------------------------
 363  * Address for Mode Register Set (MRS) command
 364  *-----------------------------------------------------------------------------
 365  */
 366 #define CFG_MRS_OFFS    0x00000110
 367 #define CFG_PSRT        0x13
 368
 369 #define CFG_BR1_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
 370                          BRx_PS_64                      |\
 371                          BRx_MS_SDRAM_P                 |\
 372                          BRx_V)
 373
 374 #define CFG_OR1_PRELIM  CFG_OR1_LITTLE
 375
 376 /* SDRAM initialization values
 377 */
 378 #define CFG_OR1_LITTLE  ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 379                          ORxS_BPD_4                     |\
 380                          ORxS_ROWST_PBI1_A7             |\
 381                          ORxS_NUMR_12)
 382
 383 #define CFG_PSDMR_LITTLE        0x004b36a3
 384
 385 #define CFG_OR1_BIG     ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 386                          ORxS_BPD_4                     |\
 387                          ORxS_ROWST_PBI1_A4             |\
 388                          ORxS_NUMR_12)
 389
 390 #define CFG_PSDMR_BIG           0x014f36a3
 391
 392 /* IO on CS4 initialization values
 393 */
 394 #define CFG_IO_BASE     0xc0000000
 395 #define CFG_IO_SIZE     1
 396
 397 #define CFG_BR4_PRELIM  ((CFG_IO_BASE & BRx_BA_MSK) |\
 398                          BRx_PS_16 | BRx_MS_GPCM_L | BRx_V)
 399
 400 #define CFG_OR4_PRELIM  (0xfff80020)
 401
 402 #define CFG_RESET_ADDRESS 0xFDFFFFFC    /* "bad" address                */
 403
 404 /* pass open firmware flat tree */
 405 #define CONFIG_OF_LIBFDT        1
 406 #define CONFIG_OF_BOARD_SETUP   1
 407
 408 #define OF_CPU                  "PowerPC,8270@0"
 409 #define OF_SOC                  "soc@f0000000"
 410 #define OF_TBCLK                (bd->bi_busfreq / 4)
 411 #if defined(CONFIG_MUAS_DEV_BOARD)
 412 #define OF_STDOUT_PATH          "/soc/cpm/serial@11a90"
 413 #else
 414 #define OF_STDOUT_PATH          "/soc/cpm/serial@11a80"
 415 #endif
 416
 417 #endif /* __CONFIG_H */