include/configs/muas3001.h

   1 /*
   2  * (C) Copyright 2008
   3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * High Level Configuration Options
  29  * (easy to change)
  30  */
  31
  32 #define CONFIG_8260             1
  33 #define CONFIG_MPC8260          1
  34 #define CONFIG_MUAS3001         1
  35
  36 #define CONFIG_SYS_TEXT_BASE    0xFF000000
  37
  38 #define CONFIG_CPM2             1       /* Has a CPM2 */
  39
  40 /* Do boardspecific init */
  41 #define CONFIG_BOARD_EARLY_INIT_R       1
  42
  43 /* enable Watchdog */
  44 #define CONFIG_WATCHDOG         1
  45
  46 /*
  47  * Select serial console configuration
  48  *
  49  * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  50  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  51  * for SCC).
  52  */
  53 #define CONFIG_CONS_ON_SMC              /* Console is on SMC         */
  54 #undef  CONFIG_CONS_ON_SCC              /* It's not on SCC           */
  55 #undef  CONFIG_CONS_NONE                /* It's not on external UART */
  56 #if defined(CONFIG_MUAS_DEV_BOARD)
  57 #define CONFIG_CONS_INDEX       2       /* SMC2 is used for console  */
  58 #else
  59 #define CONFIG_CONS_INDEX       1       /* SMC1 is used for console  */
  60 #endif
  61
  62 /*
  63  * Select ethernet configuration
  64  *
  65  * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
  66  * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
  67  * SCC, 1-3 for FCC)
  68  *
  69  * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
  70  * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
  71  * must be unset.
  72  */
  73 #undef  CONFIG_ETHER_ON_SCC             /* Ethernet is not on SCC */
  74 #define CONFIG_ETHER_ON_FCC             /* Ethernet is on FCC     */
  75 #undef  CONFIG_ETHER_NONE               /* No external Ethernet   */
  76
  77 #define CONFIG_ETHER_INDEX      1
  78 #define CONFIG_ETHER_ON_FCC1
  79 #define CONFIG_HAS_ETH0
  80 #define FCC_ENET
  81
  82 /*
  83  * - Rx-CLK is CLK11
  84  * - Tx-CLK is CLK12
  85  */
  86 # define CONFIG_SYS_CMXFCR_VALUE        (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
  87 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
  88 /*
  89  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  90  */
  91 # define CONFIG_SYS_CPMFCR_RAMTYPE      (0)
  92 /* know on local Bus */
  93 /* define CONFIG_SYS_CPMFCR_RAMTYPE     (CPMFCR_DTB | CPMFCR_BDB) */
  94 /*
  95  * - Enable Full Duplex in FSMR
  96  */
  97 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
  98
  99 #define CONFIG_MII                      /* MII PHY management           */
 100 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management  */
 101 # define CONFIG_SYS_PHY_ADDR            1
 102 /*
 103  * GPIO pins used for bit-banged MII communications
 104  */
 105 #define MDIO_PORT       0               /* Port A */
 106 #define MDIO_DECLARE    volatile ioport_t *iop = ioport_addr ( \
 107                                 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
 108 #define MDC_DECLARE     MDIO_DECLARE
 109
 110
 111 #define CONFIG_SYS_MDIO_PIN     0x00200000      /* PA10 */
 112 #define CONFIG_SYS_MDC_PIN      0x00400000      /* PA9  */
 113
 114 #define MDIO_ACTIVE     (iop->pdir |=  CONFIG_SYS_MDIO_PIN)
 115 #define MDIO_TRISTATE   (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
 116 #define MDIO_READ       ((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
 117
 118 #define MDIO(bit)       if(bit) iop->pdat |=  CONFIG_SYS_MDIO_PIN; \
 119                         else    iop->pdat &= ~CONFIG_SYS_MDIO_PIN
 120
 121 #define MDC(bit)        if(bit) iop->pdat |=  CONFIG_SYS_MDC_PIN; \
 122                         else    iop->pdat &= ~CONFIG_SYS_MDC_PIN
 123
 124 #define MIIDELAY        udelay(1)
 125
 126 #ifndef CONFIG_8260_CLKIN
 127 #define CONFIG_8260_CLKIN       66000000        /* in Hz */
 128 #endif
 129
 130 #define CONFIG_BAUDRATE         115200
 131
 132 /*
 133  * Command line configuration.
 134  */
 135 #include <config_cmd_default.h>
 136
 137 #define CONFIG_CMD_DTT
 138 #define CONFIG_CMD_ECHO
 139 #define CONFIG_CMD_IMMAP
 140 #define CONFIG_CMD_MII
 141 #define CONFIG_CMD_PING
 142 #define CONFIG_CMD_I2C
 143
 144 /*
 145  * Default environment settings
 146  */
 147 #define CONFIG_EXTRA_ENV_SETTINGS                                               \
 148         "netdev=eth0\0"                                                         \
 149         "u-boot_addr_r=100000\0"                                                \
 150         "kernel_addr_r=200000\0"                                                \
 151         "fdt_addr_r=400000\0"                                                   \
 152         "rootpath=/opt/eldk/ppc_6xx\0"                                          \
 153         "u-boot=muas3001/u-boot.bin\0"                                          \
 154         "bootfile=muas3001/uImage\0"                                            \
 155         "fdt_file=muas3001/muas3001.dtb\0"                                      \
 156         "ramdisk_file=uRamdisk\0"                                               \
 157         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                                \
 158         "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; "            \
 159                 "cp.b ${u-boot_addr_r} ff000000 ${filesize};"                   \
 160                 "prot on ff000000 ff03ffff\0"                                   \
 161         "ramargs=setenv bootargs root=/dev/ram rw\0"                            \
 162         "nfsargs=setenv bootargs root=/dev/nfs rw "                             \
 163                 "nfsroot=${serverip}:${rootpath}\0"                             \
 164         "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0"     \
 165         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"                      \
 166         "addip=setenv bootargs ${bootargs} "                                    \
 167                 "ip=${ipaddr}:${serverip}:${gatewayip}:"                        \
 168                 "${netmask}:${hostname}:${netdev}:off panic=1\0"                \
 169         "net_nfs=tftp ${kernel_addr_r} ${bootfile}; "                           \
 170                 "tftp ${fdt_addr_r} ${fdt_file}; run nfsargs addip addcons;"    \
 171                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"                      \
 172         "net_self=tftp ${kernel_addr_r} ${bootfile}; "                          \
 173                 "tftp ${fdt_addr_r} ${fdt_file}; "                              \
 174                 "tftp ${ramdisk_addr} ${ramdisk_file}; "                        \
 175                 "run ramargs addip; "                                           \
 176                 "bootm ${kernel_addr_r} ${ramdisk_addr} ${fdt_addr_r}\0"        \
 177         "ramdisk_addr=ff210000\0"                                               \
 178         "kernel_addr=ff050000\0"                                                \
 179         "fdt_addr=ff200000\0"                                                   \
 180         "flash_self=run ramargs addip addcons;bootm ${kernel_addr}"             \
 181         " ${ramdisk_addr} ${fdt_addr}\0"                                        \
 182         "updateramdisk=era ${ramdisk_addr} +1f0000;tftpb ${kernel_addr_r}"      \
 183         " ${ramdisk_file};"                                                     \
 184         "cp.b ${kernel_addr_r} ${ramdisk_addr} ${filesize}\0"                   \
 185         "updatekernel=era ${kernel_addr} +1b0000;tftpb ${kernel_addr_r}"        \
 186         " ${bootfile};"                                                         \
 187         "cp.b ${kernel_addr_r} ${kernel_addr} ${filesize}\0"                    \
 188         "updatefdt=era ${fdt_addr} +10000;tftpb ${fdt_addr_r} ${fdt_file};"     \
 189         "cp.b ${fdt_addr_r} ${fdt_addr} ${filesize}\0"                          \
 190         ""
 191
 192 #define CONFIG_BOOTCOMMAND      "run net_nfs"
 193 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 194
 195 /*
 196  * Miscellaneous configurable options
 197  */
 198 #define CONFIG_SYS_HUSH_PARSER
 199 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 200 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 201 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt   */
 202 #if defined(CONFIG_CMD_KGDB)
 203 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 204 #else
 205 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 206 #endif
 207 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size  */
 208 #define CONFIG_SYS_MAXARGS              16              /* max number of command args */
 209 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size  */
 210
 211 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 212 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 213
 214 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 215
 216 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 217
 218 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
 219
 220 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 221 #define CONFIG_SYS_FLASH_BASE           0xFF000000
 222 #define CONFIG_SYS_FLASH_SIZE           32
 223 #define CONFIG_SYS_FLASH_CFI
 224 #define CONFIG_FLASH_CFI_DRIVER
 225 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of flash banks       */
 226 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sects on one chip */
 227
 228 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 229
 230 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 231 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 232 #define CONFIG_SYS_RAMBOOT
 233 #endif
 234
 235 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256KB for Monitor */
 236
 237 #define CONFIG_ENV_IS_IN_FLASH
 238
 239 #ifdef CONFIG_ENV_IS_IN_FLASH
 240 #define CONFIG_ENV_SECT_SIZE    0x10000
 241 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 242 #endif /* CONFIG_ENV_IS_IN_FLASH */
 243
 244 /*
 245  * I2C Bus
 246  */
 247 #define CONFIG_HARD_I2C         1       /* To enable I2C support        */
 248 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address  */
 249 #define CONFIG_SYS_I2C_SLAVE            0x7F
 250
 251 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 252 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 253 #define CONFIG_DTT_LM75         1       /* ON Semi's LM75               */
 254 #define CONFIG_DTT_SENSORS      {0}     /* Sensor addresses             */
 255 #define CONFIG_SYS_DTT_MAX_TEMP 70
 256 #define CONFIG_SYS_DTT_LOW_TEMP -30
 257 #define CONFIG_SYS_DTT_HYSTERESIS       3
 258
 259 #define CONFIG_SYS_IMMR         0xF0000000
 260 #define CONFIG_SYS_DEFAULT_IMMR 0x0F010000
 261
 262 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 263 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000  /* Size of used area in DPRAM   */
 264 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* size in bytes reserved for initial data */
 265 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
 266 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 267
 268 /* Hard reset configuration word */
 269 #define CONFIG_SYS_HRCW_MASTER          0x0E028200      /* BPS=11 CIP=1 ISB=010 BMS=1 */
 270
 271 /* No slaves */
 272 #define CONFIG_SYS_HRCW_SLAVE1  0
 273 #define CONFIG_SYS_HRCW_SLAVE2  0
 274 #define CONFIG_SYS_HRCW_SLAVE3  0
 275 #define CONFIG_SYS_HRCW_SLAVE4  0
 276 #define CONFIG_SYS_HRCW_SLAVE5  0
 277 #define CONFIG_SYS_HRCW_SLAVE6  0
 278 #define CONFIG_SYS_HRCW_SLAVE7  0
 279
 280 #define CONFIG_SYS_MALLOC_LEN           (4096 << 10)    /* Reserve 4 MB for malloc()    */
 281 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 282
 283 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPUs */
 284 #if defined(CONFIG_CMD_KGDB)
 285 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 286 #endif
 287
 288 #define CONFIG_SYS_HID0_INIT            0
 289 #define CONFIG_SYS_HID0_FINAL           (HID0_ICE | HID0_IFEM | HID0_ABE)
 290
 291 #define CONFIG_SYS_HID2         0
 292
 293 #define CONFIG_SYS_SIUMCR               0x00200000
 294 #define CONFIG_SYS_BCR                  0x004c0000
 295 #define CONFIG_SYS_SCCR         0x0
 296
 297 /*-----------------------------------------------------------------------
 298  * SYPCR - System Protection Control                             4-35
 299  * SYPCR can only be written once after reset!
 300  *-----------------------------------------------------------------------
 301  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 302  */
 303 #if defined(CONFIG_WATCHDOG)
 304 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 305                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 306 #else
 307 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 308                          SYPCR_SWRI|SYPCR_SWP)
 309 #endif /* CONFIG_WATCHDOG */
 310
 311 /*-----------------------------------------------------------------------
 312  * RMR - Reset Mode Register                                     5-5
 313  *-----------------------------------------------------------------------
 314  * turn on Checkstop Reset Enable
 315  */
 316 #define CONFIG_SYS_RMR         0
 317
 318 /*-----------------------------------------------------------------------
 319  * TMCNTSC - Time Counter Status and Control                     4-40
 320  *-----------------------------------------------------------------------
 321  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 322  * and enable Time Counter
 323  */
 324 #define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 325
 326 /*-----------------------------------------------------------------------
 327  * PISCR - Periodic Interrupt Status and Control                 4-42
 328  *-----------------------------------------------------------------------
 329  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 330  * Periodic timer
 331  */
 332 #define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 333
 334 /*-----------------------------------------------------------------------
 335  * RCCR - RISC Controller Configuration                         13-7
 336  *-----------------------------------------------------------------------
 337  */
 338 #define CONFIG_SYS_RCCR        0
 339
 340 /*
 341  * Init Memory Controller:
 342  *
 343  * Bank Bus     Machine PortSz  Device
 344  * ---- ---     ------- ------  ------
 345  *  0   60x     GPCM    32 bit  FLASH
 346  *  1   60x     SDRAM   64 bit  SDRAM
 347  *  4   60x     GPCM    16 bit  I/O Ctrl
 348  *
 349  */
 350 /* Bank 0 - FLASH
 351  */
 352 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)    |\
 353                          BRx_PS_32                      |\
 354                          BRx_MS_GPCM_P                  |\
 355                          BRx_V)
 356
 357 #define CONFIG_SYS_OR0_PRELIM (0xff000020)
 358
 359 /* Bank 1 - 60x bus SDRAM
 360  */
 361 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT   (256 << 20)     /* less than 256 MB */
 362
 363 #define CONFIG_SYS_MPTPR       0x2800
 364
 365 /*-----------------------------------------------------------------------------
 366  * Address for Mode Register Set (MRS) command
 367  *-----------------------------------------------------------------------------
 368  */
 369 #define CONFIG_SYS_MRS_OFFS     0x00000110
 370 #define CONFIG_SYS_PSRT        0x13
 371
 372 #define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
 373                          BRx_PS_64                      |\
 374                          BRx_MS_SDRAM_P                 |\
 375                          BRx_V)
 376
 377 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR1_LITTLE
 378
 379 /* SDRAM initialization values
 380 */
 381 #define CONFIG_SYS_OR1_LITTLE   ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 382                          ORxS_BPD_4                     |\
 383                          ORxS_ROWST_PBI1_A7             |\
 384                          ORxS_NUMR_12)
 385
 386 #define CONFIG_SYS_PSDMR_LITTLE 0x004b36a3
 387
 388 #define CONFIG_SYS_OR1_BIG      ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 389                          ORxS_BPD_4                     |\
 390                          ORxS_ROWST_PBI1_A4             |\
 391                          ORxS_NUMR_12)
 392
 393 #define CONFIG_SYS_PSDMR_BIG            0x014f36a3
 394
 395 /* IO on CS4 initialization values
 396 */
 397 #define CONFIG_SYS_IO_BASE      0xc0000000
 398 #define CONFIG_SYS_IO_SIZE      1
 399
 400 #define CONFIG_SYS_BR4_PRELIM   ((CONFIG_SYS_IO_BASE & BRx_BA_MSK) |\
 401                          BRx_PS_16 | BRx_MS_GPCM_L | BRx_V)
 402
 403 #define CONFIG_SYS_OR4_PRELIM   (0xfff80020)
 404
 405 #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC     /* "bad" address                */
 406
 407 /* pass open firmware flat tree */
 408 #define CONFIG_OF_LIBFDT        1
 409 #define CONFIG_OF_BOARD_SETUP   1
 410
 411 #define OF_TBCLK                (bd->bi_busfreq / 4)
 412 #if defined(CONFIG_MUAS_DEV_BOARD)
 413 #define OF_STDOUT_PATH          "/soc/cpm/serial@11a90"
 414 #else
 415 #define OF_STDOUT_PATH          "/soc/cpm/serial@11a80"
 416 #endif
 417
 418 #endif /* __CONFIG_H */