include/configs/mx31pdk.h

   1 /*
   2  * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
   3  *
   4  * (C) Copyright 2004
   5  * Texas Instruments.
   6  * Richard Woodruff <r-woodruff2@ti.com>
   7  * Kshitij Gupta <kshitij@ti.com>
   8  *
   9  * Configuration settings for the Freescale i.MX31 PDK board.
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 #include <asm/arch/imx-regs.h>
  34
  35 /* High Level Configuration Options */
  36 #define CONFIG_ARM1136                  /* This is an arm1136 CPU core */
  37 #define CONFIG_MX31                     /* in a mx31 */
  38
  39 #define CONFIG_DISPLAY_CPUINFO
  40 #define CONFIG_DISPLAY_BOARDINFO
  41
  42 #define CONFIG_CMDLINE_TAG                      /* enable passing of ATAGs */
  43 #define CONFIG_SETUP_MEMORY_TAGS
  44 #define CONFIG_INITRD_TAG
  45
  46 #define CONFIG_MACH_TYPE        MACH_TYPE_MX31_3DS
  47
  48 #define CONFIG_SPL
  49 #define CONFIG_SPL_TARGET       "u-boot-with-spl.bin"
  50 #define CONFIG_SPL_LDSCRIPT     "arch/$(ARCH)/cpu/u-boot-spl.lds"
  51 #define CONFIG_SPL_MAX_SIZE     2048
  52 #define CONFIG_SPL_NAND_SUPPORT
  53
  54 #define CONFIG_SPL_TEXT_BASE    0x87dc0000
  55 #define CONFIG_SYS_TEXT_BASE    0x87e00000
  56
  57 #ifndef CONFIG_SPL_BUILD
  58 #define CONFIG_SKIP_LOWLEVEL_INIT
  59 #endif
  60
  61 /*
  62  * Size of malloc() pool
  63  */
  64 #define CONFIG_SYS_MALLOC_LEN           (2*CONFIG_ENV_SIZE + 2 * 128 * 1024)
  65
  66 /*
  67  * Hardware drivers
  68  */
  69
  70 #define CONFIG_MXC_UART
  71 #define CONFIG_MXC_UART_BASE    UART1_BASE
  72 #define CONFIG_MXC_GPIO
  73
  74 #define CONFIG_HARD_SPI
  75 #define CONFIG_MXC_SPI
  76 #define CONFIG_DEFAULT_SPI_BUS  1
  77 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
  78
  79 /* PMIC Controller */
  80 #define CONFIG_POWER
  81 #define CONFIG_POWER_SPI
  82 #define CONFIG_POWER_FSL
  83 #define CONFIG_FSL_PMIC_BUS     1
  84 #define CONFIG_FSL_PMIC_CS      2
  85 #define CONFIG_FSL_PMIC_CLK     1000000
  86 #define CONFIG_FSL_PMIC_MODE    (SPI_MODE_0 | SPI_CS_HIGH)
  87 #define CONFIG_FSL_PMIC_BITLEN  32
  88 #define CONFIG_RTC_MC13XXX
  89
  90 /* allow to overwrite serial and ethaddr */
  91 #define CONFIG_ENV_OVERWRITE
  92 #define CONFIG_CONS_INDEX               1
  93 #define CONFIG_BAUDRATE                 115200
  94
  95 /***********************************************************
  96  * Command definition
  97  ***********************************************************/
  98
  99 #include <config_cmd_default.h>
 100
 101 #define CONFIG_CMD_MII
 102 #define CONFIG_CMD_PING
 103 #define CONFIG_CMD_DHCP
 104 #define CONFIG_CMD_SPI
 105 #define CONFIG_CMD_DATE
 106 #define CONFIG_CMD_NAND
 107 #define CONFIG_CMD_BOOTZ
 108
 109 /*
 110  * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require
 111  * that CFG_NO_FLASH is undefined).
 112  */
 113 #undef CONFIG_CMD_IMLS
 114
 115 #define CONFIG_BOARD_LATE_INIT
 116
 117 #define CONFIG_BOOTDELAY        1
 118
 119 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 120         "bootargs_base=setenv bootargs console=ttymxc0,115200\0"        \
 121         "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs "       \
 122                 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"     \
 123         "bootcmd=run bootcmd_net\0"                                     \
 124         "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; "     \
 125                 "tftpboot 0x81000000 uImage-mx31; bootm\0"              \
 126         "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; "           \
 127                 "nand erase 0x0 0x40000; "                              \
 128                 "nand write 0x81000000 0x0 0x40000\0"
 129
 130 #define CONFIG_SMC911X
 131 #define CONFIG_SMC911X_BASE     0xB6000000
 132 #define CONFIG_SMC911X_32_BIT
 133
 134 /*
 135  * Miscellaneous configurable options
 136  */
 137 #define CONFIG_SYS_LONGHELP     /* undef to save memory */
 138 #define CONFIG_SYS_PROMPT       "MX31PDK U-Boot > "
 139 #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 140 /* Print Buffer Size */
 141 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + \
 142                                 sizeof(CONFIG_SYS_PROMPT)+16)
 143 /* max number of command args */
 144 #define CONFIG_SYS_MAXARGS      16
 145 /* Boot Argument Buffer Size */
 146 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 147
 148 /* memtest works on */
 149 #define CONFIG_SYS_MEMTEST_START        0x80000000
 150 #define CONFIG_SYS_MEMTEST_END          0x80010000
 151
 152 /* default load address */
 153 #define CONFIG_SYS_LOAD_ADDR            0x81000000
 154
 155 #define CONFIG_SYS_HZ                   1000
 156
 157 #define CONFIG_CMDLINE_EDITING
 158
 159 /*-----------------------------------------------------------------------
 160  * Physical Memory Map
 161  */
 162 #define CONFIG_NR_DRAM_BANKS    1
 163 #define PHYS_SDRAM_1            CSD0_BASE
 164 #define PHYS_SDRAM_1_SIZE       (128 * 1024 * 1024)
 165 #define CONFIG_BOARD_EARLY_INIT_F
 166
 167 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 168 #define CONFIG_SYS_INIT_RAM_ADDR        IRAM_BASE_ADDR
 169 #define CONFIG_SYS_INIT_RAM_SIZE        IRAM_SIZE
 170 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 171                                                 GENERATED_GBL_DATA_SIZE)
 172 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
 173                                                 CONFIG_SYS_INIT_RAM_SIZE)
 174
 175 /*-----------------------------------------------------------------------
 176  * FLASH and environment organization
 177  */
 178 /* No NOR flash present */
 179 #define CONFIG_SYS_NO_FLASH
 180
 181 #define CONFIG_ENV_IS_IN_NAND
 182 #define CONFIG_ENV_OFFSET               0x40000
 183 #define CONFIG_ENV_OFFSET_REDUND        0x60000
 184 #define CONFIG_ENV_SIZE                 (128 * 1024)
 185
 186 /*
 187  * NAND driver
 188  */
 189 #define CONFIG_NAND_MXC
 190 #define CONFIG_MXC_NAND_REGS_BASE      NFC_BASE_ADDR
 191 #define CONFIG_SYS_MAX_NAND_DEVICE     1
 192 #define CONFIG_SYS_NAND_BASE           NFC_BASE_ADDR
 193 #define CONFIG_MXC_NAND_HWECC
 194 #define CONFIG_SYS_NAND_LARGEPAGE
 195
 196 /* NAND configuration for the NAND_SPL */
 197
 198 /* Start copying real U-boot from the second page */
 199 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
 200 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x3f800
 201 /* Load U-Boot to this address */
 202 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
 203 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
 204
 205 #define CONFIG_SYS_NAND_PAGE_SIZE       0x800
 206 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 207 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 208 #define CONFIG_SYS_NAND_SIZE            (256 * 1024 * 1024)
 209 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 210
 211
 212 /* Configuration of lowlevel_init.S (clocks and SDRAM) */
 213 #define CCM_CCMR_SETUP          0x074B0BF5
 214 #define CCM_PDR0_SETUP_532MHZ   (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
 215                                  PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) |    \
 216                                  PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) |    \
 217                                  PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
 218 #define CCM_MPCTL_SETUP_532MHZ  (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) |  \
 219                                  PLL_MFN(12))
 220
 221 #define ESDMISC_MDDR_SETUP      0x00000004
 222 #define ESDMISC_MDDR_RESET_DL   0x0000000c
 223 #define ESDCFG0_MDDR_SETUP      0x006ac73a
 224
 225 #define ESDCTL_ROW_COL          (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
 226 #define ESDCTL_SETTINGS         (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
 227                                  ESDCTL_DSIZ(2) | ESDCTL_BL(1))
 228 #define ESDCTL_PRECHARGE        (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
 229 #define ESDCTL_AUTOREFRESH      (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
 230 #define ESDCTL_LOADMODEREG      (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
 231 #define ESDCTL_RW               ESDCTL_SETTINGS
 232
 233 #endif /* __CONFIG_H */