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driver/i2c/mxc: Enable I2C bus 3 and 4
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1 /*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 *
4 * Configuration settings for the MX53SMD Freescale board.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11
12 #define CONFIG_MX53
13
14 #define CONFIG_DISPLAY_CPUINFO
15 #define CONFIG_DISPLAY_BOARDINFO
16
17 #define CONFIG_MACH_TYPE MACH_TYPE_MX53_SMD
18
19 #include <asm/arch/imx-regs.h>
20
21 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
22 #define CONFIG_SETUP_MEMORY_TAGS
23 #define CONFIG_INITRD_TAG
24 #define CONFIG_REVISION_TAG
25
26 #define CONFIG_SYS_GENERIC_BOARD
27
28 /* Size of malloc() pool */
29 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
30
31 #define CONFIG_BOARD_EARLY_INIT_F
32 #define CONFIG_MXC_GPIO
33
34 #define CONFIG_MXC_UART
35 #define CONFIG_MXC_UART_BASE UART1_BASE
36
37 /* I2C Configs */
38 #define CONFIG_CMD_I2C
39 #define CONFIG_SYS_I2C
40 #define CONFIG_SYS_I2C_MXC
41 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
42
43 /* MMC Configs */
44 #define CONFIG_FSL_ESDHC
45 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
46 #define CONFIG_SYS_FSL_ESDHC_NUM 1
47
48 #define CONFIG_MMC
49 #define CONFIG_CMD_MMC
50 #define CONFIG_GENERIC_MMC
51 #define CONFIG_CMD_FAT
52 #define CONFIG_DOS_PARTITION
53
54 /* Eth Configs */
55 #define CONFIG_HAS_ETH1
56 #define CONFIG_MII
57
58 #define CONFIG_FEC_MXC
59 #define IMX_FEC_BASE FEC_BASE_ADDR
60 #define CONFIG_FEC_MXC_PHYADDR 0x1F
61
62 #define CONFIG_CMD_PING
63 #define CONFIG_CMD_DHCP
64 #define CONFIG_CMD_MII
65 #define CONFIG_CMD_NET
66
67 /* allow to overwrite serial and ethaddr */
68 #define CONFIG_ENV_OVERWRITE
69 #define CONFIG_CONS_INDEX 1
70 #define CONFIG_BAUDRATE 115200
71
72 /* Command definition */
73 #include <config_cmd_default.h>
74
75 #undef CONFIG_CMD_IMLS
76
77 #define CONFIG_BOOTDELAY 3
78
79 #define CONFIG_ETHPRIME "FEC0"
80
81 #define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
82 #define CONFIG_SYS_TEXT_BASE 0x77800000
83
84 #define CONFIG_EXTRA_ENV_SETTINGS \
85 "script=boot.scr\0" \
86 "uimage=uImage\0" \
87 "mmcdev=0\0" \
88 "mmcpart=2\0" \
89 "mmcroot=/dev/mmcblk0p3 rw\0" \
90 "mmcrootfstype=ext3 rootwait\0" \
91 "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
92 "root=${mmcroot} " \
93 "rootfstype=${mmcrootfstype}\0" \
94 "loadbootscript=" \
95 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
96 "bootscript=echo Running bootscript from mmc ...; " \
97 "source\0" \
98 "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
99 "mmcboot=echo Booting from mmc ...; " \
100 "run mmcargs; " \
101 "bootm\0" \
102 "netargs=setenv bootargs console=ttymxc0,${baudrate} " \
103 "root=/dev/nfs " \
104 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
105 "netboot=echo Booting from net ...; " \
106 "run netargs; " \
107 "dhcp ${uimage}; bootm\0" \
108
109 #define CONFIG_BOOTCOMMAND \
110 "mmc dev ${mmcdev}; if mmc rescan; then " \
111 "if run loadbootscript; then " \
112 "run bootscript; " \
113 "else " \
114 "if run loaduimage; then " \
115 "run mmcboot; " \
116 "else run netboot; " \
117 "fi; " \
118 "fi; " \
119 "else run netboot; fi"
120 #define CONFIG_ARP_TIMEOUT 200UL
121
122 /* Miscellaneous configurable options */
123 #define CONFIG_SYS_LONGHELP /* undef to save memory */
124 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
125 #define CONFIG_AUTO_COMPLETE
126 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
127
128 /* Print Buffer Size */
129 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
130 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
131 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
132
133 #define CONFIG_SYS_MEMTEST_START 0x70000000
134 #define CONFIG_SYS_MEMTEST_END 0x70010000
135
136 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
137
138 #define CONFIG_CMDLINE_EDITING
139
140 /* Physical Memory Map */
141 #define CONFIG_NR_DRAM_BANKS 2
142 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
143 #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
144 #define PHYS_SDRAM_2 CSD1_BASE_ADDR
145 #define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024)
146 #define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
147
148 #define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
149 #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
150 #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
151
152 #define CONFIG_SYS_INIT_SP_OFFSET \
153 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
154 #define CONFIG_SYS_INIT_SP_ADDR \
155 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
156
157 /* FLASH and environment organization */
158 #define CONFIG_SYS_NO_FLASH
159
160 #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
161 #define CONFIG_ENV_SIZE (8 * 1024)
162 #define CONFIG_ENV_IS_IN_MMC
163 #define CONFIG_SYS_MMC_ENV_DEV 0
164
165 #define CONFIG_OF_LIBFDT
166
167 #endif /* __CONFIG_H */