include/configs/mx6qsabreauto.h

   1 /*
   2  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   3  *
   4  * Configuration settings for the Freescale i.MX6Q SabreAuto board.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __MX6QSABREAUTO_CONFIG_H
  10 #define __MX6QSABREAUTO_CONFIG_H
  11
  12 #define CONFIG_MACH_TYPE        3529
  13 #define CONFIG_MXC_UART_BASE    UART4_BASE
  14 #define CONFIG_CONSOLE_DEV              "ttymxc3"
  15 #define CONFIG_MMCROOT                  "/dev/mmcblk0p2"
  16 #define PHYS_SDRAM_SIZE         (2u * 1024 * 1024 * 1024)
  17
  18 /* USB Configs */
  19 #define CONFIG_USB_EHCI
  20 #define CONFIG_USB_EHCI_MX6
  21 #define CONFIG_USB_STORAGE
  22 #define CONFIG_USB_HOST_ETHER
  23 #define CONFIG_USB_ETHER_ASIX
  24 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  25 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET        /* For OTG port */
  26 #define CONFIG_MXC_USB_PORTSC   (PORT_PTS_UTMI | PORT_PTS_PTW)
  27 #define CONFIG_MXC_USB_FLAGS    0
  28
  29 #define CONFIG_PCA953X
  30 #define CONFIG_SYS_I2C_PCA953X_WIDTH    { {0x30, 8}, {0x32, 8}, {0x34, 8} }
  31
  32 #include "mx6sabre_common.h"
  33
  34 #undef CONFIG_SYS_NO_FLASH
  35 #define CONFIG_SYS_FLASH_BASE           WEIM_ARB_BASE_ADDR
  36 #define CONFIG_SYS_FLASH_SECT_SIZE      (128 * 1024)
  37 #define CONFIG_SYS_MAX_FLASH_BANKS 1    /* max number of memory banks */
  38 #define CONFIG_SYS_MAX_FLASH_SECT 256   /* max number of sectors on one chip */
  39 #define CONFIG_SYS_FLASH_CFI            /* Flash memory is CFI compliant */
  40 #define CONFIG_FLASH_CFI_DRIVER         /* Use drivers/cfi_flash.c */
  41 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
  42 #define CONFIG_SYS_FLASH_EMPTY_INFO
  43
  44 #define CONFIG_SYS_FSL_USDHC_NUM        2
  45 #if defined(CONFIG_ENV_IS_IN_MMC)
  46 #define CONFIG_SYS_MMC_ENV_DEV          0
  47 #endif
  48
  49 /* I2C Configs */
  50 #define CONFIG_SYS_I2C
  51 #define CONFIG_SYS_I2C_MXC
  52 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
  53 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
  54 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
  55 #define CONFIG_SYS_I2C_SPEED            100000
  56
  57 /* NAND flash command */
  58 #define CONFIG_CMD_NAND
  59 #define CONFIG_CMD_NAND_TRIMFFS
  60
  61 /* NAND stuff */
  62 #define CONFIG_NAND_MXS
  63 #define CONFIG_SYS_MAX_NAND_DEVICE     1
  64 #define CONFIG_SYS_NAND_BASE           0x40000000
  65 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  66 #define CONFIG_SYS_NAND_ONFI_DETECTION
  67
  68 /* DMA stuff, needed for GPMI/MXS NAND support */
  69 #define CONFIG_APBH_DMA
  70 #define CONFIG_APBH_DMA_BURST
  71 #define CONFIG_APBH_DMA_BURST8
  72
  73 /* PMIC */
  74 #define CONFIG_POWER
  75 #define CONFIG_POWER_I2C
  76 #define CONFIG_POWER_PFUZE100
  77 #define CONFIG_POWER_PFUZE100_I2C_ADDR  0x08
  78
  79 #endif                         /* __MX6QSABREAUTO_CONFIG_H */