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1 /*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * Configuration settings for the Freescale i.MX6SX Sabreauto board.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11
12 #include "mx6_common.h"
13
14 /* Size of malloc() pool */
15 #define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
16
17 #define CONFIG_MXC_UART
18 #define CONFIG_MXC_UART_BASE UART1_BASE
19
20 #define CONFIG_EXTRA_ENV_SETTINGS \
21 "script=boot.scr\0" \
22 "image=zImage\0" \
23 "console=ttymxc0\0" \
24 "fdt_high=0xffffffff\0" \
25 "initrd_high=0xffffffff\0" \
26 "fdt_file=imx6sx-sabreauto.dtb\0" \
27 "fdt_addr=0x88000000\0" \
28 "boot_fdt=try\0" \
29 "ip_dyn=yes\0" \
30 "mmcdev=0\0" \
31 "mmcpart=1\0" \
32 "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
33 "mmcargs=setenv bootargs console=${console},${baudrate} " \
34 "root=${mmcroot}\0" \
35 "loadbootscript=" \
36 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
37 "bootscript=echo Running bootscript from mmc ...; " \
38 "source\0" \
39 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
40 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
41 "mmcboot=echo Booting from mmc ...; " \
42 "run mmcargs; " \
43 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
44 "if run loadfdt; then " \
45 "bootz ${loadaddr} - ${fdt_addr}; " \
46 "else " \
47 "if test ${boot_fdt} = try; then " \
48 "bootz; " \
49 "else " \
50 "echo WARN: Cannot load the DT; " \
51 "fi; " \
52 "fi; " \
53 "else " \
54 "bootz; " \
55 "fi;\0" \
56 "netargs=setenv bootargs console=${console},${baudrate} " \
57 "root=/dev/nfs " \
58 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
59 "netboot=echo Booting from net ...; " \
60 "run netargs; " \
61 "if test ${ip_dyn} = yes; then " \
62 "setenv get_cmd dhcp; " \
63 "else " \
64 "setenv get_cmd tftp; " \
65 "fi; " \
66 "${get_cmd} ${image}; " \
67 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
68 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
69 "bootz ${loadaddr} - ${fdt_addr}; " \
70 "else " \
71 "if test ${boot_fdt} = try; then " \
72 "bootz; " \
73 "else " \
74 "echo WARN: Cannot load the DT; " \
75 "fi; " \
76 "fi; " \
77 "else " \
78 "bootz; " \
79 "fi;\0"
80
81 #define CONFIG_BOOTCOMMAND \
82 "mmc dev ${mmcdev};" \
83 "mmc dev ${mmcdev}; if mmc rescan; then " \
84 "if run loadbootscript; then " \
85 "run bootscript; " \
86 "else " \
87 "if run loadimage; then " \
88 "run mmcboot; " \
89 "else run netboot; " \
90 "fi; " \
91 "fi; " \
92 "else run netboot; fi"
93
94 /* Miscellaneous configurable options */
95 #define CONFIG_SYS_MEMTEST_START 0x80000000
96 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
97
98 /* Physical Memory Map */
99 #define CONFIG_NR_DRAM_BANKS 1
100 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
101
102 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
103 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
104 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
105
106 #define CONFIG_SYS_INIT_SP_OFFSET \
107 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
108 #define CONFIG_SYS_INIT_SP_ADDR \
109 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
110
111 /* MMC Configuration */
112 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
113
114 /* I2C Configs */
115 #define CONFIG_SYS_I2C_MXC
116 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
117 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
118 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
119 #define CONFIG_SYS_I2C_SPEED 100000
120
121 /* NAND flash command */
122 #define CONFIG_CMD_NAND
123 #define CONFIG_CMD_NAND_TRIMFFS
124
125 /* NAND stuff */
126 #define CONFIG_NAND_MXS
127 #define CONFIG_SYS_MAX_NAND_DEVICE 1
128 #define CONFIG_SYS_NAND_BASE 0x40000000
129 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
130 #define CONFIG_SYS_NAND_ONFI_DETECTION
131
132 /* DMA stuff, needed for GPMI/MXS NAND support */
133 #define CONFIG_APBH_DMA
134 #define CONFIG_APBH_DMA_BURST
135 #define CONFIG_APBH_DMA_BURST8
136
137 /* Network */
138
139 #define CONFIG_FEC_MXC
140 #define CONFIG_MII
141
142 #define IMX_FEC_BASE ENET2_BASE_ADDR
143 #define CONFIG_FEC_MXC_PHYADDR 0x0
144
145 #define CONFIG_FEC_XCV_TYPE RGMII
146 #define CONFIG_ETHPRIME "FEC"
147
148 #define CONFIG_PHYLIB
149 #define CONFIG_PHY_ATHEROS
150
151 #ifdef CONFIG_CMD_USB
152 #define CONFIG_USB_EHCI_MX6
153 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
154 #define CONFIG_USB_HOST_ETHER
155 #define CONFIG_USB_ETHER_ASIX
156 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
157 #define CONFIG_MXC_USB_FLAGS 0
158 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
159 #endif
160
161 #define CONFIG_IMX_THERMAL
162
163 #ifdef CONFIG_FSL_QSPI
164 #define CONFIG_SYS_FSL_QSPI_AHB
165 #define CONFIG_SF_DEFAULT_BUS 0
166 #define CONFIG_SF_DEFAULT_CS 0
167 #define CONFIG_SF_DEFAULT_SPEED 40000000
168 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
169 #define FSL_QSPI_FLASH_SIZE SZ_32M
170 #define FSL_QSPI_FLASH_NUM 2
171 #endif
172
173 #define CONFIG_ENV_OFFSET (8 * SZ_64K)
174 #define CONFIG_ENV_SIZE SZ_8K
175 #define CONFIG_ENV_IS_IN_MMC
176
177 #define CONFIG_SYS_FSL_USDHC_NUM 2
178 #if defined(CONFIG_ENV_IS_IN_MMC)
179 #define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC3*/
180 #endif
181
182 #endif /* __CONFIG_H */