include/configs/neo.h

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #define CONFIG_405EP            1       /* this is a PPC405 CPU */
  12 #define CONFIG_NEO              1       /*  on a Neo board */
  13
  14 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  15
  16 /*
  17  * Include common defines/options for all AMCC eval boards
  18  */
  19 #define CONFIG_HOSTNAME         neo
  20 #include "amcc-common.h"
  21
  22 #define CONFIG_BOARD_EARLY_INIT_R
  23 #define CONFIG_MISC_INIT_R
  24 #define CONFIG_LAST_STAGE_INIT
  25
  26 #define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
  27
  28 /*
  29  * Configure PLL
  30  */
  31 #define PLLMR0_DEFAULT PLLMR0_266_133_66_33
  32 #define PLLMR1_DEFAULT PLLMR1_266_133_66_33
  33
  34 #define CONFIG_ENV_IS_IN_FLASH  /* use FLASH for environment vars */
  35
  36 /*
  37  * Default environment variables
  38  */
  39 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  40         CONFIG_AMCC_DEF_ENV                                             \
  41         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
  42         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
  43         "kernel_addr=fc000000\0"                                        \
  44         "fdt_addr=fc1e0000\0"                                           \
  45         "ramdisk_addr=fc200000\0"                                       \
  46         ""
  47
  48 #define CONFIG_PHY_ADDR         4       /* PHY address                  */
  49 #define CONFIG_HAS_ETH0
  50 #define CONFIG_HAS_ETH1
  51 #define CONFIG_PHY1_ADDR        0xc     /* EMAC1 PHY address            */
  52 #define CONFIG_PHY_CLK_FREQ    EMAC_STACR_CLK_66MHZ
  53
  54 /*
  55  * Commands additional to the ones defined in amcc-common.h
  56  */
  57 #define CONFIG_CMD_DTT
  58 #undef CONFIG_CMD_EEPROM
  59 #undef CONFIG_CMD_IRQ
  60
  61 /*
  62  * SDRAM configuration (please see cpu/ppc/sdram.[ch])
  63  */
  64 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0 */
  65
  66 /* SDRAM timings used in datasheet */
  67 #define CONFIG_SYS_SDRAM_CL            3        /* CAS latency */
  68 #define CONFIG_SYS_SDRAM_tRP           20       /* PRECHARGE command period */
  69 #define CONFIG_SYS_SDRAM_tRC           66       /* ACTIVE-to-ACTIVE command period */
  70 #define CONFIG_SYS_SDRAM_tRCD          20       /* ACTIVE-to-READ delay */
  71 #define CONFIG_SYS_SDRAM_tRFC           66      /* Auto refresh period */
  72
  73 /*
  74  * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
  75  * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
  76  * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
  77  * The Linux BASE_BAUD define should match this configuration.
  78  *    baseBaud = cpuClock/(uartDivisor*16)
  79  * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
  80  * set Linux BASE_BAUD to 403200.
  81  */
  82 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  83 #define CONFIG_SYS_NS16550_SERIAL
  84 #define CONFIG_SYS_NS16550_REG_SIZE     1
  85 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  86
  87 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* external serial clock */
  88 #undef  CONFIG_SYS_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
  89 #define CONFIG_SYS_BASE_BAUD            691200
  90
  91 /*
  92  * I2C stuff
  93  */
  94 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           100000
  95
  96 /* RTC */
  97 #define CONFIG_RTC_DS1337
  98 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  99
 100 /* Temp sensor/hwmon/dtt */
 101 #define CONFIG_DTT_LM63         1       /* National LM63        */
 102 #define CONFIG_DTT_SENSORS      { 0 }   /* Sensor addresses     */
 103 #define CONFIG_DTT_PWM_LOOKUPTABLE      \
 104                 { { 40, 10 }, { 50, 20 }, { 60, 40 } }
 105 #define CONFIG_DTT_TACH_LIMIT   0xa10
 106
 107 /*
 108  * FLASH organization
 109  */
 110 #define CONFIG_SYS_FLASH_CFI                            /* The flash is CFI compatible  */
 111 #define CONFIG_FLASH_CFI_DRIVER                 /* Use common CFI driver        */
 112
 113 #define CONFIG_SYS_FLASH_BASE           0xFC000000
 114 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 115
 116 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 117 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 118
 119 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 120 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 121
 122 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 123
 124 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 125 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash        */
 126
 127 #ifdef CONFIG_ENV_IS_IN_FLASH
 128 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector          */
 129 #define CONFIG_ENV_ADDR         0xFFF00000
 130 #define CONFIG_ENV_SIZE         0x20000 /* Total Size of Environment Sector */
 131
 132 /* Address and size of Redundant Environment Sector     */
 133 #define CONFIG_ENV_ADDR_REDUND  0xFFF20000
 134 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 135 #endif
 136
 137 /*
 138  * PPC405 GPIO Configuration
 139  */
 140 #define CONFIG_SYS_4xx_GPIO_TABLE { \
 141 { \
 142 /* GPIO Core 0 */ \
 143 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0   PerBLast   */ \
 144 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1   TS1E       */ \
 145 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2   TS2E       */ \
 146 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3   TS1O       */ \
 147 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4   TS2O       */ \
 148 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5   TS3        */ \
 149 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6   TS4        */ \
 150 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO7   TS5        */ \
 151 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8   TS6        */ \
 152 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9   TrcClk     */ \
 153 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10  PerCS1     */ \
 154 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11  PerCS2     */ \
 155 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12  PerCS3     */ \
 156 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13  PerCS4     */ \
 157 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14  PerAddr03  */ \
 158 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15  PerAddr04  */ \
 159 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16  PerAddr05  */ \
 160 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17  IRQ0       */ \
 161 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18  IRQ1       */ \
 162 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19  IRQ2       */ \
 163 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20  IRQ3       */ \
 164 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21  IRQ4       */ \
 165 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22  IRQ5       */ \
 166 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23  IRQ6       */ \
 167 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24  UART0_DCD  */ \
 168 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25  UART0_DSR  */ \
 169 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26  UART0_RI   */ \
 170 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27  UART0_DTR  */ \
 171 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28  UART1_Rx   */ \
 172 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29  UART1_Tx   */ \
 173 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30  RejectPkt0 */ \
 174 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31  RejectPkt1 */ \
 175 } \
 176 }
 177
 178 /*
 179  * Definitions for initial stack pointer and data area (in data cache)
 180  */
 181 /* use on chip memory (OCM) for temperary stack until sdram is tested */
 182 #define CONFIG_SYS_TEMP_STACK_OCM        1
 183
 184 /* On Chip Memory location */
 185 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 186 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 187 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 188 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 189
 190 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 191 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 192
 193 /*
 194  * External Bus Controller (EBC) Setup
 195  */
 196
 197 /* Memory Bank 0 (NOR-FLASH) initialization                    */
 198 #define CONFIG_SYS_EBC_PB0AP            0x92015480
 199 #define CONFIG_SYS_EBC_PB0CR            0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
 200
 201 /* Memory Bank 1 (NVRAM) initialization                                        */
 202 #define CONFIG_SYS_EBC_PB1AP            0x92015480
 203 #define CONFIG_SYS_EBC_PB1CR            0xFB85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit  */
 204
 205 /* Memory Bank 2 (FPGA) initialization                 */
 206 #define CONFIG_SYS_FPGA0_BASE           0x7f100000
 207 #define CONFIG_SYS_EBC_PB2AP            0x92015480
 208 #define CONFIG_SYS_EBC_PB2CR            0x7f11a000  /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
 209
 210 #define CONFIG_SYS_FPGA_BASE(k)         CONFIG_SYS_FPGA0_BASE
 211
 212 #define CONFIG_SYS_FPGA_COUNT           1
 213
 214 #define CONFIG_SYS_FPGA_PTR \
 215         { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
 216
 217 #define CONFIG_SYS_FPGA_COMMON
 218
 219 /* Memory Bank 3 (Latches) initialization                      */
 220 #define CONFIG_SYS_LATCH_BASE           0x7f200000
 221 #define CONFIG_SYS_EBC_PB3AP            0x92015480
 222 #define CONFIG_SYS_EBC_PB3CR            0x7f21a000  /* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
 223
 224 #define CONFIG_SYS_LATCH0_RESET         0xffff
 225 #define CONFIG_SYS_LATCH0_BOOT          0xffff
 226 #define CONFIG_SYS_LATCH1_RESET         0xffbf
 227 #define CONFIG_SYS_LATCH1_BOOT          0xffff
 228
 229 #endif  /* __CONFIG_H */