include/configs/o2dnt.h

   1 /*
   2  * (C) Copyright 2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * High Level Configuration Options
  29  * (easy to change)
  30  */
  31 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU */
  32 #define CONFIG_MPC5200
  33 #define CONFIG_O2DNT            1       /* ... on O2DNT board */
  34
  35 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33.000000MHz */
  36
  37 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH  */
  38 #define BOOTFLAG_WARM           0x02    /* Software reboot           */
  39
  40 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
  41
  42 /*
  43  * Serial console configuration
  44  */
  45 #define CONFIG_PSC_CONSOLE      5       /* console is on PSC5 */
  46 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
  47 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  48
  49 /*
  50  * PCI Mapping:
  51  * 0x40000000 - 0x4fffffff - PCI Memory
  52  * 0x50000000 - 0x50ffffff - PCI IO Space
  53  */
  54 #define CONFIG_PCI              1
  55 #define CONFIG_PCI_PNP          1
  56 /* #define CONFIG_PCI_SCAN_SHOW 1 */
  57 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  58
  59 #define CONFIG_PCI_MEM_BUS      0x40000000
  60 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  61 #define CONFIG_PCI_MEM_SIZE     0x10000000
  62
  63 #define CONFIG_PCI_IO_BUS       0x50000000
  64 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  65 #define CONFIG_PCI_IO_SIZE      0x01000000
  66
  67 #define CONFIG_SYS_XLB_PIPELINING       1
  68
  69 #define CONFIG_NET_MULTI        1
  70 #define CONFIG_EEPRO100
  71 #define CONFIG_SYS_RX_ETH_BUFFER        8  /* use 8 rx buffer on eepro100  */
  72 #define CONFIG_NS8382X          1
  73
  74 /* Partitions */
  75 #define CONFIG_MAC_PARTITION
  76 #define CONFIG_DOS_PARTITION
  77 #define CONFIG_ISO_PARTITION
  78
  79 #define CONFIG_TIMESTAMP        /* Print image info with timestamp */
  80
  81
  82 /*
  83  * BOOTP options
  84  */
  85 #define CONFIG_BOOTP_BOOTFILESIZE
  86 #define CONFIG_BOOTP_BOOTPATH
  87 #define CONFIG_BOOTP_GATEWAY
  88 #define CONFIG_BOOTP_HOSTNAME
  89
  90
  91 /*
  92  * Command line configuration.
  93  */
  94 #include <config_cmd_default.h>
  95
  96 #define CONFIG_CMD_EEPROM
  97 #define CONFIG_CMD_FAT
  98 #define CONFIG_CMD_I2C
  99 #define CONFIG_CMD_NFS
 100 #define CONFIG_CMD_MII
 101 #define CONFIG_CMD_PING
 102 #define CONFIG_CMD_PCI
 103
 104
 105 #if (TEXT_BASE == 0xFF000000)           /* Boot low with 16 MB Flash */
 106 #   define CONFIG_SYS_LOWBOOT           1
 107 #else
 108 #   error "TEXT_BASE must be 0xFF000000"
 109 #endif
 110
 111 /*
 112  * Autobooting
 113  */
 114 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 115
 116 #define CONFIG_PREBOOT  "echo;" \
 117         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 118         "echo"
 119
 120 #undef  CONFIG_BOOTARGS
 121
 122 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 123         "netdev=eth0\0"                                                 \
 124         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 125                 "nfsroot=${serverip}:${rootpath}\0"                     \
 126         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 127         "addip=setenv bootargs ${bootargs} "                            \
 128                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 129                 ":${hostname}:${netdev}:off panic=1\0"                  \
 130         "flash_nfs=run nfsargs addip;"                                  \
 131                 "bootm ${kernel_addr}\0"                                \
 132         "flash_self=run ramargs addip;"                                 \
 133                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 134         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
 135         "rootpath=/opt/eldk/ppc_82xx\0"                                 \
 136         "bootfile=/tftpboot/MPC5200/uImage\0"                           \
 137         ""
 138
 139 #define CONFIG_BOOTCOMMAND      "run flash_self"
 140
 141 /*
 142  * IPB Bus clocking configuration.
 143  */
 144 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
 145
 146 #if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
 147 /*
 148  * PCI Bus clocking configuration
 149  *
 150  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 151  * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
 152  *  of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
 153  */
 154 #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2    /* define for 66MHz speed */
 155 #endif
 156
 157 /*
 158  * I2C configuration
 159  */
 160 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 161 #define CONFIG_SYS_I2C_MODULE           1       /* Select I2C module #1 or #2 */
 162
 163 #define CONFIG_SYS_I2C_SPEED            100000 /* 100 kHz */
 164 #define CONFIG_SYS_I2C_SLAVE            0x7F
 165
 166 /*
 167  * EEPROM configuration:
 168  *
 169  * O2DNT board is equiped with Ramtron FRAM device FM24CL16
 170  * 16 Kib Ferroelectric Nonvolatile serial RAM memory
 171  * organized as 2048 x 8 bits and addressable as eight I2C devices
 172  * 0x50 ... 0x57 each 256 bytes in size
 173  *
 174  */
 175 #define CONFIG_SYS_I2C_FRAM
 176 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x */
 177 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 178 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 179 /*
 180  * There is no write delay with FRAM, write operations are performed at bus
 181  * speed. Thus, no status polling or write delay is needed.
 182  */
 183 /*#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70*/
 184
 185
 186 /*
 187  * Flash configuration
 188  */
 189 #define CONFIG_SYS_FLASH_BASE           0xFF000000
 190 #define CONFIG_SYS_FLASH_SIZE           0x01000000
 191 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00040000)
 192
 193 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks      */
 194 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max num of sects on one chip */
 195
 196 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 197 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 198 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    10000   /* Timeout for Flash Clear Lock Bits (in ms) */
 199 #define CONFIG_SYS_FLASH_PROTECTION             /* "Real" (hardware) sectors protection */
 200
 201 /*
 202  * Environment settings
 203  */
 204 #define CONFIG_ENV_IS_IN_FLASH  1
 205 #define CONFIG_ENV_SIZE         0x20000
 206 #define CONFIG_ENV_SECT_SIZE    0x20000
 207 #define CONFIG_ENV_OVERWRITE    1
 208
 209 /*
 210  * Memory map
 211  */
 212 #define CONFIG_SYS_MBAR         0xF0000000
 213 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 214 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 215
 216 /* Use SRAM until RAM will be available */
 217 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 218 #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE       /* End of used area in DPRAM */
 219
 220
 221 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* size in bytes reserved for initial data */
 222 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 223 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 224
 225 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
 226 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor   */
 227 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 228 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 229
 230 /*
 231  * Ethernet configuration
 232  */
 233 #define CONFIG_MPC5xxx_FEC      1
 234 #define CONFIG_MPC5xxx_FEC_MII100
 235 /*
 236  * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 237  */
 238 /* #define CONFIG_MPC5xxx_FEC_MII10 */
 239 #define CONFIG_PHY_ADDR         0x00
 240
 241 /*
 242  * GPIO configuration
 243  */
 244 /*#define CONFIG_SYS_GPS_PORT_CONFIG    0x10002004 */
 245 #define CONFIG_SYS_GPS_PORT_CONFIG      0x00002006      /* no CAN */
 246
 247 /*
 248  * Miscellaneous configurable options
 249  */
 250 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 251 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt   */
 252
 253 #if defined(CONFIG_CMD_KGDB)
 254 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 255 #else
 256 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 257 #endif
 258 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
 259 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 260 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 261
 262 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 263 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 264
 265 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 266
 267 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 268
 269 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs */
 270 #if defined(CONFIG_CMD_KGDB)
 271 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 272 #endif
 273
 274 /*
 275  * Various low-level settings
 276  */
 277 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 278 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 279
 280 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 281 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 282
 283 #ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
 284 /*
 285  * For 66 MHz PCI clock additional Wait State is needed for CS0 (flash).
 286  */
 287 #define CONFIG_SYS_BOOTCS_CFG           0x00057801 /* for pci_clk = 66 MHz */
 288 #else
 289 #define CONFIG_SYS_BOOTCS_CFG           0x00047801 /* for pci_clk = 33 MHz */
 290 #endif
 291
 292 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 293 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 294
 295 #define CONFIG_SYS_CS_BURST             0x00000000
 296 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
 297
 298 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
 299
 300 #endif /* __CONFIG_H */