include/configs/omap1510.h

   1 /*
   2  *
   3  * BRIEF MODULE DESCRIPTION
   4  *   OMAP hardware map
   5  *
   6  * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com)
   7  * Author: RidgeRun, Inc.
   8  *         Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com
   9  *
  10  *  This program is free software; you can redistribute  it and/or modify it
  11  *  under  the terms of  the GNU General  Public License as published by the
  12  *  Free Software Foundation;  either version 2 of the  License, or (at your
  13  *  option) any later version.
  14  *
  15  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  16  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  17  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  18  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  19  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  21  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  22  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  23  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  24  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  *  You should have received a copy of the  GNU General Public License along
  27  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  28  *  675 Mass Ave, Cambridge, MA 02139, USA.
  29  */
  30
  31 #include <asm/arch/sizes.h>
  32
  33 /*
  34   There are 2 sets of general I/O -->
  35   1. GPIO (shared between ARM & DSP, configured by ARM)
  36   2. MPUIO which can be used only by the ARM.
  37
  38   Base address FFFB:5000 is where the ARM accesses the MPUIO control registers
  39   (see 7.2.2 of the TRM for MPUIO reg definitions).
  40
  41   Base address E101:5000 is reserved for ARM access of the same MPUIO control
  42   regs, but via the DSP I/O map.  This address is unavailable on 1510.
  43
  44   Base address FFFC:E000 is where the ARM accesses the GPIO config registers
  45   directly via its own peripheral bus.
  46
  47   Base address E101:E000 is where the ARM can access the same GPIO config
  48   registers, but the access takes place through the ARM port interface (called
  49   API or MPUI) via the DSP's peripheral bus (DSP I/O space).
  50
  51   Therefore, the ARM should setup the GPIO regs thru the FFFC:E000 addresses
  52   instead of the E101:E000 addresses.  The DSP has only read access of the pin
  53   control register, so this may explain the inability to write to E101:E018.
  54   Try accessing pin control reg at FFFC:E018.
  55  */
  56 #define OMAP1510_GPIO_BASE       0xfffce000
  57 #define OMAP1510_GPIO_START      OMAP1510_GPIO_BASE
  58 #define OMAP1510_GPIO_SIZE       SZ_4K
  59
  60 #define OMAP1510_MCBSP1_BASE     0xE1011000
  61 #define OMAP1510_MCBSP1_SIZE     SZ_4K
  62 #define OMAP1510_MCBSP1_START    0xE1011000
  63
  64 #define OMAP1510_MCBSP2_BASE     0xFFFB1000
  65
  66 #define OMAP1510_MCBSP3_BASE     0xE1017000
  67 #define OMAP1510_MCBSP3_SIZE     SZ_4K
  68 #define OMAP1510_MCBSP3_START    0xE1017000
  69
  70 /*
  71  * Where's the flush address (for flushing D and I cache?)
  72  */
  73 #define FLUSH_BASE              0xdf000000
  74 #define FLUSH_BASE_PHYS 0x00000000
  75
  76 #ifndef __ASSEMBLER__
  77
  78 #define PCIO_BASE               0
  79
  80 /*
  81  * RAM definitions
  82  */
  83 #define MAPTOPHYS(a)            ((unsigned long)(a) - PAGE_OFFSET)
  84 #define KERNTOPHYS(a)           ((unsigned long)(&a))
  85 #define KERNEL_BASE             (0x10008000)
  86 #endif
  87
  88 /* macro to get at IO space when running virtually */
  89 #define IO_ADDRESS(x) ((x))
  90
  91 /* ----------------------------------------------------------------------------
  92  *  OMAP1510 system registers
  93  * ----------------------------------------------------------------------------
  94  */
  95
  96 #define OMAP1510_UART1_BASE         0xfffb0000   /* "BLUETOOTH-UART" */
  97 #define OMAP1510_UART2_BASE         0xfffb0800   /* "MODEM-UART" */
  98 #define OMAP1510_RTC_BASE           0xfffb4800   /* RTC */
  99 #define OMAP1510_UART3_BASE         0xfffb9800   /* Shared MPU/DSP UART */
 100 #define OMAP1510_COM_MCBSP2_BASE    0xffff1000   /* Com McBSP2 */
 101 #define OMAP1510_AUDIO_MCBSP_BASE   0xffff1800   /* Audio McBSP2 */
 102 #define OMAP1510_ARMIO_BASE         0xfffb5000   /* keyboard/gpio */
 103
 104 /*
 105  * OMAP1510 UART3 Registers
 106  */
 107
 108 #define OMAP_MPU_UART3_BASE  0xFFFB9800 /* UART3 through MPU bus */
 109
 110 /* UART3 Registers Maping through MPU bus */
 111
 112 #define UART3_RHR        (OMAP_MPU_UART3_BASE + 0)
 113 #define UART3_THR        (OMAP_MPU_UART3_BASE + 0)
 114 #define UART3_DLL        (OMAP_MPU_UART3_BASE + 0)
 115 #define UART3_IER        (OMAP_MPU_UART3_BASE + 4)
 116 #define UART3_DLH        (OMAP_MPU_UART3_BASE + 4)
 117 #define UART3_IIR        (OMAP_MPU_UART3_BASE + 8)
 118 #define UART3_FCR        (OMAP_MPU_UART3_BASE + 8)
 119 #define UART3_EFR        (OMAP_MPU_UART3_BASE + 8)
 120 #define UART3_LCR        (OMAP_MPU_UART3_BASE + 0x0C)
 121 #define UART3_MCR        (OMAP_MPU_UART3_BASE + 0x10)
 122 #define UART3_XON1_ADDR1 (OMAP_MPU_UART3_BASE + 0x10)
 123 #define UART3_XON2_ADDR2 (OMAP_MPU_UART3_BASE + 0x14)
 124 #define UART3_LSR        (OMAP_MPU_UART3_BASE + 0x14)
 125 #define UART3_TCR        (OMAP_MPU_UART3_BASE + 0x18)
 126 #define UART3_MSR        (OMAP_MPU_UART3_BASE + 0x18)
 127 #define UART3_XOFF1      (OMAP_MPU_UART3_BASE + 0x18)
 128 #define UART3_XOFF2      (OMAP_MPU_UART3_BASE + 0x1C)
 129 #define UART3_SPR        (OMAP_MPU_UART3_BASE + 0x1C)
 130 #define UART3_TLR        (OMAP_MPU_UART3_BASE + 0x1C)
 131 #define UART3_MDR1       (OMAP_MPU_UART3_BASE + 0x20)
 132 #define UART3_MDR2       (OMAP_MPU_UART3_BASE + 0x24)
 133 #define UART3_SFLSR      (OMAP_MPU_UART3_BASE + 0x28)
 134 #define UART3_TXFLL      (OMAP_MPU_UART3_BASE + 0x28)
 135 #define UART3_RESUME     (OMAP_MPU_UART3_BASE + 0x2C)
 136 #define UART3_TXFLH      (OMAP_MPU_UART3_BASE + 0x2C)
 137 #define UART3_SFREGL     (OMAP_MPU_UART3_BASE + 0x30)
 138 #define UART3_RXFLL      (OMAP_MPU_UART3_BASE + 0x30)
 139 #define UART3_SFREGH     (OMAP_MPU_UART3_BASE + 0x34)
 140 #define UART3_RXFLH      (OMAP_MPU_UART3_BASE + 0x34)
 141 #define UART3_BLR        (OMAP_MPU_UART3_BASE + 0x38)
 142 #define UART3_ACREG      (OMAP_MPU_UART3_BASE + 0x3C)
 143 #define UART3_DIV16      (OMAP_MPU_UART3_BASE + 0x3C)
 144 #define UART3_SCR        (OMAP_MPU_UART3_BASE + 0x40)
 145 #define UART3_SSR        (OMAP_MPU_UART3_BASE + 0x44)
 146 #define UART3_EBLR       (OMAP_MPU_UART3_BASE + 0x48)
 147 #define UART3_OSC_12M_SEL (OMAP_MPU_UART3_BASE + 0x4C)
 148 #define UART3_MVR        (OMAP_MPU_UART3_BASE + 0x50)
 149
 150 /*
 151  * Configuration Registers
 152  */
 153 #define FUNC_MUX_CTRL_0         0xfffe1000
 154 #define FUNC_MUX_CTRL_1         0xfffe1004
 155 #define FUNC_MUX_CTRL_2         0xfffe1008
 156 #define COMP_MODE_CTRL_0        0xfffe100c
 157 #define FUNC_MUX_CTRL_3         0xfffe1010
 158 #define FUNC_MUX_CTRL_4         0xfffe1014
 159 #define FUNC_MUX_CTRL_5         0xfffe1018
 160 #define FUNC_MUX_CTRL_6         0xfffe101C
 161 #define FUNC_MUX_CTRL_7         0xfffe1020
 162 #define FUNC_MUX_CTRL_8         0xfffe1024
 163 #define FUNC_MUX_CTRL_9         0xfffe1028
 164 #define FUNC_MUX_CTRL_A         0xfffe102C
 165 #define FUNC_MUX_CTRL_B         0xfffe1030
 166 #define FUNC_MUX_CTRL_C         0xfffe1034
 167 #define FUNC_MUX_CTRL_D         0xfffe1038
 168 #define PULL_DWN_CTRL_0         0xfffe1040
 169 #define PULL_DWN_CTRL_1         0xfffe1044
 170 #define PULL_DWN_CTRL_2         0xfffe1048
 171 #define PULL_DWN_CTRL_3         0xfffe104c
 172 #define GATE_INH_CTRL_0         0xfffe1050
 173 #define VOLTAGE_CTRL_0          0xfffe1060
 174 #define TEST_DBG_CTRL_0         0xfffe1070
 175
 176 #define MOD_CONF_CTRL_0         0xfffe1080
 177
 178 /*
 179  * Traffic Controller Memory Interface Registers
 180  */
 181 #define TCMIF_BASE              0xfffecc00
 182 #define IMIF_PRIO               (TCMIF_BASE + 0x00)
 183 #define EMIFS_PRIO_REG          (TCMIF_BASE + 0x04)
 184 #define EMIFF_PRIO_REG          (TCMIF_BASE + 0x08)
 185 #define EMIFS_CONFIG_REG        (TCMIF_BASE + 0x0c)
 186 #define EMIFS_CS0_CONFIG        (TCMIF_BASE + 0x10)
 187 #define EMIFS_CS1_CONFIG        (TCMIF_BASE + 0x14)
 188 #define EMIFS_CS2_CONFIG        (TCMIF_BASE + 0x18)
 189 #define EMIFS_CS3_CONFIG        (TCMIF_BASE + 0x1c)
 190 #define EMIFF_SDRAM_CONFIG      (TCMIF_BASE + 0x20)
 191 #define EMIFF_MRS               (TCMIF_BASE + 0x24)
 192 #define TC_TIMEOUT1             (TCMIF_BASE + 0x28)
 193 #define TC_TIMEOUT2             (TCMIF_BASE + 0x2c)
 194 #define TC_TIMEOUT3             (TCMIF_BASE + 0x30)
 195 #define TC_ENDIANISM            (TCMIF_BASE + 0x34)
 196 #define EMIFF_SDRAM_CONFIG_2    (TCMIF_BASE + 0x3c)
 197 #define EMIF_CFG_DYNAMIC_WS     (TCMIF_BASE + 0x40)
 198
 199 /*
 200  * LCD Panel
 201  */
 202 #define TI925_LCD_BASE          0xFFFEC000
 203 #define TI925_LCD_CONTROL       (TI925_LCD_BASE)
 204 #define TI925_LCD_TIMING0       (TI925_LCD_BASE+0x4)
 205 #define TI925_LCD_TIMING1       (TI925_LCD_BASE+0x8)
 206 #define TI925_LCD_TIMING2       (TI925_LCD_BASE+0xc)
 207 #define TI925_LCD_STATUS        (TI925_LCD_BASE+0x10)
 208 #define TI925_LCD_SUBPANEL      (TI925_LCD_BASE+0x14)
 209
 210 #define OMAP_LCD_CONTROL        TI925_LCD_CONTROL
 211
 212 /*
 213  * MMC/SD Host Controller Registers
 214  */
 215
 216 #define OMAP_MMC_CMD     0xFFFB7800 /* MMC Command */
 217 #define OMAP_MMC_ARGL    0xFFFB7804 /* MMC argument low */
 218 #define OMAP_MMC_ARGH    0xFFFB7808 /* MMC argument high */
 219 #define OMAP_MMC_CON     0xFFFB780C /* MMC system configuration */
 220 #define OMAP_MMC_STAT    0xFFFB7810 /* MMC status */
 221 #define OMAP_MMC_IE      0xFFFB7814 /* MMC system interrupt enable */
 222 #define OMAP_MMC_CTO     0xFFFB7818 /* MMC command time-out */
 223 #define OMAP_MMC_DTO     0xFFFB781C /* MMC data time-out */
 224 #define OMAP_MMC_DATA    0xFFFB7820 /* MMC TX/RX FIFO data */
 225 #define OMAP_MMC_BLEN    0xFFFB7824 /* MMC block length */
 226 #define OMAP_MMC_NBLK    0xFFFB7828 /* MMC number of blocks */
 227 #define OMAP_MMC_BUF     0xFFFB782C /* MMC buffer configuration */
 228 #define OMAP_MMC_SPI     0xFFFB7830 /* MMC serial port interface */
 229 #define OMAP_MMC_SDIO    0xFFFB7834 /* MMC SDIO mode configuration */
 230 #define OMAP_MMC_SYST    0xFFFB7838 /* MMC system test */
 231 #define OMAP_MMC_REV     0xFFFB783C /* MMC module version */
 232 #define OMAP_MMC_RSP0    0xFFFB7840 /* MMC command response 0 */
 233 #define OMAP_MMC_RSP1    0xFFFB7844 /* MMC command response 1 */
 234 #define OMAP_MMC_RSP2    0xFFFB7848 /* MMC command response 2 */
 235 #define OMAP_MMC_RSP3    0xFFFB784C /* MMC command response 3 */
 236 #define OMAP_MMC_RSP4    0xFFFB7850 /* MMC command response 4 */
 237 #define OMAP_MMC_RSP5    0xFFFB7854 /* MMC command response 5 */
 238 #define OMAP_MMC_RSP6    0xFFFB7858 /* MMC command response 6 */
 239 #define OMAP_MMC_RSP7    0xFFFB785C /* MMC command response 4 */
 240
 241 /* MMC masks */
 242
 243 #define OMAP_MMC_END_OF_CMD     (1 << 0)        /* End of command phase */
 244 #define OMAP_MMC_CARD_BUSY      (1 << 2)        /* Card enter busy state */
 245 #define OMAP_MMC_BLOCK_RS       (1 << 3)        /* Block received/sent */
 246 #define OMAP_MMC_EOF_BUSY       (1 << 4)        /* Card exit busy state */
 247 #define OMAP_MMC_DATA_TIMEOUT   (1 << 5)        /* Data response time-out */
 248 #define OMAP_MMC_DATA_CRC       (1 << 6)        /* Date CRC error */
 249 #define OMAP_MMC_CMD_TIMEOUT    (1 << 7)        /* Command response time-out */
 250 #define OMAP_MMC_CMD_CRC        (1 << 8)        /* Command CRC error */
 251 #define OMAP_MMC_A_FULL         (1 << 10)       /* Buffer almost full */
 252 #define OMAP_MMC_A_EMPTY        (1 << 11)       /* Buffer almost empty */
 253 #define OMAP_MMC_OCR_BUSY       (1 << 12)       /* OCR busy */
 254 #define OMAP_MMC_CARD_IRQ       (1 << 13)       /* Card IRQ received */
 255 #define OMAP_MMC_CARD_ERR       (1 << 14)       /* Card status error in response */
 256
 257 /* 2.9.2 MPUI Interface Registers FFFE:C900 */
 258
 259 #define MPUI_CTRL_REG           (volatile __u32 *)(0xfffec900)
 260 #define MPUI_DEBUG_ADDR         (volatile __u32 *)(0xfffec904)
 261 #define MPUI_DEBUG_DATA         (volatile __u32 *)(0xfffec908)
 262 #define MPUI_DEBUG_FLAG         (volatile __u16 *)(0xfffec90c)
 263 #define MPUI_STATUS_REG         (volatile __u16 *)(0xfffec910)
 264 #define MPUI_DSP_STATUS_REG     (volatile __u16 *)(0xfffec914)
 265 #define MPUI_DSP_BOOT_CONFIG    (volatile __u16 *)(0xfffec918)
 266 #define MPUI_DSP_API_CONFIG     (volatile __u16 *)(0xfffec91c)
 267
 268 /* 2.9.6 Traffic Controller Memory Interface Registers: */
 269 #define OMAP_IMIF_PRIO_REG              0xfffecc00
 270 #define OMAP_EMIFS_PRIO_REG             0xfffecc04
 271 #define OMAP_EMIFF_PRIO_REG             0xfffecc08
 272 #define OMAP_EMIFS_CONFIG_REG           0xfffecc0c
 273 #define OMAP_EMIFS_CS0_CONFIG           0xfffecc10
 274 #define OMAP_EMIFS_CS1_CONFIG           0xfffecc14
 275 #define OMAP_EMIFS_CS2_CONFIG           0xfffecc18
 276 #define OMAP_EMIFS_CS3_CONFIG           0xfffecc1c
 277 #define OMAP_EMIFF_SDRAM_CONFIG         0xfffecc20
 278 #define OMAP_EMIFF_MRS                  0xfffecc24
 279 #define OMAP_TIMEOUT1                   0xfffecc28
 280 #define OMAP_TIMEOUT2                   0xfffecc2c
 281 #define OMAP_TIMEOUT3                   0xfffecc30
 282 #define OMAP_ENDIANISM                  0xfffecc34
 283
 284 /* 2.9.10 EMIF Slow Interface Configuration Register (EMIFS_CONFIG_REG): */
 285 #define OMAP_EMIFS_CONFIG_FR            (1 << 4)
 286 #define OMAP_EMIFS_CONFIG_PDE           (1 << 3)
 287 #define OMAP_EMIFS_CONFIG_PWD_EN        (1 << 2)
 288 #define OMAP_EMIFS_CONFIG_BM            (1 << 1)
 289 #define OMAP_EMIFS_CONFIG_WP            (1 << 0)
 290
 291 /*
 292  * Memory chunk set aside for the Framebuffer in SRAM
 293  */
 294 #define SRAM_FRAMEBUFFER_MEMORY OMAP1510_SRAM_BASE
 295
 296
 297 /*
 298  * DMA
 299  */
 300
 301 #define OMAP1510_DMA_BASE 0xFFFED800
 302 #define OMAP_DMA_BASE     OMAP1510_DMA_BASE
 303
 304 /* Global Register selection */
 305 #define NO_GLOBAL_DMA_ACCESS 0
 306
 307 /* Channel select field
 308  * NOTE: all other channels are linear, chan0 is 0, chan1 is 1, etc...
 309  */
 310 #define LCD_CHANNEL 0xc
 311
 312 /* Register Select Field (LCD) */
 313 #define DMA_LCD_CTRL            0
 314 #define DMA_LCD_TOP_F1_L        1
 315 #define DMA_LCD_TOP_F1_U        2
 316 #define DMA_LCD_BOT_F1_L        3
 317 #define DMA_LCD_BOT_F1_U        4
 318
 319 #define LCD_FRAME_MODE          (1<<0)
 320 #define LCD_FRAME_IT_IE         (1<<1)
 321 #define LCD_BUS_ERROR_IT_IE     (1<<2)
 322 #define LCD_FRAME_1_IT_COND     (1<<3)
 323 #define LCD_FRAME_2_IT_COND     (1<<4)
 324 #define LCD_BUS_ERROR_IT_COND   (1<<5)
 325 #define LCD_SOURCE_IMIF         (1<<6)
 326
 327 /*
 328  * Real-Time Clock
 329  */
 330
 331 #define RTC_SECONDS             (volatile __u8 *)(OMAP1510_RTC_BASE + 0x00)
 332 #define RTC_MINUTES             (volatile __u8 *)(OMAP1510_RTC_BASE + 0x04)
 333 #define RTC_HOURS               (volatile __u8 *)(OMAP1510_RTC_BASE + 0x08)
 334 #define RTC_DAYS                (volatile __u8 *)(OMAP1510_RTC_BASE + 0x0C)
 335 #define RTC_MONTHS              (volatile __u8 *)(OMAP1510_RTC_BASE + 0x10)
 336 #define RTC_YEARS               (volatile __u8 *)(OMAP1510_RTC_BASE + 0x14)
 337 #define RTC_CTRL                (volatile __u8 *)(OMAP1510_RTC_BASE + 0x40)
 338
 339
 340 /* ---------------------------------------------------------------------------
 341  *  OMAP1510 Interrupt Handlers
 342  * ---------------------------------------------------------------------------
 343  *
 344  */
 345 #define OMAP_IH1_BASE           0xfffecb00
 346 #define OMAP_IH2_BASE           0xfffe0000
 347 #define OMAP1510_ITR            0x0
 348 #define OMAP1510_MASK           0x4
 349
 350 #define INTERRUPT_HANDLER_BASE   OMAP_IH1_BASE
 351 #define INTERRUPT_INPUT_REGISTER OMAP1510_ITR
 352 #define INTERRUPT_MASK_REGISTER  OMAP1510_MASK
 353
 354
 355 /* ---------------------------------------------------------------------------
 356  *  OMAP1510 TIMERS
 357  * ---------------------------------------------------------------------------
 358  *
 359  */
 360
 361 #define OMAP1510_32kHz_TIMER_BASE 0xfffb9000
 362
 363 /* 32k Timer Registers */
 364 #define TIMER32k_CR     0x08
 365 #define TIMER32k_TVR    0x00
 366 #define TIMER32k_TCR    0x04
 367
 368 /* 32k Timer Control Register definition */
 369 #define TIMER32k_TSS    (1<<0)
 370 #define TIMER32k_TRB    (1<<1)
 371 #define TIMER32k_INT    (1<<2)
 372 #define TIMER32k_ARL    (1<<3)
 373
 374 /* MPU Timer base addresses  */
 375 #define OMAP1510_MPUTIMER_BASE  0xfffec500
 376 #define OMAP1510_MPUTIMER_OFF   0x00000100
 377
 378 #define OMAP1510_TIMER1_BASE    0xfffec500
 379 #define OMAP1510_TIMER2_BASE    0xfffec600
 380 #define OMAP1510_TIMER3_BASE    0xfffec700
 381
 382 /* MPU Timer Registers */
 383 #define CNTL_TIMER      0
 384 #define LOAD_TIM        4
 385 #define READ_TIM        8
 386
 387 /*  CNTL_TIMER register bits */
 388 #define MPUTIM_FREE             (1<<6)
 389 #define MPUTIM_CLOCK_ENABLE     (1<<5)
 390 #define MPUTIM_PTV_MASK         (0x7<<PTV_BIT)
 391 #define MPUTIM_PTV_BIT          2
 392 #define MPUTIM_AR               (1<<1)
 393 #define MPUTIM_ST               (1<<0)
 394
 395 /* ---------------------------------------------------------------------------
 396  *  OMAP1510 GPIO (SHARED)
 397  * ---------------------------------------------------------------------------
 398  *
 399  */
 400 #define GPIO_DATA_INPUT_REG     (OMAP1510_GPIO_BASE + 0x0)
 401 #define GPIO_DATA_OUTPUT_REG    (OMAP1510_GPIO_BASE + 0x4)
 402 #define GPIO_DIR_CONTROL_REG    (OMAP1510_GPIO_BASE + 0x8)
 403 #define GPIO_INT_CONTROL_REG    (OMAP1510_GPIO_BASE + 0xc)
 404 #define GPIO_INT_MASK_REG       (OMAP1510_GPIO_BASE + 0x10)
 405 #define GPIO_INT_STATUS_REG     (OMAP1510_GPIO_BASE + 0x14)
 406 #define GPIO_PIN_CONTROL_REG    (OMAP1510_GPIO_BASE + 0x18)
 407
 408
 409 /* ---------------------------
 410  * OMAP1510 MPUIO (ARM only)
 411  *----------------------------
 412  */
 413 #define OMAP1510_MPUIO_BASE     0xFFFB5000
 414 #define MPUIO_DATA_INPUT_REG    (OMAP1510_MPUIO_BASE + 0x0)
 415 #define MPUIO_DATA_OUTPUT_REG   (OMAP1510_MPUIO_BASE + 0x4)
 416 #define MPUIO_DIR_CONTROL_REG   (OMAP1510_MPUIO_BASE + 0x8)
 417
 418 /* ---------------------------------------------------------------------------
 419  *  OMAP1510 TIPB (only)
 420  * ---------------------------------------------------------------------------
 421  *
 422  */
 423 #define TIPB_PUBLIC_CNTL_BASE           0xfffed300
 424 #define MPU_PUBLIC_TIPB_CNTL_REG        (TIPB_PUBLIC_CNTL_BASE + 0x8)
 425 #define TIPB_PRIVATE_CNTL_BASE          0xfffeca00
 426 #define MPU_PRIVATE_TIPB_CNTL_REG       (TIPB_PRIVATE_CNTL_BASE + 0x8)
 427
 428 /*
 429  * ---------------------------------------------------------------------------
 430  *  OMAP1510 Camera Interface
 431  * ---------------------------------------------------------------------------
 432  */
 433 #define CAMERA_BASE             (IO_BASE + 0x6800)
 434 #define CAM_CTRLCLOCK_REG       (CAMERA_BASE + 0x00)
 435 #define CAM_IT_STATUS_REG       (CAMERA_BASE + 0x04)
 436 #define CAM_MODE_REG            (CAMERA_BASE + 0x08)
 437 #define CAM_STATUS_REG          (CAMERA_BASE + 0x0C)
 438 #define CAM_CAMDATA_REG         (CAMERA_BASE + 0x10)
 439 #define CAM_GPIO_REG            (CAMERA_BASE + 0x14)
 440 #define CAM_PEAK_CTR_REG        (CAMERA_BASE + 0x18)
 441
 442 #if 0
 443 #ifndef __ASSEMBLY__
 444 typedef struct {
 445         __u32 ctrlclock;
 446         __u32 it_status;
 447         __u32 mode;
 448         __u32 status;
 449         __u32 camdata;
 450         __u32 gpio;
 451         __u32 peak_counter;
 452 } camera_regs_t;
 453 #endif
 454 #endif
 455
 456 /* CTRLCLOCK bit shifts */
 457 #define FOSCMOD_BIT     0
 458 #define FOSCMOD_MASK    (0x7 << FOSCMOD_BIT)
 459 #define  FOSCMOD_12MHz  0x0
 460 #define  FOSCMOD_6MHz   0x2
 461 #define  FOSCMOD_9_6MHz 0x4
 462 #define  FOSCMOD_24MHz  0x5
 463 #define  FOSCMOD_8MHz   0x6
 464 #define POLCLK          (1<<3)
 465 #define CAMEXCLK_EN     (1<<4)
 466 #define MCLK_EN         (1<<5)
 467 #define DPLL_EN         (1<<6)
 468 #define LCLK_EN         (1<<7)
 469
 470 /* IT_STATUS bit shifts */
 471 #define V_UP            (1<<0)
 472 #define V_DOWN          (1<<1)
 473 #define H_UP            (1<<2)
 474 #define H_DOWN          (1<<3)
 475 #define FIFO_FULL       (1<<4)
 476 #define DATA_XFER       (1<<5)
 477
 478 /* MODE bit shifts */
 479 #define CAMOSC          (1<<0)
 480 #define IMGSIZE_BIT     1
 481 #define IMGSIZE_MASK    (0x3 << IMGSIZE_BIT)
 482 #define  IMGSIZE_CIF    (0x0 << IMGSIZE_BIT)    /* 352x288 */
 483 #define  IMGSIZE_QCIF   (0x1 << IMGSIZE_BIT)    /* 176x144 */
 484 #define  IMGSIZE_VGA    (0x2 << IMGSIZE_BIT)    /* 640x480 */
 485 #define  IMGSIZE_QVGA   (0x3 << IMGSIZE_BIT)    /* 320x240 */
 486 #define ORDERCAMD       (1<<3)
 487 #define EN_V_UP         (1<<4)
 488 #define EN_V_DOWN       (1<<5)
 489 #define EN_H_UP         (1<<6)
 490 #define EN_H_DOWN       (1<<7)
 491 #define EN_DMA          (1<<8)
 492 #define THRESHOLD       (1<<9)
 493 #define THRESHOLD_BIT   9
 494 #define THRESHOLD_MASK  (0x7f<<9)
 495 #define EN_NIRQ         (1<<16)
 496 #define EN_FIFO_FULL    (1<<17)
 497 #define RAZ_FIFO        (1<<18)
 498
 499 /* STATUS bit shifts */
 500 #define VSTATUS         (1<<0)
 501 #define HSTATUS         (1<<1)
 502
 503 /* GPIO bit shifts */
 504 #define CAM_RST         (1<<0)
 505
 506
 507 /*********************
 508  * Watchdog timer.
 509  *********************/
 510 #define WDTIM_BASE      0xfffec800
 511 #define WDTIM_CONTROL   (WDTIM_BASE+0x00)
 512 #define WDTIM_LOAD      (WDTIM_BASE+0x04)
 513 #define WDTIM_READ      (WDTIM_BASE+0x04)
 514 #define WDTIM_MODE      (WDTIM_BASE+0x08)
 515
 516 /* Values to write to mode register to disable the watchdog function. */
 517 #define DISABLE_SEQ1    0xF5
 518 #define DISABLE_SEQ2    0xA0
 519
 520 /* WDTIM_CONTROL bit definitions. */
 521 #define WDTIM_CONTROL_ST        BIT7
 522
 523
 524
 525 /* ---------------------------------------------------------------------------
 526  *  Differentiating processor versions for those who care.
 527  * ---------------------------------------------------------------------------
 528  *
 529  */
 530 #define OMAP1509 0
 531 #define OMAP1510 1
 532
 533 #define OMAP1510_ID_CODE_REG 0xfffed404
 534
 535 #ifndef __ASSEMBLY__
 536 int cpu_type(void);
 537 #endif
 538
 539 /*
 540  * EVM Implementation Specifics.
 541  *
 542  * *** NOTE ***
 543  * Any definitions in these files should be prefixed by an identifier -
 544  * eg. OMAP1510P1_FLASH0_BASE .
 545  *
 546  */
 547 #ifdef CONFIG_OMAP_INNOVATOR
 548 #include "innovator.h"
 549 #endif
 550
 551 #ifdef CONFIG_OMAP_1510P1
 552 #include "omap1510p1.h"
 553 #endif
 554
 555 /*****************************************************************************/
 556
 557 #define CLKGEN_RESET_BASE (0xfffece00)
 558 #define ARM_CKCTL       (volatile __u16 *)(CLKGEN_RESET_BASE + 0x0)
 559 #define ARM_IDLECT1     (volatile __u16 *)(CLKGEN_RESET_BASE + 0x4)
 560 #define ARM_IDLECT2     (volatile __u16 *)(CLKGEN_RESET_BASE + 0x8)
 561 #define ARM_EWUPCT      (volatile __u16 *)(CLKGEN_RESET_BASE + 0xC)
 562 #define ARM_RSTCT1      (volatile __u16 *)(CLKGEN_RESET_BASE + 0x10)
 563 #define ARM_RSTCT2      (volatile __u16 *)(CLKGEN_RESET_BASE + 0x14)
 564 #define ARM_SYSST       (volatile __u16 *)(CLKGEN_RESET_BASE + 0x18)
 565
 566
 567 #define CK_CLKIN        12 /* MHz */
 568 #define CK_RATEF        1
 569 #define CK_IDLEF        2
 570 #define CK_ENABLEF      4
 571 #define CK_SELECTF      8
 572 #ifndef __ASSEMBLER__
 573 #define CK_DPLL1        ((volatile __u16 *)0xfffecf00)
 574 #else
 575 #define CK_DPLL1 (0xfffecf00)
 576 #endif
 577 #define SETARM_IDLE_SHIFT
 578
 579 /* ARM_CKCTL bit shifts */
 580 #define PERDIV          0
 581 #define LCDDIV          2
 582 #define ARMDIV          4
 583 #define DSPDIV          6
 584 #define TCDIV           8
 585 #define DSPMMUDIV       10
 586 #define ARM_TIMXO       12
 587 #define EN_DSPCK        13
 588 #define ARM_INTHCK_SEL  14 /* REVISIT -- where is this used? */
 589
 590 #define ARM_CKCTL_RSRVD_BIT15           (1 << 15)
 591 #define ARM_CKCTL_ARM_INTHCK_SEL        (1 << 14)
 592 #define ARM_CKCTL_EN_DSPCK              (1 << 13)
 593 #define ARM_CKCTL_ARM_TIMXO             (1 << 12)
 594 #define ARM_CKCTL_DSPMMU_DIV1           (1 << 11)
 595 #define ARM_CKCTL_DSPMMU_DIV2           (1 << 10)
 596 #define ARM_CKCTL_TCDIV1                (1 << 9)
 597 #define ARM_CKCTL_TCDIV2                (1 << 8)
 598 #define ARM_CKCTL_DSPDIV1               (1 << 7)
 599 #define ARM_CKCTL_DSPDIV0               (1 << 6)
 600 #define ARM_CKCTL_ARMDIV1               (1 << 5)
 601 #define ARM_CKCTL_ARMDIV0               (1 << 4)
 602 #define ARM_CKCTL_LCDDIV1               (1 << 3)
 603 #define ARM_CKCTL_LCDDIV0               (1 << 2)
 604 #define ARM_CKCTL_PERDIV1               (1 << 1)
 605 #define ARM_CKCTL_PERDIV0               (1 << 0)
 606
 607 /* ARM_IDLECT1 bit shifts */
 608 #define IDLWDT_ARM      0
 609 #define IDLXORP_ARM     1
 610 #define IDLPER_ARM      2
 611 #define IDLLCD_ARM      3
 612 #define IDLLB_ARM       4
 613 #define IDLHSAB_ARM     5
 614 #define IDLIF_ARM       6
 615 #define IDLDPLL_ARM     7
 616 #define IDLAPI_ARM      8
 617 #define IDLTIM_ARM      9
 618 #define SETARM_IDLE     11
 619
 620 /* ARM_IDLECT2 bit shifts */
 621 #define EN_WDTCK        0
 622 #define EN_XORPCK       1
 623 #define EN_PERCK        2
 624 #define EN_LCDCK        3
 625 #define EN_LBCK         4
 626 #define EN_HSABCK       5
 627 #define EN_APICK        6
 628 #define EN_TIMCK        7
 629 #define DMACK_REQ       8
 630 #define EN_GPIOCK       9
 631 #define EN_LBFREECK     10
 632
 633 #define ARM_RSTCT1_SW_RST       (1 << 3)
 634 #define ARM_RSTCT1_DSP_RST      (1 << 2)
 635 #define ARM_RSTCT1_DSP_EN       (1 << 1)
 636 #define ARM_RSTCT1_ARM_RST      (1 << 0)
 637
 638 /* ARM_RSTCT2 bit shifts */
 639 #define EN_PER          0
 640
 641 #define ARM_SYSST_RSRVD_BIT15   (1 << 15)
 642 #define ARM_SYSST_RSRVD_BIT14   (1 << 14)
 643 #define ARM_SYSST_CLOCK_SELECT2 (1 << 13)
 644 #define ARM_SYSST_CLOCK_SELECT1 (1 << 12)
 645 #define ARM_SYSST_CLOCK_SELECT0 (1 << 11)
 646 #define ARM_SYSST_RSRVD_BIT10   (1 << 10)
 647 #define ARM_SYSST_RSRVD_BIT9    (1 << 9)
 648 #define ARM_SYSST_RSRVD_BIT8    (1 << 8)
 649 #define ARM_SYSST_RSRVD_BIT7    (1 << 7)
 650 #define ARM_SYSST_IDLE_DSP      (1 << 6)
 651 #define ARM_SYSST_POR           (1 << 5)
 652 #define ARM_SYSST_EXT_RST       (1 << 4)
 653 #define ARM_SYSST_ARM_MCRST     (1 << 3)
 654 #define ARM_SYSST_ARM_WDRST     (1 << 2)
 655 #define ARM_SYSST_GLOB_SWRST    (1 << 1)
 656 #define ARM_SYSST_DSP_WDRST     (1 << 0)
 657
 658 /* Table 15-23. DPLL Control Registers: */
 659 #define DPLL_CTL_REG            (volatile __u16 *)(0xfffecf00)
 660
 661 /* Table 15-24. Control Register (CTL_REG): */
 662
 663 #define DPLL_CTL_REG_IOB                (1 << 13)
 664 #define DPLL_CTL_REG_PLL_MULT           Fld(5,0)
 665
 666 /*****************************************************************************/
 667
 668 /* OMAP INTERRUPT REGISTERS */
 669 #define IRQ_ITR                 0x00
 670 #define IRQ_MIR                 0x04
 671 #define IRQ_SIR_IRQ             0x10
 672 #define IRQ_SIR_FIQ             0x14
 673 #define IRQ_CONTROL_REG         0x18
 674 #define IRQ_ISR                 0x9c
 675 #define IRQ_ILR0                0x1c
 676
 677 #define REG_IHL1_MIR  (OMAP_IH1_BASE+IRQ_MIR)
 678 #define REG_IHL2_MIR  (OMAP_IH2_BASE+IRQ_MIR)
 679
 680 /* INTERRUPT LEVEL REGISTER BITS */
 681 #define ILR_PRIORITY_MASK       (0x3c)
 682 #define ILR_PRIORITY_SHIFT      (2)
 683 #define ILR_LEVEL_TRIGGER       (1<<1)
 684 #define ILR_FIQ                 (1<<0)
 685
 686 #define IRQ_LEVEL_INT           1
 687 #define IRQ_EDGE_INT            0