include/configs/omap2420h4.h

   1 /*
   2  * (C) Copyright 2004
   3  * Texas Instruments.
   4  * Richard Woodruff <r-woodruff2@ti.com>
   5  * Kshitij Gupta <kshitij@ti.com>
   6  *
   7  * Configuration settings for the 242x TI H4 board.
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  */
  34 #define CONFIG_ARM1136           1    /* This is an arm1136 CPU core */
  35 #define CONFIG_OMAP              1    /* in a TI OMAP core */
  36 #define CONFIG_OMAP2420          1    /* which is in a 2420 */
  37 #define CONFIG_OMAP2420H4        1    /* and on a H4 board */
  38 //#define CONFIG_APTIX           1    /* define if on APTIX test chip */
  39 //#define CONFIG_VIRTIO          1    /* Using Virtio simulator */
  40
  41 #define PRCM_CONFIG_II           1
  42 #define CONFIG_PARTIAL_SRAM      1
  43
  44 #include <asm/arch/omap2420.h>        /* get chip and board defs */
  45
  46 #ifdef CONFIG_APTIX
  47 #define V_SCLK                   1500000
  48 #else
  49 #define V_SCLK                   12000000
  50 #endif
  51
  52 /* input clock of PLL */
  53 /* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
  54 #define CONFIG_SYS_CLK_FREQ      V_SCLK
  55
  56 #undef CONFIG_USE_IRQ                 /* no support for IRQs */
  57 #define CONFIG_MISC_INIT_R
  58
  59 #define CONFIG_CMDLINE_TAG       1    /* enable passing of ATAGs */
  60 #define CONFIG_SETUP_MEMORY_TAGS 1
  61 #define CONFIG_INITRD_TAG        1
  62
  63 /*
  64  * Size of malloc() pool
  65  */
  66 #define CFG_ENV_SIZE             SZ_128K     /* Total Size of Environment Sector */
  67 #define CFG_MALLOC_LEN           (CFG_ENV_SIZE + SZ_128K)
  68 #define CFG_GBL_DATA_SIZE        128  /* size in bytes reserved for initial data */
  69
  70 /*
  71  * Hardware drivers
  72  */
  73
  74 /*
  75  * SMC91c96 Etherent
  76  */
  77 #define CONFIG_DRIVER_LAN91C96
  78 #define CONFIG_LAN91C96_BASE     (H4_CS1_BASE+0x300)
  79 #define CONFIG_LAN91C96_EXT_PHY
  80
  81 /*
  82  * NS16550 Configuration
  83  */
  84 #ifdef CONFIG_APTIX
  85 #define V_NS16550_CLK            (6000000)   /* 6MHz in current MaxSet */
  86 #else
  87 #define V_NS16550_CLK            (48000000)  /* 48MHz (APLL96/2) */
  88 #endif
  89
  90 #define CFG_NS16550
  91 #define CFG_NS16550_SERIAL
  92 #define CFG_NS16550_REG_SIZE     (-4)
  93 #define CFG_NS16550_CLK          V_NS16550_CLK   /* 3MHz (1.5MHz*2) */
  94 #define CFG_NS16550_COM1         OMAP2420_UART1
  95
  96 /*
  97  * select serial console configuration
  98  */
  99 #define CONFIG_SERIAL1           1    /* UART1 on H4 */
 100
 101   /*
 102    * I2C configuration
 103    */
 104 #define CONFIG_HARD_I2C
 105 #define CFG_I2C_SPEED          100000
 106 #define CFG_I2C_SLAVE          1
 107 #define CONFIG_DRIVER_OMAP24XX_I2C
 108
 109 /* allow to overwrite serial and ethaddr */
 110 #define CONFIG_ENV_OVERWRITE
 111 #define CONFIG_CONS_INDEX        1
 112 #define CONFIG_BAUDRATE          115200
 113 #define CFG_BAUDRATE_TABLE       {9600, 19200, 38400, 57600, 115200}
 114
 115 #define CONFIG_COMMANDS          (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C)
 116
 117 // I'd like to get to these. Snap kernel loads if we make MMC go //
 118   // #define CONFIG_COMMANDS       (CONFIG_CMD_DFL | CFG_CMD_NAND | CFG_CMD_JFFS2 | CFG_CMD_DHCP | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_I2C)
 119
 120 #define CONFIG_BOOTP_MASK        CONFIG_BOOTP_DEFAULT
 121
 122 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 123 #include <cmd_confdefs.h>
 124
 125 #define CONFIG_BOOTDELAY         3
 126
 127 #ifdef NFS_BOOT_DEFAULTS
 128 #define CONFIG_BOOTARGS          "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw nfsroot=128.247.77.158:/home/a0384864/wtbu/rootfs ip=dhcp"
 129 #else
 130 #define CONFIG_BOOTARGS          "root=/dev/ram0 rw mem=32M console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192"
 131 #endif
 132
 133 #define CONFIG_NETMASK           255.255.254.0
 134 #define CONFIG_IPADDR            128.247.77.90
 135 #define CONFIG_SERVERIP          128.247.77.158
 136 #define CONFIG_BOOTFILE          "uImage"
 137
 138 /*
 139  * Miscellaneous configurable options
 140  */
 141 #ifdef CONFIG_APTIX
 142 #define V_PROMPT                 "OMAP2420 Aptix # "
 143 #else
 144 #define V_PROMPT                 "OMAP242x H4 # "
 145 #endif
 146
 147 #define CFG_LONGHELP             /* undef to save memory */
 148 #define CFG_PROMPT               V_PROMPT
 149 #define CFG_CBSIZE               256  /* Console I/O Buffer Size */
 150 /* Print Buffer Size */
 151 #define CFG_PBSIZE               (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
 152 #define CFG_MAXARGS              16          /* max number of command args */
 153 #define CFG_BARGSIZE             CFG_CBSIZE  /* Boot Argument Buffer Size */
 154
 155 #define CFG_MEMTEST_START        (OMAP2420_SDRC_CS0)  /* memtest works on */
 156 #define CFG_MEMTEST_END          (OMAP2420_SDRC_CS0+SZ_31M)
 157
 158 #undef  CFG_CLKS_IN_HZ           /* everything, incl board info, in Hz */
 159
 160 #define CFG_LOAD_ADDR            (OMAP2420_SDRC_CS0) /* default load address */
 161
 162 /* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
 163  * 32KHz clk, or from external sig. This rate is divided by a local divisor.
 164  */
 165 #ifdef CONFIG_APTIX
 166 #define V_PVT                    3
 167 #else
 168 #define V_PVT                    7  /* use with 12MHz/128 */
 169 #endif
 170
 171 #define CFG_TIMERBASE            OMAP2420_GPT2
 172 #define CFG_PVT                  V_PVT  /* 2^(pvt+1) */
 173 #define CFG_HZ                   ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
 174
 175 /*-----------------------------------------------------------------------
 176  * Stack sizes
 177  *
 178  * The stack sizes are set up in start.S using the settings below
 179  */
 180 #define CONFIG_STACKSIZE         SZ_128K /* regular stack */
 181 #ifdef CONFIG_USE_IRQ
 182 #define CONFIG_STACKSIZE_IRQ     SZ_4K   /* IRQ stack */
 183 #define CONFIG_STACKSIZE_FIQ     SZ_4K   /* FIQ stack */
 184 #endif
 185
 186 /*-----------------------------------------------------------------------
 187  * Physical Memory Map
 188  */
 189 #define CONFIG_NR_DRAM_BANKS     2                 /* CS1 may or may not be populated */
 190 #define PHYS_SDRAM_1             OMAP2420_SDRC_CS0
 191 #define PHYS_SDRAM_1_SIZE        SZ_32M            /* at least 32 meg */
 192 #define PHYS_SDRAM_2             OMAP2420_SDRC_CS1
 193
 194 #define PHYS_FLASH_1             H4_CS0_BASE       /* Flash Bank #1 */
 195 #define PHYS_FLASH_SIZE_1        SZ_32M
 196 #define PHYS_FLASH_2             (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */
 197 #define PHYS_FLASH_SIZE_2        SZ_32M
 198 #define CFG_FLASH_BASE           PHYS_FLASH_1
 199
 200 /*-----------------------------------------------------------------------
 201  * FLASH and environment organization
 202  */
 203 #define CFG_MAX_FLASH_BANKS      2           /* max number of memory banks */
 204 #define CFG_MAX_FLASH_SECT       (259)       /* max number of sectors on one chip */
 205
 206 #define CFG_ENV_ADDR             (CFG_FLASH_BASE + SZ_128K)
 207 #define CFG_ENV_IS_IN_FLASH      1
 208
 209 /* timeout values are in ticks */
 210 #define CFG_FLASH_ERASE_TOUT     (10*75*CFG_HZ) /* Timeout for Flash Erase */
 211 #define CFG_FLASH_WRITE_TOUT     (10*75*CFG_HZ) /* Timeout for Flash Write */
 212
 213 #endif                                                  /* __CONFIG_H */