include/configs/omap3_cairo.h

   1 /*
   2  * Configuration settings for the QUIPOS Cairo board.
   3  *
   4  * Copyright (C) DENX GmbH
   5  *
   6  * Author :
   7  *      Albert ARIBAUD <albert.aribaud@3adev.fr>
   8  *
   9  * Derived from EVM  code by
  10  *      Manikandan Pillai <mani.pillai@ti.com>
  11  * Itself derived from Beagle Board and 3430 SDP code by
  12  *      Richard Woodruff <r-woodruff2@ti.com>
  13  *      Syed Mohammed Khasim <khasim@ti.com>
  14  *
  15  * Also derived from include/configs/omap3_beagle.h
  16  *
  17  * SPDX-License-Identifier:     GPL-2.0+
  18  */
  19
  20 #ifndef __OMAP3_CAIRO_CONFIG_H
  21 #define __OMAP3_CAIRO_CONFIG_H
  22
  23 #define CONFIG_NR_DRAM_BANKS    2       /* CS1 may or may not be populated */
  24
  25 /*
  26  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
  27  * 64 bytes before this address should be set aside for u-boot.img's
  28  * header. That is 0x800FFFC0--0x80100000 should not be used for any
  29  * other needs.  We use this rather than the inherited defines from
  30  * ti_armv7_common.h for backwards compatibility.
  31  */
  32 #define CONFIG_SYS_TEXT_BASE            0x80100000
  33 #define CONFIG_SYS_UBOOT_START          CONFIG_SYS_TEXT_BASE
  34 #define CONFIG_SPL_BSS_START_ADDR       0x80000000
  35 #define CONFIG_SPL_BSS_MAX_SIZE         (512 << 10)     /* 512 KB */
  36 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
  37 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  38
  39 #define CONFIG_NAND
  40
  41 #include <configs/ti_omap3_common.h>
  42
  43 /*
  44  * Display CPU and Board information
  45  */
  46 #define CONFIG_DISPLAY_CPUINFO          1
  47 #define CONFIG_DISPLAY_BOARDINFO        1
  48
  49 #define CONFIG_MISC_INIT_R
  50
  51 #define CONFIG_REVISION_TAG             1
  52 #define CONFIG_ENV_OVERWRITE
  53
  54 /* Enable Multi Bus support for I2C */
  55 #define CONFIG_I2C_MULTI_BUS            1
  56
  57 /* Probe all devices */
  58 #define CONFIG_SYS_I2C_NOPROBES         { {0x0, 0x0} }
  59
  60 #define CONFIG_NAND
  61
  62 /* commands to include */
  63 #include <config_cmd_default.h>
  64
  65 #define CONFIG_CMD_NAND_LOCK_UNLOCK
  66
  67 /* Disable some commands */
  68 #undef CONFIG_CMD_FPGA          /* FPGA configuration Support   */
  69 #undef CONFIG_CMD_IMI           /* iminfo                       */
  70
  71 /*
  72  * TWL4030
  73  */
  74 #define CONFIG_TWL4030_LED              1
  75
  76 /*
  77  * Board NAND Info.
  78  */
  79 #define CONFIG_SYS_NAND_QUIET_TEST      1
  80 #define CONFIG_NAND_OMAP_GPMC
  81 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
  82                                                         /* devices */
  83 /* override default CONFIG_BOOTDELAY */
  84 #undef CONFIG_BOOTDELAY
  85 #define CONFIG_BOOTDELAY        0
  86
  87 #define CONFIG_EXTRA_ENV_SETTINGS \
  88         "machid=ffffffff\0" \
  89         "fdt_high=0x87000000\0" \
  90         "baudrate=115200\0" \
  91         "fec_addr=00:50:C2:7E:90:F0\0" \
  92         "netmask=255.255.255.0\0" \
  93         "ipaddr=192.168.2.9\0" \
  94         "gateway=192.168.2.1\0" \
  95         "serverip=192.168.2.10\0" \
  96         "nfshost=192.168.2.10\0" \
  97         "stdin=serial\0" \
  98         "stdout=serial\0" \
  99         "stderr=serial\0" \
 100         "bootargs_mmc_ramdisk=mem=128M " \
 101                 "console=ttyO1,115200n8 " \
 102                 "root=/dev/ram0 rw " \
 103                 "initrd=0x81600000,16M " \
 104                 "mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \
 105                 "omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \
 106         "mmcboot=mmc init; " \
 107                 "fatload mmc 0 0x80000000 uImage; " \
 108                 "fatload mmc 0 0x81600000 ramdisk.gz; " \
 109                 "setenv bootargs ${bootargs_mmc_ramdisk}; " \
 110                 "bootm 0x80000000\0" \
 111         "bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \
 112         "root=/dev/nfs " \
 113         "nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \
 114         "mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \
 115         "omap_vout.vid1_static_vrfb_alloc=y\0" \
 116         "boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \
 117         "bootm 0x80000000\0" \
 118         "bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \
 119         "root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \
 120         "omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \
 121         "omapfb.rotate_type=1\0" \
 122         "boot_nand=nand read.i 0x80000000 280000 300000; setenv " \
 123         "bootargs ${bootargs_nand}; bootm 0x80000000\0" \
 124         "ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
 125         "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
 126         "i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \
 127         "ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
 128         "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \
 129         "mw 60 09 00 1; i2c mw 60 06 10 1\0" \
 130         "ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
 131         "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
 132         "i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \
 133         "ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
 134         "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
 135         "i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \
 136         "flash_xloader=mw.b 0x81600000 0xff 0x20000; " \
 137                 "nand erase 0 20000; " \
 138                 "fatload mmc 0 0x81600000 MLO; " \
 139                 "nandecc hw; " \
 140                 "nand write.i 0x81600000 0 20000;\0" \
 141         "flash_uboot=mw.b 0x81600000 0xff 0x40000; " \
 142                 "nand erase 80000 40000; " \
 143                 "fatload mmc 0 0x81600000 u-boot.bin; " \
 144                 "nandecc sw; " \
 145                 "nand write.i 0x81600000 80000 40000;\0" \
 146         "flash_kernel=mw.b 0x81600000 0xff 0x300000; " \
 147                 "nand erase 280000 300000; " \
 148                 "fatload mmc 0 0x81600000 uImage; " \
 149                 "nandecc sw; " \
 150                 "nand write.i 0x81600000 280000 300000;\0" \
 151         "flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \
 152                 "nandecc sw; " \
 153                 "nand write.jffs2 0x680000 0xFF ${filesize}; " \
 154                 "nand erase 680000 ${filesize}; " \
 155                 "nand write.jffs2 81600000 680000 ${filesize};\0" \
 156         "flash_scrub=nand scrub; " \
 157                 "run flash_xloader; " \
 158                 "run flash_uboot; " \
 159                 "run flash_kernel; " \
 160                 "run flash_rootfs;\0" \
 161         "flash_all=run ledred; " \
 162                 "nand erase.chip; " \
 163                 "run ledorange; " \
 164                 "run flash_xloader; " \
 165                 "run flash_uboot; " \
 166                 "run flash_kernel; " \
 167                 "run flash_rootfs; " \
 168                 "run ledgreen; " \
 169                 "run boot_nand; \0" \
 170
 171 #define CONFIG_BOOTCOMMAND \
 172         "if fatload mmc 0 0x81600000 MLO; then run flash_all; " \
 173         "else run boot_nand; fi"
 174
 175 /*
 176  * OMAP3 has 12 GP timers, they can be driven by the system clock
 177  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 178  * This rate is divided by a local divisor.
 179  */
 180 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 181
 182 /*-----------------------------------------------------------------------
 183  * FLASH and environment organization
 184  */
 185
 186 /* **** PISMO SUPPORT *** */
 187 #if defined(CONFIG_CMD_NAND)
 188 #define CONFIG_SYS_FLASH_BASE           NAND_BASE
 189 #endif
 190
 191 /* Monitor at start of flash */
 192 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 193 #define CONFIG_SYS_ONENAND_BASE         ONENAND_MAP
 194
 195 #define CONFIG_ENV_IS_IN_NAND           1
 196 #define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB */
 197 #define ONENAND_ENV_OFFSET              0x260000 /* environment starts here */
 198 #define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
 199
 200 #define CONFIG_SYS_ENV_SECT_SIZE        (128 << 10)     /* 128 KiB */
 201 #define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
 202 #define CONFIG_ENV_ADDR                 SMNAND_ENV_OFFSET
 203
 204 #define CONFIG_OMAP3_SPI
 205
 206 #define CONFIG_SYS_CACHELINE_SIZE       64
 207
 208 /* Defines for SPL */
 209 #define CONFIG_SPL_OMAP3_ID_NAND
 210
 211 /* NAND boot config */
 212 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 213 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 214 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 215 #define CONFIG_SYS_NAND_OOBSIZE         64
 216 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128*1024)
 217 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 218 #define CONFIG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9,\
 219                                                 10, 11, 12, 13}
 220 #define CONFIG_SYS_NAND_ECCSIZE         512
 221 #define CONFIG_SYS_NAND_ECCBYTES        3
 222 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
 223 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 224 /* NAND: SPL falcon mode configs */
 225 #ifdef CONFIG_SPL_OS_BOOT
 226 #define CONFIG_CMD_SPL_NAND_OFS         0x240000
 227 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
 228 #define CONFIG_CMD_SPL_WRITE_SIZE       0x2000
 229 #endif
 230
 231 /* env defaults */
 232 #define CONFIG_BOOTFILE                 "uImage"
 233
 234 /* Override OMAP3 common serial console configuration from UART3
 235  * to UART2.
 236  *
 237  * Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3)
 238  * are needed and peripheral clocks for UART2 must be enabled in
 239  * function per_clocks_enable().
 240  */
 241 #undef CONFIG_CONS_INDEX
 242 #define CONFIG_CONS_INDEX               2
 243 #ifdef CONFIG_SPL_BUILD
 244 #undef CONFIG_SYS_NS16550_COM3
 245 #define CONFIG_SYS_NS16550_COM2         OMAP34XX_UART2
 246 #undef CONFIG_SERIAL3
 247 #define CONFIG_SERIAL2
 248 #endif
 249
 250 /* Keep old prompt in case some existing script depends on it */
 251 #undef CONFIG_SYS_PROMPT
 252 #define CONFIG_SYS_PROMPT               "Cairo # "
 253
 254 /* Provide MACH_TYPE for compatibility with non-DT kernels */
 255 #define MACH_TYPE_OMAP3_CAIRO   3063
 256 #define CONFIG_MACH_TYPE        MACH_TYPE_OMAP3_CAIRO
 257
 258 /*-----------------------------------------------------------------------
 259  * FLASH and environment organization
 260  */
 261
 262 /* **** PISMO SUPPORT *** */
 263
 264 #define CONFIG_SYS_MAX_FLASH_SECT       520     /* max number of sectors */
 265                                                 /* on one chip */
 266 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of flash banks */
 267
 268 /*-----------------------------------------------------------------------
 269  * CFI FLASH driver setup
 270  */
 271 /* timeout values are in ticks */
 272 #define CONFIG_SYS_FLASH_ERASE_TOUT     (100 * CONFIG_SYS_HZ)
 273 #define CONFIG_SYS_FLASH_WRITE_TOUT     (100 * CONFIG_SYS_HZ)
 274
 275 /* Flash banks JFFS2 should use */
 276 #define CONFIG_SYS_MAX_MTD_BANKS        (CONFIG_SYS_MAX_FLASH_BANKS + \
 277                                         CONFIG_SYS_MAX_NAND_DEVICE)
 278 #define CONFIG_SYS_JFFS2_MEM_NAND
 279 /* use flash_info[2] */
 280 #define CONFIG_SYS_JFFS2_FIRST_BANK     CONFIG_SYS_MAX_FLASH_BANKS
 281 #define CONFIG_SYS_JFFS2_NUM_BANKS      1
 282
 283 #endif /* __OMAP3_CAIRO_CONFIG_H */