include/configs/p1_p2_rdb_pc.h

   1 /*
   2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * QorIQ RDB boards configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #if defined(CONFIG_P1020MBG)
  14 #define CONFIG_BOARDNAME "P1020MBG-PC"
  15 #define CONFIG_P1020
  16 #define CONFIG_VSC7385_ENET
  17 #define CONFIG_SLIC
  18 #define __SW_BOOT_MASK          0x03
  19 #define __SW_BOOT_NOR           0xe4
  20 #define __SW_BOOT_SD            0x54
  21 #define CONFIG_SYS_L2_SIZE      (256 << 10)
  22 #endif
  23
  24 #if defined(CONFIG_P1020UTM)
  25 #define CONFIG_BOARDNAME "P1020UTM-PC"
  26 #define CONFIG_P1020
  27 #define __SW_BOOT_MASK          0x03
  28 #define __SW_BOOT_NOR           0xe0
  29 #define __SW_BOOT_SD            0x50
  30 #define CONFIG_SYS_L2_SIZE      (256 << 10)
  31 #endif
  32
  33 #if defined(CONFIG_P1020RDB_PC)
  34 #define CONFIG_BOARDNAME "P1020RDB-PC"
  35 #define CONFIG_NAND_FSL_ELBC
  36 #define CONFIG_P1020
  37 #define CONFIG_VSC7385_ENET
  38 #define CONFIG_SLIC
  39 #define __SW_BOOT_MASK          0x03
  40 #define __SW_BOOT_NOR           0x5c
  41 #define __SW_BOOT_SPI           0x1c
  42 #define __SW_BOOT_SD            0x9c
  43 #define __SW_BOOT_NAND          0xec
  44 #define __SW_BOOT_PCIE          0x6c
  45 #define CONFIG_SYS_L2_SIZE      (256 << 10)
  46 #endif
  47
  48 /*
  49  * P1020RDB-PD board has user selectable switches for evaluating different
  50  * frequency and boot options for the P1020 device. The table that
  51  * follow describe the available options. The front six binary number was in
  52  * accordance with SW3[1:6].
  53  * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
  54  * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
  55  * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
  56  * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
  57  * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
  58  * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
  59  * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
  60  */
  61 #if defined(CONFIG_P1020RDB_PD)
  62 #define CONFIG_BOARDNAME "P1020RDB-PD"
  63 #define CONFIG_NAND_FSL_ELBC
  64 #define CONFIG_P1020
  65 #define CONFIG_VSC7385_ENET
  66 #define CONFIG_SLIC
  67 #define __SW_BOOT_MASK          0x03
  68 #define __SW_BOOT_NOR           0x64
  69 #define __SW_BOOT_SPI           0x34
  70 #define __SW_BOOT_SD            0x24
  71 #define __SW_BOOT_NAND          0x44
  72 #define __SW_BOOT_PCIE          0x74
  73 #define CONFIG_SYS_L2_SIZE      (256 << 10)
  74 /*
  75  * Dynamic MTD Partition support with mtdparts
  76  */
  77 #define CONFIG_MTD_DEVICE
  78 #define CONFIG_MTD_PARTITIONS
  79 #define CONFIG_CMD_MTDPARTS
  80 #define CONFIG_FLASH_CFI_MTD
  81 #define MTDIDS_DEFAULT "nor0=ec000000.nor"
  82 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \
  83                         "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
  84 #endif
  85
  86 #if defined(CONFIG_P1021RDB)
  87 #define CONFIG_BOARDNAME "P1021RDB-PC"
  88 #define CONFIG_NAND_FSL_ELBC
  89 #define CONFIG_P1021
  90 #define CONFIG_QE
  91 #define CONFIG_VSC7385_ENET
  92 #define CONFIG_SYS_LBC_LBCR     0x00080000      /* Implement conversion of
  93                                                 addresses in the LBC */
  94 #define __SW_BOOT_MASK          0x03
  95 #define __SW_BOOT_NOR           0x5c
  96 #define __SW_BOOT_SPI           0x1c
  97 #define __SW_BOOT_SD            0x9c
  98 #define __SW_BOOT_NAND          0xec
  99 #define __SW_BOOT_PCIE          0x6c
 100 #define CONFIG_SYS_L2_SIZE      (256 << 10)
 101 /*
 102  * Dynamic MTD Partition support with mtdparts
 103  */
 104 #define CONFIG_MTD_DEVICE
 105 #define CONFIG_MTD_PARTITIONS
 106 #define CONFIG_CMD_MTDPARTS
 107 #define CONFIG_FLASH_CFI_MTD
 108 #ifdef CONFIG_PHYS_64BIT
 109 #define MTDIDS_DEFAULT "nor0=fef000000.nor"
 110 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \
 111                         "256k(dtb),4608k(kernel),9728k(fs)," \
 112                         "256k(qe-ucode-firmware),1280k(u-boot)"
 113 #else
 114 #define MTDIDS_DEFAULT "nor0=ef000000.nor"
 115 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \
 116                         "256k(dtb),4608k(kernel),9728k(fs)," \
 117                         "256k(qe-ucode-firmware),1280k(u-boot)"
 118 #endif
 119 #endif
 120
 121 #if defined(CONFIG_P1024RDB)
 122 #define CONFIG_BOARDNAME "P1024RDB"
 123 #define CONFIG_NAND_FSL_ELBC
 124 #define CONFIG_P1024
 125 #define CONFIG_SLIC
 126 #define __SW_BOOT_MASK          0xf3
 127 #define __SW_BOOT_NOR           0x00
 128 #define __SW_BOOT_SPI           0x08
 129 #define __SW_BOOT_SD            0x04
 130 #define __SW_BOOT_NAND          0x0c
 131 #define CONFIG_SYS_L2_SIZE      (256 << 10)
 132 #endif
 133
 134 #if defined(CONFIG_P1025RDB)
 135 #define CONFIG_BOARDNAME "P1025RDB"
 136 #define CONFIG_NAND_FSL_ELBC
 137 #define CONFIG_P1025
 138 #define CONFIG_QE
 139 #define CONFIG_SLIC
 140
 141 #define CONFIG_SYS_LBC_LBCR     0x00080000      /* Implement conversion of
 142                                                 addresses in the LBC */
 143 #define __SW_BOOT_MASK          0xf3
 144 #define __SW_BOOT_NOR           0x00
 145 #define __SW_BOOT_SPI           0x08
 146 #define __SW_BOOT_SD            0x04
 147 #define __SW_BOOT_NAND          0x0c
 148 #define CONFIG_SYS_L2_SIZE      (256 << 10)
 149 #endif
 150
 151 #if defined(CONFIG_P2020RDB)
 152 #define CONFIG_BOARDNAME "P2020RDB-PCA"
 153 #define CONFIG_NAND_FSL_ELBC
 154 #define CONFIG_P2020
 155 #define CONFIG_VSC7385_ENET
 156 #define __SW_BOOT_MASK          0x03
 157 #define __SW_BOOT_NOR           0xc8
 158 #define __SW_BOOT_SPI           0x28
 159 #define __SW_BOOT_SD            0x68 /* or 0x18 */
 160 #define __SW_BOOT_NAND          0xe8
 161 #define __SW_BOOT_PCIE          0xa8
 162 #define CONFIG_SYS_L2_SIZE      (512 << 10)
 163 /*
 164  * Dynamic MTD Partition support with mtdparts
 165  */
 166 #define CONFIG_MTD_DEVICE
 167 #define CONFIG_MTD_PARTITIONS
 168 #define CONFIG_CMD_MTDPARTS
 169 #define CONFIG_FLASH_CFI_MTD
 170 #ifdef CONFIG_PHYS_64BIT
 171 #define MTDIDS_DEFAULT "nor0=fef000000.nor"
 172 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \
 173                         "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
 174 #else
 175 #define MTDIDS_DEFAULT "nor0=ef000000.nor"
 176 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \
 177                         "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
 178 #endif
 179 #endif
 180
 181 #ifdef CONFIG_SDCARD
 182 #define CONFIG_SPL_MMC_MINIMAL
 183 #define CONFIG_SPL_FLUSH_IMAGE
 184 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
 185 #define CONFIG_FSL_LAW                 /* Use common FSL init code */
 186 #define CONFIG_SYS_TEXT_BASE            0x11001000
 187 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
 188 #define CONFIG_SPL_PAD_TO               0x20000
 189 #define CONFIG_SPL_MAX_SIZE             (128 * 1024)
 190 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
 191 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
 192 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
 193 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (128 << 10)
 194 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 195 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
 196 #define CONFIG_SPL_MMC_BOOT
 197 #ifdef CONFIG_SPL_BUILD
 198 #define CONFIG_SPL_COMMON_INIT_DDR
 199 #endif
 200 #endif
 201
 202 #ifdef CONFIG_SPIFLASH
 203 #define CONFIG_SPL_SPI_FLASH_MINIMAL
 204 #define CONFIG_SPL_FLUSH_IMAGE
 205 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
 206 #define CONFIG_FSL_LAW         /* Use common FSL init code */
 207 #define CONFIG_SYS_TEXT_BASE            0x11001000
 208 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
 209 #define CONFIG_SPL_PAD_TO               0x20000
 210 #define CONFIG_SPL_MAX_SIZE             (128 * 1024)
 211 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
 212 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
 213 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
 214 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (128 << 10)
 215 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 216 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
 217 #define CONFIG_SPL_SPI_BOOT
 218 #ifdef CONFIG_SPL_BUILD
 219 #define CONFIG_SPL_COMMON_INIT_DDR
 220 #endif
 221 #endif
 222
 223 #ifdef CONFIG_NAND
 224 #ifdef CONFIG_TPL_BUILD
 225 #define CONFIG_SPL_NAND_BOOT
 226 #define CONFIG_SPL_FLUSH_IMAGE
 227 #define CONFIG_SPL_NAND_INIT
 228 #define CONFIG_SPL_COMMON_INIT_DDR
 229 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
 230 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
 231 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 232 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (832 << 10)
 233 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
 234 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
 235 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
 236 #elif defined(CONFIG_SPL_BUILD)
 237 #define CONFIG_SPL_INIT_MINIMAL
 238 #define CONFIG_SPL_FLUSH_IMAGE
 239 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
 240 #define CONFIG_SPL_TEXT_BASE            0xff800000
 241 #define CONFIG_SPL_MAX_SIZE             4096
 242 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
 243 #define CONFIG_SYS_NAND_U_BOOT_DST      0xf8f80000
 244 #define CONFIG_SYS_NAND_U_BOOT_START    0xf8f80000
 245 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
 246 #endif /* not CONFIG_TPL_BUILD */
 247
 248 #define CONFIG_SPL_PAD_TO               0x20000
 249 #define CONFIG_TPL_PAD_TO               0x20000
 250 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
 251 #define CONFIG_SYS_TEXT_BASE            0x11001000
 252 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 253 #endif
 254
 255 #ifndef CONFIG_SYS_TEXT_BASE
 256 #define CONFIG_SYS_TEXT_BASE            0xeff40000
 257 #endif
 258
 259 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 260 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 261 #endif
 262
 263 #ifndef CONFIG_SYS_MONITOR_BASE
 264 #ifdef CONFIG_SPL_BUILD
 265 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 266 #else
 267 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 268 #endif
 269 #endif
 270
 271 /* High Level Configuration Options */
 272 #define CONFIG_BOOKE
 273 #define CONFIG_E500
 274
 275 #define CONFIG_MP
 276
 277 #define CONFIG_FSL_ELBC
 278 #define CONFIG_PCIE1    /* PCIE controller 1 (slot 1) */
 279 #define CONFIG_PCIE2    /* PCIE controller 2 (slot 2) */
 280 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 281 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 282 #define CONFIG_FSL_PCIE_RESET   /* need PCIe reset errata */
 283 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 284
 285 #define CONFIG_FSL_LAW
 286 #define CONFIG_TSEC_ENET        /* tsec ethernet support */
 287 #define CONFIG_ENV_OVERWRITE
 288
 289 #define CONFIG_CMD_SATA
 290 #define CONFIG_SATA_SIL
 291 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 292 #define CONFIG_LIBATA
 293 #define CONFIG_LBA48
 294
 295 #if defined(CONFIG_P2020RDB)
 296 #define CONFIG_SYS_CLK_FREQ     100000000
 297 #else
 298 #define CONFIG_SYS_CLK_FREQ     66666666
 299 #endif
 300 #define CONFIG_DDR_CLK_FREQ     66666666
 301
 302 #define CONFIG_HWCONFIG
 303 /*
 304  * These can be toggled for performance analysis, otherwise use default.
 305  */
 306 #define CONFIG_L2_CACHE
 307 #define CONFIG_BTB
 308
 309 #define CONFIG_BOARD_EARLY_INIT_F       /* Call board_pre_init */
 310
 311 #define CONFIG_ENABLE_36BIT_PHYS
 312
 313 #ifdef CONFIG_PHYS_64BIT
 314 #define CONFIG_ADDR_MAP                 1
 315 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
 316 #endif
 317
 318 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 319 #define CONFIG_SYS_MEMTEST_END          0x1fffffff
 320 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 321
 322 #define CONFIG_SYS_CCSRBAR              0xffe00000
 323 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 324
 325 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
 326        SPL code*/
 327 #ifdef CONFIG_SPL_BUILD
 328 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 329 #endif
 330
 331 /* DDR Setup */
 332 #define CONFIG_SYS_FSL_DDR3
 333 #define CONFIG_SYS_DDR_RAW_TIMING
 334 #define CONFIG_DDR_SPD
 335 #define CONFIG_SYS_SPD_BUS_NUM 1
 336 #define SPD_EEPROM_ADDRESS 0x52
 337 #undef CONFIG_FSL_DDR_INTERACTIVE
 338
 339 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
 340 #define CONFIG_SYS_SDRAM_SIZE_LAW       LAW_SIZE_2G
 341 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 342 #else
 343 #define CONFIG_SYS_SDRAM_SIZE_LAW       LAW_SIZE_1G
 344 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 345 #endif
 346 #define CONFIG_SYS_SDRAM_SIZE           (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
 347 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 348 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 349
 350 #define CONFIG_NUM_DDR_CONTROLLERS      1
 351 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 352
 353 /* Default settings for DDR3 */
 354 #ifndef CONFIG_P2020RDB
 355 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
 356 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
 357 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
 358 #define CONFIG_SYS_DDR_CS1_BNDS         0x0040007f
 359 #define CONFIG_SYS_DDR_CS1_CONFIG       0x80014302
 360 #define CONFIG_SYS_DDR_CS1_CONFIG_2     0x00000000
 361
 362 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 363 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
 364 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
 365 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
 366
 367 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 368 #define CONFIG_SYS_DDR_WRLVL_CONTROL    0x8655A608
 369 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
 370 #define CONFIG_SYS_DDR_RCW_1            0x00000000
 371 #define CONFIG_SYS_DDR_RCW_2            0x00000000
 372 #define CONFIG_SYS_DDR_CONTROL          0xC70C0000      /* Type = DDR3  */
 373 #define CONFIG_SYS_DDR_CONTROL_2        0x04401050
 374 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
 375 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 376
 377 #define CONFIG_SYS_DDR_TIMING_3         0x00020000
 378 #define CONFIG_SYS_DDR_TIMING_0         0x00330004
 379 #define CONFIG_SYS_DDR_TIMING_1         0x6f6B4846
 380 #define CONFIG_SYS_DDR_TIMING_2         0x0FA8C8CF
 381 #define CONFIG_SYS_DDR_CLK_CTRL         0x03000000
 382 #define CONFIG_SYS_DDR_MODE_1           0x40461520
 383 #define CONFIG_SYS_DDR_MODE_2           0x8000c000
 384 #define CONFIG_SYS_DDR_INTERVAL         0x0C300000
 385 #endif
 386
 387 #undef CONFIG_CLOCKS_IN_MHZ
 388
 389 /*
 390  * Memory map
 391  *
 392  * 0x0000_0000 0x7fff_ffff      DDR             Up to 2GB cacheable
 393  * 0x8000_0000 0xdfff_ffff      PCI Express Mem 1.5G non-cacheable(PCIe * 3)
 394  * 0xec00_0000 0xefff_ffff      NOR flash       Up to 64M non-cacheable CS0/1
 395  * 0xf8f8_0000 0xf8ff_ffff      L2 SRAM         Up to 512K cacheable
 396  *   (early boot only)
 397  * 0xff80_0000 0xff80_7fff      NAND flash      32K non-cacheable       CS1/0
 398  * 0xff98_0000 0xff98_ffff      PMC             64K non-cacheable       CS2
 399  * 0xffa0_0000 0xffaf_ffff      CPLD            1M non-cacheable        CS3
 400  * 0xffb0_0000 0xffbf_ffff      VSC7385 switch  1M non-cacheable        CS2
 401  * 0xffc0_0000 0xffc3_ffff      PCI IO range    256k non-cacheable
 402  * 0xffd0_0000 0xffd0_3fff      L1 for stack    16K cacheable
 403  * 0xffe0_0000 0xffef_ffff      CCSR            1M non-cacheable
 404  */
 405
 406 /*
 407  * Local Bus Definitions
 408  */
 409 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
 410 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* 64M */
 411 #define CONFIG_SYS_FLASH_BASE           0xec000000
 412 #elif defined(CONFIG_P1020UTM)
 413 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* 32M */
 414 #define CONFIG_SYS_FLASH_BASE           0xee000000
 415 #else
 416 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* 16M */
 417 #define CONFIG_SYS_FLASH_BASE           0xef000000
 418 #endif
 419
 420 #ifdef CONFIG_PHYS_64BIT
 421 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 422 #else
 423 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 424 #endif
 425
 426 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 427         | BR_PS_16 | BR_V)
 428
 429 #define CONFIG_FLASH_OR_PRELIM  0xfc000ff7
 430
 431 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 432 #define CONFIG_SYS_FLASH_QUIET_TEST
 433 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 434
 435 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 436
 437 #undef CONFIG_SYS_FLASH_CHECKSUM
 438 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 439 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 440
 441 #define CONFIG_FLASH_CFI_DRIVER
 442 #define CONFIG_SYS_FLASH_CFI
 443 #define CONFIG_SYS_FLASH_EMPTY_INFO
 444 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 445
 446 /* Nand Flash */
 447 #ifdef CONFIG_NAND_FSL_ELBC
 448 #define CONFIG_SYS_NAND_BASE            0xff800000
 449 #ifdef CONFIG_PHYS_64BIT
 450 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 451 #else
 452 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 453 #endif
 454
 455 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 456 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 457 #define CONFIG_CMD_NAND
 458 #if defined(CONFIG_P1020RDB_PD)
 459 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 460 #else
 461 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 * 1024)
 462 #endif
 463
 464 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 465         | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 466         | BR_PS_8       /* Port Size = 8 bit */ \
 467         | BR_MS_FCM     /* MSEL = FCM */ \
 468         | BR_V) /* valid */
 469 #if defined(CONFIG_P1020RDB_PD)
 470 #define CONFIG_SYS_NAND_OR_PRELIM       (OR_AM_32KB \
 471         | OR_FCM_PGS    /* Large Page*/ \
 472         | OR_FCM_CSCT \
 473         | OR_FCM_CST \
 474         | OR_FCM_CHT \
 475         | OR_FCM_SCY_1 \
 476         | OR_FCM_TRLX \
 477         | OR_FCM_EHTR)
 478 #else
 479 #define CONFIG_SYS_NAND_OR_PRELIM       (OR_AM_32KB     /* small page */ \
 480         | OR_FCM_CSCT \
 481         | OR_FCM_CST \
 482         | OR_FCM_CHT \
 483         | OR_FCM_SCY_1 \
 484         | OR_FCM_TRLX \
 485         | OR_FCM_EHTR)
 486 #endif
 487 #endif /* CONFIG_NAND_FSL_ELBC */
 488
 489 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 490
 491 #define CONFIG_SYS_INIT_RAM_LOCK
 492 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* stack in RAM */
 493 #ifdef CONFIG_PHYS_64BIT
 494 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 495 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 496 /* The assembler doesn't like typecast */
 497 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 498         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 499           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 500 #else
 501 /* Initial L1 address */
 502 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 503 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 504 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 505 #endif
 506 /* Size of used area in RAM */
 507 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 508
 509 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 510                                         GENERATED_GBL_DATA_SIZE)
 511 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 512
 513 #define CONFIG_SYS_MONITOR_LEN  (768 * 1024)
 514 #define CONFIG_SYS_MALLOC_LEN   (1024 * 1024)/* Reserved for malloc */
 515
 516 #define CONFIG_SYS_CPLD_BASE    0xffa00000
 517 #ifdef CONFIG_PHYS_64BIT
 518 #define CONFIG_SYS_CPLD_BASE_PHYS       0xfffa00000ull
 519 #else
 520 #define CONFIG_SYS_CPLD_BASE_PHYS       CONFIG_SYS_CPLD_BASE
 521 #endif
 522 /* CPLD config size: 1Mb */
 523 #define CONFIG_CPLD_BR_PRELIM   (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
 524                                         BR_PS_8 | BR_V)
 525 #define CONFIG_CPLD_OR_PRELIM   (0xfff009f7)
 526
 527 #define CONFIG_SYS_PMC_BASE     0xff980000
 528 #define CONFIG_SYS_PMC_BASE_PHYS        CONFIG_SYS_PMC_BASE
 529 #define CONFIG_PMC_BR_PRELIM    (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
 530                                         BR_PS_8 | BR_V)
 531 #define CONFIG_PMC_OR_PRELIM    (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
 532                                  OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
 533                                  OR_GPCM_EAD)
 534
 535 #ifdef CONFIG_NAND
 536 #define CONFIG_SYS_BR0_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
 537 #define CONFIG_SYS_OR0_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 538 #define CONFIG_SYS_BR1_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 539 #define CONFIG_SYS_OR1_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 540 #else
 541 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 542 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 543 #ifdef CONFIG_NAND_FSL_ELBC
 544 #define CONFIG_SYS_BR1_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
 545 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 546 #endif
 547 #endif
 548 #define CONFIG_SYS_BR3_PRELIM   CONFIG_CPLD_BR_PRELIM   /* CPLD Base Address */
 549 #define CONFIG_SYS_OR3_PRELIM   CONFIG_CPLD_OR_PRELIM   /* CPLD Options */
 550
 551 /* Vsc7385 switch */
 552 #ifdef CONFIG_VSC7385_ENET
 553 #define CONFIG_SYS_VSC7385_BASE         0xffb00000
 554
 555 #ifdef CONFIG_PHYS_64BIT
 556 #define CONFIG_SYS_VSC7385_BASE_PHYS    0xfffb00000ull
 557 #else
 558 #define CONFIG_SYS_VSC7385_BASE_PHYS    CONFIG_SYS_VSC7385_BASE
 559 #endif
 560
 561 #define CONFIG_SYS_VSC7385_BR_PRELIM    \
 562         (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
 563 #define CONFIG_SYS_VSC7385_OR_PRELIM    (OR_AM_128KB | OR_GPCM_CSNT | \
 564                         OR_GPCM_XACS |  OR_GPCM_SCY_15 | OR_GPCM_SETA | \
 565                         OR_GPCM_TRLX |  OR_GPCM_EHTR | OR_GPCM_EAD)
 566
 567 #define CONFIG_SYS_BR2_PRELIM   CONFIG_SYS_VSC7385_BR_PRELIM
 568 #define CONFIG_SYS_OR2_PRELIM   CONFIG_SYS_VSC7385_OR_PRELIM
 569
 570 /* The size of the VSC7385 firmware image */
 571 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 572 #endif
 573
 574 /*
 575  * Config the L2 Cache as L2 SRAM
 576 */
 577 #if defined(CONFIG_SPL_BUILD)
 578 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 579 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 580 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 581 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 582 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 583 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 584 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
 585 #define CONFIG_SPL_RELOC_STACK_SIZE     (32 << 10)
 586 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
 587 #if defined(CONFIG_P2020RDB)
 588 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (364 << 10)
 589 #else
 590 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (108 << 10)
 591 #endif
 592 #elif defined(CONFIG_NAND)
 593 #ifdef CONFIG_TPL_BUILD
 594 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 595 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 596 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 597 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 598 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 599 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 600 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
 601 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 602 #else
 603 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 604 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 605 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 606 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x2000)
 607 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 608 #endif /* CONFIG_TPL_BUILD */
 609 #endif
 610 #endif
 611
 612 /* Serial Port - controlled on board with jumper J8
 613  * open - index 2
 614  * shorted - index 1
 615  */
 616 #define CONFIG_CONS_INDEX               1
 617 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 618 #define CONFIG_SYS_NS16550_SERIAL
 619 #define CONFIG_SYS_NS16550_REG_SIZE     1
 620 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 621 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 622 #define CONFIG_NS16550_MIN_FUNCTIONS
 623 #endif
 624
 625 #define CONFIG_SYS_BAUDRATE_TABLE       \
 626         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 627
 628 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 629 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 630
 631 /* I2C */
 632 #define CONFIG_SYS_I2C
 633 #define CONFIG_SYS_I2C_FSL
 634 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 635 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 636 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 637 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 638 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 639 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 640 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x29} }
 641 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52
 642 #define CONFIG_SYS_SPD_BUS_NUM          1 /* For rom_loc and flash bank */
 643
 644 /*
 645  * I2C2 EEPROM
 646  */
 647 #undef CONFIG_ID_EEPROM
 648
 649 #define CONFIG_RTC_PT7C4338
 650 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 651 #define CONFIG_SYS_I2C_PCA9557_ADDR     0x18
 652
 653 /* enable read and write access to EEPROM */
 654 #define CONFIG_CMD_EEPROM
 655 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 656 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 657 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 658
 659 /*
 660  * eSPI - Enhanced SPI
 661  */
 662 #define CONFIG_HARD_SPI
 663
 664 #if defined(CONFIG_SPI_FLASH)
 665 #define CONFIG_SF_DEFAULT_SPEED 10000000
 666 #define CONFIG_SF_DEFAULT_MODE  0
 667 #endif
 668
 669 #if defined(CONFIG_PCI)
 670 /*
 671  * General PCI
 672  * Memory space is mapped 1-1, but I/O space must start from 0.
 673  */
 674
 675 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 676 #define CONFIG_SYS_PCIE2_NAME           "PCIe SLOT"
 677 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 678 #ifdef CONFIG_PHYS_64BIT
 679 #define CONFIG_SYS_PCIE2_MEM_BUS        0xc0000000
 680 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 681 #else
 682 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 683 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 684 #endif
 685 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 686 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 687 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 688 #ifdef CONFIG_PHYS_64BIT
 689 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 690 #else
 691 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 692 #endif
 693 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 694
 695 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 696 #define CONFIG_SYS_PCIE1_NAME           "mini PCIe SLOT"
 697 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 698 #ifdef CONFIG_PHYS_64BIT
 699 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 700 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 701 #else
 702 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 703 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 704 #endif
 705 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 706 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 707 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 708 #ifdef CONFIG_PHYS_64BIT
 709 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
 710 #else
 711 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
 712 #endif
 713 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 714
 715 #define CONFIG_PCI_PNP  /* do pci plug-and-play */
 716 #define CONFIG_CMD_PCI
 717
 718 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 719 #define CONFIG_DOS_PARTITION
 720 #endif /* CONFIG_PCI */
 721
 722 #if defined(CONFIG_TSEC_ENET)
 723 #define CONFIG_MII              /* MII PHY management */
 724 #define CONFIG_TSEC1
 725 #define CONFIG_TSEC1_NAME       "eTSEC1"
 726 #define CONFIG_TSEC2
 727 #define CONFIG_TSEC2_NAME       "eTSEC2"
 728 #define CONFIG_TSEC3
 729 #define CONFIG_TSEC3_NAME       "eTSEC3"
 730
 731 #define TSEC1_PHY_ADDR  2
 732 #define TSEC2_PHY_ADDR  0
 733 #define TSEC3_PHY_ADDR  1
 734
 735 #define TSEC1_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 736 #define TSEC2_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 737 #define TSEC3_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 738
 739 #define TSEC1_PHYIDX    0
 740 #define TSEC2_PHYIDX    0
 741 #define TSEC3_PHYIDX    0
 742
 743 #define CONFIG_ETHPRIME "eTSEC1"
 744
 745 #define CONFIG_PHY_GIGE 1       /* Include GbE speed/duplex detection */
 746
 747 #define CONFIG_HAS_ETH0
 748 #define CONFIG_HAS_ETH1
 749 #define CONFIG_HAS_ETH2
 750 #endif /* CONFIG_TSEC_ENET */
 751
 752 #ifdef CONFIG_QE
 753 /* QE microcode/firmware address */
 754 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 755 #define CONFIG_SYS_QE_FW_ADDR   0xefec0000
 756 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 757 #endif /* CONFIG_QE */
 758
 759 #ifdef CONFIG_P1025RDB
 760 /*
 761  * QE UEC ethernet configuration
 762  */
 763 #define CONFIG_MIIM_ADDRESS     (CONFIG_SYS_CCSRBAR + 0x82120)
 764
 765 #undef CONFIG_UEC_ETH
 766 #define CONFIG_PHY_MODE_NEED_CHANGE
 767
 768 #define CONFIG_UEC_ETH1 /* ETH1 */
 769 #define CONFIG_HAS_ETH0
 770
 771 #ifdef CONFIG_UEC_ETH1
 772 #define CONFIG_SYS_UEC1_UCC_NUM 0       /* UCC1 */
 773 #define CONFIG_SYS_UEC1_RX_CLK  QE_CLK12 /* CLK12 for MII */
 774 #define CONFIG_SYS_UEC1_TX_CLK  QE_CLK9 /* CLK9 for MII */
 775 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 776 #define CONFIG_SYS_UEC1_PHY_ADDR        0x0     /* 0x0 for MII */
 777 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 778 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 779 #endif /* CONFIG_UEC_ETH1 */
 780
 781 #define CONFIG_UEC_ETH5 /* ETH5 */
 782 #define CONFIG_HAS_ETH1
 783
 784 #ifdef CONFIG_UEC_ETH5
 785 #define CONFIG_SYS_UEC5_UCC_NUM 4       /* UCC5 */
 786 #define CONFIG_SYS_UEC5_RX_CLK  QE_CLK_NONE
 787 #define CONFIG_SYS_UEC5_TX_CLK  QE_CLK13 /* CLK 13 for RMII */
 788 #define CONFIG_SYS_UEC5_ETH_TYPE        FAST_ETH
 789 #define CONFIG_SYS_UEC5_PHY_ADDR        0x3     /* 0x3 for RMII */
 790 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 791 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
 792 #endif /* CONFIG_UEC_ETH5 */
 793 #endif /* CONFIG_P1025RDB */
 794
 795 /*
 796  * Environment
 797  */
 798 #ifdef CONFIG_SPIFLASH
 799 #define CONFIG_ENV_IS_IN_SPI_FLASH
 800 #define CONFIG_ENV_SPI_BUS      0
 801 #define CONFIG_ENV_SPI_CS       0
 802 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 803 #define CONFIG_ENV_SPI_MODE     0
 804 #define CONFIG_ENV_SIZE         0x2000  /* 8KB */
 805 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 806 #define CONFIG_ENV_SECT_SIZE    0x10000
 807 #elif defined(CONFIG_SDCARD)
 808 #define CONFIG_ENV_IS_IN_MMC
 809 #define CONFIG_FSL_FIXED_MMC_LOCATION
 810 #define CONFIG_ENV_SIZE         0x2000
 811 #define CONFIG_SYS_MMC_ENV_DEV  0
 812 #elif defined(CONFIG_NAND)
 813 #ifdef CONFIG_TPL_BUILD
 814 #define CONFIG_ENV_SIZE         0x2000
 815 #define CONFIG_ENV_ADDR         (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 816 #else
 817 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 818 #endif
 819 #define CONFIG_ENV_IS_IN_NAND
 820 #define CONFIG_ENV_OFFSET       (1024 * 1024)
 821 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE)
 822 #elif defined(CONFIG_SYS_RAMBOOT)
 823 #define CONFIG_ENV_IS_NOWHERE   /* Store ENV in memory only */
 824 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 825 #define CONFIG_ENV_SIZE         0x2000
 826 #else
 827 #define CONFIG_ENV_IS_IN_FLASH
 828 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 829 #define CONFIG_ENV_SIZE         0x2000
 830 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 831 #endif
 832
 833 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 834 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 835
 836 /*
 837  * Command line configuration.
 838  */
 839 #define CONFIG_CMD_IRQ
 840 #define CONFIG_CMD_DATE
 841 #define CONFIG_CMD_REGINFO
 842
 843 /*
 844  * USB
 845  */
 846 #define CONFIG_HAS_FSL_DR_USB
 847
 848 #if defined(CONFIG_HAS_FSL_DR_USB)
 849 #define CONFIG_USB_EHCI
 850
 851 #ifdef CONFIG_USB_EHCI
 852 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 853 #define CONFIG_USB_EHCI_FSL
 854 #endif
 855 #endif
 856
 857 #if defined(CONFIG_P1020RDB_PD)
 858 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
 859 #endif
 860
 861 #define CONFIG_MMC
 862
 863 #ifdef CONFIG_MMC
 864 #define CONFIG_FSL_ESDHC
 865 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 866 #define CONFIG_GENERIC_MMC
 867 #endif
 868
 869 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
 870                  || defined(CONFIG_FSL_SATA)
 871 #define CONFIG_DOS_PARTITION
 872 #endif
 873
 874 #undef CONFIG_WATCHDOG  /* watchdog disabled */
 875
 876 /*
 877  * Miscellaneous configurable options
 878  */
 879 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 880 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 881 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 882 #if defined(CONFIG_CMD_KGDB)
 883 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 884 #else
 885 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 886 #endif
 887 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 888         /* Print Buffer Size */
 889 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 890 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 891
 892 /*
 893  * For booting Linux, the board info and command line data
 894  * have to be in the first 64 MB of memory, since this is
 895  * the maximum mapped by the Linux kernel during initialization.
 896  */
 897 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux*/
 898 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 899
 900 #if defined(CONFIG_CMD_KGDB)
 901 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 902 #endif
 903
 904 /*
 905  * Environment Configuration
 906  */
 907 #define CONFIG_HOSTNAME         unknown
 908 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 909 #define CONFIG_BOOTFILE         "uImage"
 910 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 911
 912 /* default location for tftp and bootm */
 913 #define CONFIG_LOADADDR 1000000
 914
 915 #define CONFIG_BOOTARGS /* the boot command will set bootargs */
 916
 917 #define CONFIG_BAUDRATE 115200
 918
 919 #ifdef __SW_BOOT_NOR
 920 #define __NOR_RST_CMD   \
 921 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
 922 i2c mw 18 3 __SW_BOOT_MASK 1; reset
 923 #endif
 924 #ifdef __SW_BOOT_SPI
 925 #define __SPI_RST_CMD   \
 926 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
 927 i2c mw 18 3 __SW_BOOT_MASK 1; reset
 928 #endif
 929 #ifdef __SW_BOOT_SD
 930 #define __SD_RST_CMD    \
 931 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
 932 i2c mw 18 3 __SW_BOOT_MASK 1; reset
 933 #endif
 934 #ifdef __SW_BOOT_NAND
 935 #define __NAND_RST_CMD  \
 936 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
 937 i2c mw 18 3 __SW_BOOT_MASK 1; reset
 938 #endif
 939 #ifdef __SW_BOOT_PCIE
 940 #define __PCIE_RST_CMD  \
 941 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
 942 i2c mw 18 3 __SW_BOOT_MASK 1; reset
 943 #endif
 944
 945 #define CONFIG_EXTRA_ENV_SETTINGS       \
 946 "netdev=eth0\0" \
 947 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"     \
 948 "loadaddr=1000000\0"    \
 949 "bootfile=uImage\0"     \
 950 "tftpflash=tftpboot $loadaddr $uboot; " \
 951         "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 952         "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "      \
 953         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
 954         "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 955         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
 956 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"    \
 957 "consoledev=ttyS0\0"    \
 958 "ramdiskaddr=2000000\0" \
 959 "ramdiskfile=rootfs.ext2.gz.uboot\0"    \
 960 "fdtaddr=1e00000\0"     \
 961 "bdev=sda1\0" \
 962 "jffs2nor=mtdblock3\0"  \
 963 "norbootaddr=ef080000\0"        \
 964 "norfdtaddr=ef040000\0" \
 965 "jffs2nand=mtdblock9\0" \
 966 "nandbootaddr=100000\0" \
 967 "nandfdtaddr=80000\0"           \
 968 "ramdisk_size=120000\0" \
 969 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
 970 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
 971 __stringify(__NOR_RST_CMD)"\0" \
 972 __stringify(__SPI_RST_CMD)"\0" \
 973 __stringify(__SD_RST_CMD)"\0" \
 974 __stringify(__NAND_RST_CMD)"\0" \
 975 __stringify(__PCIE_RST_CMD)"\0"
 976
 977 #define CONFIG_NFSBOOTCOMMAND   \
 978 "setenv bootargs root=/dev/nfs rw "     \
 979 "nfsroot=$serverip:$rootpath "  \
 980 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 981 "console=$consoledev,$baudrate $othbootargs;" \
 982 "tftp $loadaddr $bootfile;"     \
 983 "tftp $fdtaddr $fdtfile;"       \
 984 "bootm $loadaddr - $fdtaddr"
 985
 986 #define CONFIG_HDBOOT   \
 987 "setenv bootargs root=/dev/$bdev rw rootdelay=30 "      \
 988 "console=$consoledev,$baudrate $othbootargs;" \
 989 "usb start;"    \
 990 "ext2load usb 0:1 $loadaddr /boot/$bootfile;"   \
 991 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"     \
 992 "bootm $loadaddr - $fdtaddr"
 993
 994 #define CONFIG_USB_FAT_BOOT     \
 995 "setenv bootargs root=/dev/ram rw "     \
 996 "console=$consoledev,$baudrate $othbootargs " \
 997 "ramdisk_size=$ramdisk_size;"   \
 998 "usb start;"    \
 999 "fatload usb 0:2 $loadaddr $bootfile;"  \
1000 "fatload usb 0:2 $fdtaddr $fdtfile;"    \
1001 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
1002 "bootm $loadaddr $ramdiskaddr $fdtaddr"
1003
1004 #define CONFIG_USB_EXT2_BOOT    \
1005 "setenv bootargs root=/dev/ram rw "     \
1006 "console=$consoledev,$baudrate $othbootargs " \
1007 "ramdisk_size=$ramdisk_size;"   \
1008 "usb start;"    \
1009 "ext2load usb 0:4 $loadaddr $bootfile;" \
1010 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
1011 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
1012 "bootm $loadaddr $ramdiskaddr $fdtaddr"
1013
1014 #define CONFIG_NORBOOT  \
1015 "setenv bootargs root=/dev/$jffs2nor rw "       \
1016 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"  \
1017 "bootm $norbootaddr - $norfdtaddr"
1018
1019 #define CONFIG_RAMBOOTCOMMAND   \
1020 "setenv bootargs root=/dev/ram rw "     \
1021 "console=$consoledev,$baudrate $othbootargs " \
1022 "ramdisk_size=$ramdisk_size;"   \
1023 "tftp $ramdiskaddr $ramdiskfile;"       \
1024 "tftp $loadaddr $bootfile;"     \
1025 "tftp $fdtaddr $fdtfile;"       \
1026 "bootm $loadaddr $ramdiskaddr $fdtaddr"
1027
1028 #define CONFIG_BOOTCOMMAND      CONFIG_HDBOOT
1029
1030 #endif /* __CONFIG_H */