include/configs/p1_p2_rdb_pc.h

   1 /*
   2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * QorIQ RDB boards configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #if defined(CONFIG_TARGET_P1020MBG)
  14 #define CONFIG_BOARDNAME "P1020MBG-PC"
  15 #define CONFIG_VSC7385_ENET
  16 #define CONFIG_SLIC
  17 #define __SW_BOOT_MASK          0x03
  18 #define __SW_BOOT_NOR           0xe4
  19 #define __SW_BOOT_SD            0x54
  20 #define CONFIG_SYS_L2_SIZE      (256 << 10)
  21 #endif
  22
  23 #if defined(CONFIG_TARGET_P1020UTM)
  24 #define CONFIG_BOARDNAME "P1020UTM-PC"
  25 #define __SW_BOOT_MASK          0x03
  26 #define __SW_BOOT_NOR           0xe0
  27 #define __SW_BOOT_SD            0x50
  28 #define CONFIG_SYS_L2_SIZE      (256 << 10)
  29 #endif
  30
  31 #if defined(CONFIG_TARGET_P1020RDB_PC)
  32 #define CONFIG_BOARDNAME "P1020RDB-PC"
  33 #define CONFIG_NAND_FSL_ELBC
  34 #define CONFIG_VSC7385_ENET
  35 #define CONFIG_SLIC
  36 #define __SW_BOOT_MASK          0x03
  37 #define __SW_BOOT_NOR           0x5c
  38 #define __SW_BOOT_SPI           0x1c
  39 #define __SW_BOOT_SD            0x9c
  40 #define __SW_BOOT_NAND          0xec
  41 #define __SW_BOOT_PCIE          0x6c
  42 #define CONFIG_SYS_L2_SIZE      (256 << 10)
  43 #endif
  44
  45 /*
  46  * P1020RDB-PD board has user selectable switches for evaluating different
  47  * frequency and boot options for the P1020 device. The table that
  48  * follow describe the available options. The front six binary number was in
  49  * accordance with SW3[1:6].
  50  * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
  51  * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
  52  * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
  53  * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
  54  * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
  55  * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
  56  * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
  57  */
  58 #if defined(CONFIG_TARGET_P1020RDB_PD)
  59 #define CONFIG_BOARDNAME "P1020RDB-PD"
  60 #define CONFIG_NAND_FSL_ELBC
  61 #define CONFIG_VSC7385_ENET
  62 #define CONFIG_SLIC
  63 #define __SW_BOOT_MASK          0x03
  64 #define __SW_BOOT_NOR           0x64
  65 #define __SW_BOOT_SPI           0x34
  66 #define __SW_BOOT_SD            0x24
  67 #define __SW_BOOT_NAND          0x44
  68 #define __SW_BOOT_PCIE          0x74
  69 #define CONFIG_SYS_L2_SIZE      (256 << 10)
  70 /*
  71  * Dynamic MTD Partition support with mtdparts
  72  */
  73 #define CONFIG_MTD_DEVICE
  74 #define CONFIG_MTD_PARTITIONS
  75 #define CONFIG_CMD_MTDPARTS
  76 #define CONFIG_FLASH_CFI_MTD
  77 #define MTDIDS_DEFAULT "nor0=ec000000.nor"
  78 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \
  79                         "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
  80 #endif
  81
  82 #if defined(CONFIG_TARGET_P1021RDB)
  83 #define CONFIG_BOARDNAME "P1021RDB-PC"
  84 #define CONFIG_NAND_FSL_ELBC
  85 #define CONFIG_QE
  86 #define CONFIG_VSC7385_ENET
  87 #define CONFIG_SYS_LBC_LBCR     0x00080000      /* Implement conversion of
  88                                                 addresses in the LBC */
  89 #define __SW_BOOT_MASK          0x03
  90 #define __SW_BOOT_NOR           0x5c
  91 #define __SW_BOOT_SPI           0x1c
  92 #define __SW_BOOT_SD            0x9c
  93 #define __SW_BOOT_NAND          0xec
  94 #define __SW_BOOT_PCIE          0x6c
  95 #define CONFIG_SYS_L2_SIZE      (256 << 10)
  96 /*
  97  * Dynamic MTD Partition support with mtdparts
  98  */
  99 #define CONFIG_MTD_DEVICE
 100 #define CONFIG_MTD_PARTITIONS
 101 #define CONFIG_CMD_MTDPARTS
 102 #define CONFIG_FLASH_CFI_MTD
 103 #ifdef CONFIG_PHYS_64BIT
 104 #define MTDIDS_DEFAULT "nor0=fef000000.nor"
 105 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \
 106                         "256k(dtb),4608k(kernel),9728k(fs)," \
 107                         "256k(qe-ucode-firmware),1280k(u-boot)"
 108 #else
 109 #define MTDIDS_DEFAULT "nor0=ef000000.nor"
 110 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \
 111                         "256k(dtb),4608k(kernel),9728k(fs)," \
 112                         "256k(qe-ucode-firmware),1280k(u-boot)"
 113 #endif
 114 #endif
 115
 116 #if defined(CONFIG_TARGET_P1024RDB)
 117 #define CONFIG_BOARDNAME "P1024RDB"
 118 #define CONFIG_NAND_FSL_ELBC
 119 #define CONFIG_SLIC
 120 #define __SW_BOOT_MASK          0xf3
 121 #define __SW_BOOT_NOR           0x00
 122 #define __SW_BOOT_SPI           0x08
 123 #define __SW_BOOT_SD            0x04
 124 #define __SW_BOOT_NAND          0x0c
 125 #define CONFIG_SYS_L2_SIZE      (256 << 10)
 126 #endif
 127
 128 #if defined(CONFIG_TARGET_P1025RDB)
 129 #define CONFIG_BOARDNAME "P1025RDB"
 130 #define CONFIG_NAND_FSL_ELBC
 131 #define CONFIG_QE
 132 #define CONFIG_SLIC
 133
 134 #define CONFIG_SYS_LBC_LBCR     0x00080000      /* Implement conversion of
 135                                                 addresses in the LBC */
 136 #define __SW_BOOT_MASK          0xf3
 137 #define __SW_BOOT_NOR           0x00
 138 #define __SW_BOOT_SPI           0x08
 139 #define __SW_BOOT_SD            0x04
 140 #define __SW_BOOT_NAND          0x0c
 141 #define CONFIG_SYS_L2_SIZE      (256 << 10)
 142 #endif
 143
 144 #if defined(CONFIG_TARGET_P2020RDB)
 145 #define CONFIG_BOARDNAME "P2020RDB-PC"
 146 #define CONFIG_NAND_FSL_ELBC
 147 #define CONFIG_VSC7385_ENET
 148 #define __SW_BOOT_MASK          0x03
 149 #define __SW_BOOT_NOR           0xc8
 150 #define __SW_BOOT_SPI           0x28
 151 #define __SW_BOOT_SD            0x68 /* or 0x18 */
 152 #define __SW_BOOT_NAND          0xe8
 153 #define __SW_BOOT_PCIE          0xa8
 154 #define CONFIG_SYS_L2_SIZE      (512 << 10)
 155 /*
 156  * Dynamic MTD Partition support with mtdparts
 157  */
 158 #define CONFIG_MTD_DEVICE
 159 #define CONFIG_MTD_PARTITIONS
 160 #define CONFIG_CMD_MTDPARTS
 161 #define CONFIG_FLASH_CFI_MTD
 162 #ifdef CONFIG_PHYS_64BIT
 163 #define MTDIDS_DEFAULT "nor0=fef000000.nor"
 164 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \
 165                         "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
 166 #else
 167 #define MTDIDS_DEFAULT "nor0=ef000000.nor"
 168 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \
 169                         "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
 170 #endif
 171 #endif
 172
 173 #ifdef CONFIG_SDCARD
 174 #define CONFIG_SPL_MMC_MINIMAL
 175 #define CONFIG_SPL_FLUSH_IMAGE
 176 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
 177 #define CONFIG_SYS_TEXT_BASE            0x11001000
 178 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
 179 #define CONFIG_SPL_PAD_TO               0x20000
 180 #define CONFIG_SPL_MAX_SIZE             (128 * 1024)
 181 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
 182 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
 183 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
 184 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (128 << 10)
 185 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 186 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
 187 #define CONFIG_SPL_MMC_BOOT
 188 #ifdef CONFIG_SPL_BUILD
 189 #define CONFIG_SPL_COMMON_INIT_DDR
 190 #endif
 191 #endif
 192
 193 #ifdef CONFIG_SPIFLASH
 194 #define CONFIG_SPL_SPI_FLASH_MINIMAL
 195 #define CONFIG_SPL_FLUSH_IMAGE
 196 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
 197 #define CONFIG_SYS_TEXT_BASE            0x11001000
 198 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
 199 #define CONFIG_SPL_PAD_TO               0x20000
 200 #define CONFIG_SPL_MAX_SIZE             (128 * 1024)
 201 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
 202 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
 203 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
 204 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (128 << 10)
 205 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 206 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
 207 #define CONFIG_SPL_SPI_BOOT
 208 #ifdef CONFIG_SPL_BUILD
 209 #define CONFIG_SPL_COMMON_INIT_DDR
 210 #endif
 211 #endif
 212
 213 #ifdef CONFIG_NAND
 214 #ifdef CONFIG_TPL_BUILD
 215 #define CONFIG_SPL_NAND_BOOT
 216 #define CONFIG_SPL_FLUSH_IMAGE
 217 #define CONFIG_SPL_NAND_INIT
 218 #define CONFIG_SPL_COMMON_INIT_DDR
 219 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
 220 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
 221 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 222 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (832 << 10)
 223 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
 224 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
 225 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
 226 #elif defined(CONFIG_SPL_BUILD)
 227 #define CONFIG_SPL_INIT_MINIMAL
 228 #define CONFIG_SPL_FLUSH_IMAGE
 229 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
 230 #define CONFIG_SPL_TEXT_BASE            0xff800000
 231 #define CONFIG_SPL_MAX_SIZE             4096
 232 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
 233 #define CONFIG_SYS_NAND_U_BOOT_DST      0xf8f80000
 234 #define CONFIG_SYS_NAND_U_BOOT_START    0xf8f80000
 235 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
 236 #endif /* not CONFIG_TPL_BUILD */
 237
 238 #define CONFIG_SPL_PAD_TO               0x20000
 239 #define CONFIG_TPL_PAD_TO               0x20000
 240 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
 241 #define CONFIG_SYS_TEXT_BASE            0x11001000
 242 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 243 #endif
 244
 245 #ifndef CONFIG_SYS_TEXT_BASE
 246 #define CONFIG_SYS_TEXT_BASE            0xeff40000
 247 #endif
 248
 249 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 250 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 251 #endif
 252
 253 #ifndef CONFIG_SYS_MONITOR_BASE
 254 #ifdef CONFIG_SPL_BUILD
 255 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 256 #else
 257 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 258 #endif
 259 #endif
 260
 261 /* High Level Configuration Options */
 262 #define CONFIG_BOOKE
 263 #define CONFIG_E500
 264
 265 #define CONFIG_MP
 266
 267 #define CONFIG_FSL_ELBC
 268 #define CONFIG_PCIE1    /* PCIE controller 1 (slot 1) */
 269 #define CONFIG_PCIE2    /* PCIE controller 2 (slot 2) */
 270 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 271 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 272 #define CONFIG_FSL_PCIE_RESET   /* need PCIe reset errata */
 273 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 274
 275 #define CONFIG_TSEC_ENET        /* tsec ethernet support */
 276 #define CONFIG_ENV_OVERWRITE
 277
 278 #define CONFIG_CMD_SATA
 279 #define CONFIG_SATA_SIL
 280 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 281 #define CONFIG_LIBATA
 282 #define CONFIG_LBA48
 283
 284 #if defined(CONFIG_TARGET_P2020RDB)
 285 #define CONFIG_SYS_CLK_FREQ     100000000
 286 #else
 287 #define CONFIG_SYS_CLK_FREQ     66666666
 288 #endif
 289 #define CONFIG_DDR_CLK_FREQ     66666666
 290
 291 #define CONFIG_HWCONFIG
 292 /*
 293  * These can be toggled for performance analysis, otherwise use default.
 294  */
 295 #define CONFIG_L2_CACHE
 296 #define CONFIG_BTB
 297
 298 #define CONFIG_BOARD_EARLY_INIT_F       /* Call board_pre_init */
 299
 300 #define CONFIG_ENABLE_36BIT_PHYS
 301
 302 #ifdef CONFIG_PHYS_64BIT
 303 #define CONFIG_ADDR_MAP                 1
 304 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
 305 #endif
 306
 307 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 308 #define CONFIG_SYS_MEMTEST_END          0x1fffffff
 309 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 310
 311 #define CONFIG_SYS_CCSRBAR              0xffe00000
 312 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 313
 314 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
 315        SPL code*/
 316 #ifdef CONFIG_SPL_BUILD
 317 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 318 #endif
 319
 320 /* DDR Setup */
 321 #define CONFIG_SYS_FSL_DDR3
 322 #define CONFIG_SYS_DDR_RAW_TIMING
 323 #define CONFIG_DDR_SPD
 324 #define CONFIG_SYS_SPD_BUS_NUM 1
 325 #define SPD_EEPROM_ADDRESS 0x52
 326 #undef CONFIG_FSL_DDR_INTERACTIVE
 327
 328 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
 329 #define CONFIG_SYS_SDRAM_SIZE_LAW       LAW_SIZE_2G
 330 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 331 #else
 332 #define CONFIG_SYS_SDRAM_SIZE_LAW       LAW_SIZE_1G
 333 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 334 #endif
 335 #define CONFIG_SYS_SDRAM_SIZE           (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
 336 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 337 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 338
 339 #define CONFIG_NUM_DDR_CONTROLLERS      1
 340 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 341
 342 /* Default settings for DDR3 */
 343 #ifndef CONFIG_TARGET_P2020RDB
 344 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
 345 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
 346 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
 347 #define CONFIG_SYS_DDR_CS1_BNDS         0x0040007f
 348 #define CONFIG_SYS_DDR_CS1_CONFIG       0x80014302
 349 #define CONFIG_SYS_DDR_CS1_CONFIG_2     0x00000000
 350
 351 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 352 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
 353 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
 354 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
 355
 356 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 357 #define CONFIG_SYS_DDR_WRLVL_CONTROL    0x8655A608
 358 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
 359 #define CONFIG_SYS_DDR_RCW_1            0x00000000
 360 #define CONFIG_SYS_DDR_RCW_2            0x00000000
 361 #define CONFIG_SYS_DDR_CONTROL          0xC70C0000      /* Type = DDR3  */
 362 #define CONFIG_SYS_DDR_CONTROL_2        0x04401050
 363 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
 364 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 365
 366 #define CONFIG_SYS_DDR_TIMING_3         0x00020000
 367 #define CONFIG_SYS_DDR_TIMING_0         0x00330004
 368 #define CONFIG_SYS_DDR_TIMING_1         0x6f6B4846
 369 #define CONFIG_SYS_DDR_TIMING_2         0x0FA8C8CF
 370 #define CONFIG_SYS_DDR_CLK_CTRL         0x03000000
 371 #define CONFIG_SYS_DDR_MODE_1           0x40461520
 372 #define CONFIG_SYS_DDR_MODE_2           0x8000c000
 373 #define CONFIG_SYS_DDR_INTERVAL         0x0C300000
 374 #endif
 375
 376 #undef CONFIG_CLOCKS_IN_MHZ
 377
 378 /*
 379  * Memory map
 380  *
 381  * 0x0000_0000 0x7fff_ffff      DDR             Up to 2GB cacheable
 382  * 0x8000_0000 0xdfff_ffff      PCI Express Mem 1.5G non-cacheable(PCIe * 3)
 383  * 0xec00_0000 0xefff_ffff      NOR flash       Up to 64M non-cacheable CS0/1
 384  * 0xf8f8_0000 0xf8ff_ffff      L2 SRAM         Up to 512K cacheable
 385  *   (early boot only)
 386  * 0xff80_0000 0xff80_7fff      NAND flash      32K non-cacheable       CS1/0
 387  * 0xff98_0000 0xff98_ffff      PMC             64K non-cacheable       CS2
 388  * 0xffa0_0000 0xffaf_ffff      CPLD            1M non-cacheable        CS3
 389  * 0xffb0_0000 0xffbf_ffff      VSC7385 switch  1M non-cacheable        CS2
 390  * 0xffc0_0000 0xffc3_ffff      PCI IO range    256k non-cacheable
 391  * 0xffd0_0000 0xffd0_3fff      L1 for stack    16K cacheable
 392  * 0xffe0_0000 0xffef_ffff      CCSR            1M non-cacheable
 393  */
 394
 395 /*
 396  * Local Bus Definitions
 397  */
 398 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
 399 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* 64M */
 400 #define CONFIG_SYS_FLASH_BASE           0xec000000
 401 #elif defined(CONFIG_TARGET_P1020UTM)
 402 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* 32M */
 403 #define CONFIG_SYS_FLASH_BASE           0xee000000
 404 #else
 405 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* 16M */
 406 #define CONFIG_SYS_FLASH_BASE           0xef000000
 407 #endif
 408
 409 #ifdef CONFIG_PHYS_64BIT
 410 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 411 #else
 412 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 413 #endif
 414
 415 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 416         | BR_PS_16 | BR_V)
 417
 418 #define CONFIG_FLASH_OR_PRELIM  0xfc000ff7
 419
 420 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 421 #define CONFIG_SYS_FLASH_QUIET_TEST
 422 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 423
 424 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 425
 426 #undef CONFIG_SYS_FLASH_CHECKSUM
 427 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 428 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 429
 430 #define CONFIG_FLASH_CFI_DRIVER
 431 #define CONFIG_SYS_FLASH_CFI
 432 #define CONFIG_SYS_FLASH_EMPTY_INFO
 433 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 434
 435 /* Nand Flash */
 436 #ifdef CONFIG_NAND_FSL_ELBC
 437 #define CONFIG_SYS_NAND_BASE            0xff800000
 438 #ifdef CONFIG_PHYS_64BIT
 439 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 440 #else
 441 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 442 #endif
 443
 444 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 445 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 446 #define CONFIG_CMD_NAND
 447 #if defined(CONFIG_TARGET_P1020RDB_PD)
 448 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 449 #else
 450 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 * 1024)
 451 #endif
 452
 453 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 454         | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 455         | BR_PS_8       /* Port Size = 8 bit */ \
 456         | BR_MS_FCM     /* MSEL = FCM */ \
 457         | BR_V) /* valid */
 458 #if defined(CONFIG_TARGET_P1020RDB_PD)
 459 #define CONFIG_SYS_NAND_OR_PRELIM       (OR_AM_32KB \
 460         | OR_FCM_PGS    /* Large Page*/ \
 461         | OR_FCM_CSCT \
 462         | OR_FCM_CST \
 463         | OR_FCM_CHT \
 464         | OR_FCM_SCY_1 \
 465         | OR_FCM_TRLX \
 466         | OR_FCM_EHTR)
 467 #else
 468 #define CONFIG_SYS_NAND_OR_PRELIM       (OR_AM_32KB     /* small page */ \
 469         | OR_FCM_CSCT \
 470         | OR_FCM_CST \
 471         | OR_FCM_CHT \
 472         | OR_FCM_SCY_1 \
 473         | OR_FCM_TRLX \
 474         | OR_FCM_EHTR)
 475 #endif
 476 #endif /* CONFIG_NAND_FSL_ELBC */
 477
 478 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 479
 480 #define CONFIG_SYS_INIT_RAM_LOCK
 481 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* stack in RAM */
 482 #ifdef CONFIG_PHYS_64BIT
 483 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 484 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 485 /* The assembler doesn't like typecast */
 486 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 487         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 488           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 489 #else
 490 /* Initial L1 address */
 491 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 492 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 493 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 494 #endif
 495 /* Size of used area in RAM */
 496 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 497
 498 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 499                                         GENERATED_GBL_DATA_SIZE)
 500 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 501
 502 #define CONFIG_SYS_MONITOR_LEN  (768 * 1024)
 503 #define CONFIG_SYS_MALLOC_LEN   (1024 * 1024)/* Reserved for malloc */
 504
 505 #define CONFIG_SYS_CPLD_BASE    0xffa00000
 506 #ifdef CONFIG_PHYS_64BIT
 507 #define CONFIG_SYS_CPLD_BASE_PHYS       0xfffa00000ull
 508 #else
 509 #define CONFIG_SYS_CPLD_BASE_PHYS       CONFIG_SYS_CPLD_BASE
 510 #endif
 511 /* CPLD config size: 1Mb */
 512 #define CONFIG_CPLD_BR_PRELIM   (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
 513                                         BR_PS_8 | BR_V)
 514 #define CONFIG_CPLD_OR_PRELIM   (0xfff009f7)
 515
 516 #define CONFIG_SYS_PMC_BASE     0xff980000
 517 #define CONFIG_SYS_PMC_BASE_PHYS        CONFIG_SYS_PMC_BASE
 518 #define CONFIG_PMC_BR_PRELIM    (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
 519                                         BR_PS_8 | BR_V)
 520 #define CONFIG_PMC_OR_PRELIM    (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
 521                                  OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
 522                                  OR_GPCM_EAD)
 523
 524 #ifdef CONFIG_NAND
 525 #define CONFIG_SYS_BR0_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
 526 #define CONFIG_SYS_OR0_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 527 #define CONFIG_SYS_BR1_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 528 #define CONFIG_SYS_OR1_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 529 #else
 530 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 531 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 532 #ifdef CONFIG_NAND_FSL_ELBC
 533 #define CONFIG_SYS_BR1_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
 534 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 535 #endif
 536 #endif
 537 #define CONFIG_SYS_BR3_PRELIM   CONFIG_CPLD_BR_PRELIM   /* CPLD Base Address */
 538 #define CONFIG_SYS_OR3_PRELIM   CONFIG_CPLD_OR_PRELIM   /* CPLD Options */
 539
 540 /* Vsc7385 switch */
 541 #ifdef CONFIG_VSC7385_ENET
 542 #define CONFIG_SYS_VSC7385_BASE         0xffb00000
 543
 544 #ifdef CONFIG_PHYS_64BIT
 545 #define CONFIG_SYS_VSC7385_BASE_PHYS    0xfffb00000ull
 546 #else
 547 #define CONFIG_SYS_VSC7385_BASE_PHYS    CONFIG_SYS_VSC7385_BASE
 548 #endif
 549
 550 #define CONFIG_SYS_VSC7385_BR_PRELIM    \
 551         (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
 552 #define CONFIG_SYS_VSC7385_OR_PRELIM    (OR_AM_128KB | OR_GPCM_CSNT | \
 553                         OR_GPCM_XACS |  OR_GPCM_SCY_15 | OR_GPCM_SETA | \
 554                         OR_GPCM_TRLX |  OR_GPCM_EHTR | OR_GPCM_EAD)
 555
 556 #define CONFIG_SYS_BR2_PRELIM   CONFIG_SYS_VSC7385_BR_PRELIM
 557 #define CONFIG_SYS_OR2_PRELIM   CONFIG_SYS_VSC7385_OR_PRELIM
 558
 559 /* The size of the VSC7385 firmware image */
 560 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 561 #endif
 562
 563 /*
 564  * Config the L2 Cache as L2 SRAM
 565 */
 566 #if defined(CONFIG_SPL_BUILD)
 567 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 568 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 569 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 570 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 571 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 572 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 573 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
 574 #define CONFIG_SPL_RELOC_STACK_SIZE     (32 << 10)
 575 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
 576 #if defined(CONFIG_TARGET_P2020RDB)
 577 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (364 << 10)
 578 #else
 579 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (108 << 10)
 580 #endif
 581 #elif defined(CONFIG_NAND)
 582 #ifdef CONFIG_TPL_BUILD
 583 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 584 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 585 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 586 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 587 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 588 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 589 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
 590 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 591 #else
 592 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 593 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 594 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 595 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x2000)
 596 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 597 #endif /* CONFIG_TPL_BUILD */
 598 #endif
 599 #endif
 600
 601 /* Serial Port - controlled on board with jumper J8
 602  * open - index 2
 603  * shorted - index 1
 604  */
 605 #define CONFIG_CONS_INDEX               1
 606 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 607 #define CONFIG_SYS_NS16550_SERIAL
 608 #define CONFIG_SYS_NS16550_REG_SIZE     1
 609 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 610 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 611 #define CONFIG_NS16550_MIN_FUNCTIONS
 612 #endif
 613
 614 #define CONFIG_SYS_BAUDRATE_TABLE       \
 615         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 616
 617 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 618 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 619
 620 /* I2C */
 621 #define CONFIG_SYS_I2C
 622 #define CONFIG_SYS_I2C_FSL
 623 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 624 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 625 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 626 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 627 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 628 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 629 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x29} }
 630 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52
 631 #define CONFIG_SYS_SPD_BUS_NUM          1 /* For rom_loc and flash bank */
 632
 633 /*
 634  * I2C2 EEPROM
 635  */
 636 #undef CONFIG_ID_EEPROM
 637
 638 #define CONFIG_RTC_PT7C4338
 639 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 640 #define CONFIG_SYS_I2C_PCA9557_ADDR     0x18
 641
 642 /* enable read and write access to EEPROM */
 643 #define CONFIG_CMD_EEPROM
 644 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 645 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 646 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 647
 648 /*
 649  * eSPI - Enhanced SPI
 650  */
 651 #define CONFIG_HARD_SPI
 652
 653 #if defined(CONFIG_SPI_FLASH)
 654 #define CONFIG_SF_DEFAULT_SPEED 10000000
 655 #define CONFIG_SF_DEFAULT_MODE  0
 656 #endif
 657
 658 #if defined(CONFIG_PCI)
 659 /*
 660  * General PCI
 661  * Memory space is mapped 1-1, but I/O space must start from 0.
 662  */
 663
 664 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 665 #define CONFIG_SYS_PCIE2_NAME           "PCIe SLOT"
 666 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 667 #ifdef CONFIG_PHYS_64BIT
 668 #define CONFIG_SYS_PCIE2_MEM_BUS        0xc0000000
 669 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 670 #else
 671 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 672 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 673 #endif
 674 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 675 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 676 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 677 #ifdef CONFIG_PHYS_64BIT
 678 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 679 #else
 680 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 681 #endif
 682 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 683
 684 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 685 #define CONFIG_SYS_PCIE1_NAME           "mini PCIe SLOT"
 686 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 687 #ifdef CONFIG_PHYS_64BIT
 688 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 689 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 690 #else
 691 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 692 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 693 #endif
 694 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 695 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 696 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 697 #ifdef CONFIG_PHYS_64BIT
 698 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
 699 #else
 700 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
 701 #endif
 702 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 703
 704 #define CONFIG_CMD_PCI
 705
 706 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 707 #define CONFIG_DOS_PARTITION
 708 #endif /* CONFIG_PCI */
 709
 710 #if defined(CONFIG_TSEC_ENET)
 711 #define CONFIG_MII              /* MII PHY management */
 712 #define CONFIG_TSEC1
 713 #define CONFIG_TSEC1_NAME       "eTSEC1"
 714 #define CONFIG_TSEC2
 715 #define CONFIG_TSEC2_NAME       "eTSEC2"
 716 #define CONFIG_TSEC3
 717 #define CONFIG_TSEC3_NAME       "eTSEC3"
 718
 719 #define TSEC1_PHY_ADDR  2
 720 #define TSEC2_PHY_ADDR  0
 721 #define TSEC3_PHY_ADDR  1
 722
 723 #define TSEC1_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 724 #define TSEC2_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 725 #define TSEC3_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 726
 727 #define TSEC1_PHYIDX    0
 728 #define TSEC2_PHYIDX    0
 729 #define TSEC3_PHYIDX    0
 730
 731 #define CONFIG_ETHPRIME "eTSEC1"
 732
 733 #define CONFIG_PHY_GIGE 1       /* Include GbE speed/duplex detection */
 734
 735 #define CONFIG_HAS_ETH0
 736 #define CONFIG_HAS_ETH1
 737 #define CONFIG_HAS_ETH2
 738 #endif /* CONFIG_TSEC_ENET */
 739
 740 #ifdef CONFIG_QE
 741 /* QE microcode/firmware address */
 742 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 743 #define CONFIG_SYS_QE_FW_ADDR   0xefec0000
 744 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 745 #endif /* CONFIG_QE */
 746
 747 #ifdef CONFIG_TARGET_P1025RDB
 748 /*
 749  * QE UEC ethernet configuration
 750  */
 751 #define CONFIG_MIIM_ADDRESS     (CONFIG_SYS_CCSRBAR + 0x82120)
 752
 753 #undef CONFIG_UEC_ETH
 754 #define CONFIG_PHY_MODE_NEED_CHANGE
 755
 756 #define CONFIG_UEC_ETH1 /* ETH1 */
 757 #define CONFIG_HAS_ETH0
 758
 759 #ifdef CONFIG_UEC_ETH1
 760 #define CONFIG_SYS_UEC1_UCC_NUM 0       /* UCC1 */
 761 #define CONFIG_SYS_UEC1_RX_CLK  QE_CLK12 /* CLK12 for MII */
 762 #define CONFIG_SYS_UEC1_TX_CLK  QE_CLK9 /* CLK9 for MII */
 763 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 764 #define CONFIG_SYS_UEC1_PHY_ADDR        0x0     /* 0x0 for MII */
 765 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 766 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 767 #endif /* CONFIG_UEC_ETH1 */
 768
 769 #define CONFIG_UEC_ETH5 /* ETH5 */
 770 #define CONFIG_HAS_ETH1
 771
 772 #ifdef CONFIG_UEC_ETH5
 773 #define CONFIG_SYS_UEC5_UCC_NUM 4       /* UCC5 */
 774 #define CONFIG_SYS_UEC5_RX_CLK  QE_CLK_NONE
 775 #define CONFIG_SYS_UEC5_TX_CLK  QE_CLK13 /* CLK 13 for RMII */
 776 #define CONFIG_SYS_UEC5_ETH_TYPE        FAST_ETH
 777 #define CONFIG_SYS_UEC5_PHY_ADDR        0x3     /* 0x3 for RMII */
 778 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 779 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
 780 #endif /* CONFIG_UEC_ETH5 */
 781 #endif /* CONFIG_TARGET_P1025RDB */
 782
 783 /*
 784  * Environment
 785  */
 786 #ifdef CONFIG_SPIFLASH
 787 #define CONFIG_ENV_IS_IN_SPI_FLASH
 788 #define CONFIG_ENV_SPI_BUS      0
 789 #define CONFIG_ENV_SPI_CS       0
 790 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 791 #define CONFIG_ENV_SPI_MODE     0
 792 #define CONFIG_ENV_SIZE         0x2000  /* 8KB */
 793 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 794 #define CONFIG_ENV_SECT_SIZE    0x10000
 795 #elif defined(CONFIG_SDCARD)
 796 #define CONFIG_ENV_IS_IN_MMC
 797 #define CONFIG_FSL_FIXED_MMC_LOCATION
 798 #define CONFIG_ENV_SIZE         0x2000
 799 #define CONFIG_SYS_MMC_ENV_DEV  0
 800 #elif defined(CONFIG_NAND)
 801 #ifdef CONFIG_TPL_BUILD
 802 #define CONFIG_ENV_SIZE         0x2000
 803 #define CONFIG_ENV_ADDR         (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 804 #else
 805 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 806 #endif
 807 #define CONFIG_ENV_IS_IN_NAND
 808 #define CONFIG_ENV_OFFSET       (1024 * 1024)
 809 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE)
 810 #elif defined(CONFIG_SYS_RAMBOOT)
 811 #define CONFIG_ENV_IS_NOWHERE   /* Store ENV in memory only */
 812 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 813 #define CONFIG_ENV_SIZE         0x2000
 814 #else
 815 #define CONFIG_ENV_IS_IN_FLASH
 816 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 817 #define CONFIG_ENV_SIZE         0x2000
 818 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 819 #endif
 820
 821 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 822 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 823
 824 /*
 825  * Command line configuration.
 826  */
 827 #define CONFIG_CMD_IRQ
 828 #define CONFIG_CMD_DATE
 829 #define CONFIG_CMD_REGINFO
 830
 831 /*
 832  * USB
 833  */
 834 #define CONFIG_HAS_FSL_DR_USB
 835
 836 #if defined(CONFIG_HAS_FSL_DR_USB)
 837 #define CONFIG_USB_EHCI
 838
 839 #ifdef CONFIG_USB_EHCI
 840 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 841 #define CONFIG_USB_EHCI_FSL
 842 #endif
 843 #endif
 844
 845 #if defined(CONFIG_TARGET_P1020RDB_PD)
 846 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
 847 #endif
 848
 849 #define CONFIG_MMC
 850
 851 #ifdef CONFIG_MMC
 852 #define CONFIG_FSL_ESDHC
 853 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 854 #define CONFIG_GENERIC_MMC
 855 #endif
 856
 857 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
 858                  || defined(CONFIG_FSL_SATA)
 859 #define CONFIG_DOS_PARTITION
 860 #endif
 861
 862 #undef CONFIG_WATCHDOG  /* watchdog disabled */
 863
 864 /*
 865  * Miscellaneous configurable options
 866  */
 867 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 868 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 869 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 870 #if defined(CONFIG_CMD_KGDB)
 871 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 872 #else
 873 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 874 #endif
 875 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 876         /* Print Buffer Size */
 877 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 878 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 879
 880 /*
 881  * For booting Linux, the board info and command line data
 882  * have to be in the first 64 MB of memory, since this is
 883  * the maximum mapped by the Linux kernel during initialization.
 884  */
 885 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux*/
 886 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 887
 888 #if defined(CONFIG_CMD_KGDB)
 889 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 890 #endif
 891
 892 /*
 893  * Environment Configuration
 894  */
 895 #define CONFIG_HOSTNAME         unknown
 896 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 897 #define CONFIG_BOOTFILE         "uImage"
 898 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 899
 900 /* default location for tftp and bootm */
 901 #define CONFIG_LOADADDR 1000000
 902
 903 #define CONFIG_BOOTARGS /* the boot command will set bootargs */
 904
 905 #define CONFIG_BAUDRATE 115200
 906
 907 #ifdef __SW_BOOT_NOR
 908 #define __NOR_RST_CMD   \
 909 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
 910 i2c mw 18 3 __SW_BOOT_MASK 1; reset
 911 #endif
 912 #ifdef __SW_BOOT_SPI
 913 #define __SPI_RST_CMD   \
 914 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
 915 i2c mw 18 3 __SW_BOOT_MASK 1; reset
 916 #endif
 917 #ifdef __SW_BOOT_SD
 918 #define __SD_RST_CMD    \
 919 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
 920 i2c mw 18 3 __SW_BOOT_MASK 1; reset
 921 #endif
 922 #ifdef __SW_BOOT_NAND
 923 #define __NAND_RST_CMD  \
 924 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
 925 i2c mw 18 3 __SW_BOOT_MASK 1; reset
 926 #endif
 927 #ifdef __SW_BOOT_PCIE
 928 #define __PCIE_RST_CMD  \
 929 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
 930 i2c mw 18 3 __SW_BOOT_MASK 1; reset
 931 #endif
 932
 933 #define CONFIG_EXTRA_ENV_SETTINGS       \
 934 "netdev=eth0\0" \
 935 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"     \
 936 "loadaddr=1000000\0"    \
 937 "bootfile=uImage\0"     \
 938 "tftpflash=tftpboot $loadaddr $uboot; " \
 939         "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 940         "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "      \
 941         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
 942         "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 943         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
 944 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"    \
 945 "consoledev=ttyS0\0"    \
 946 "ramdiskaddr=2000000\0" \
 947 "ramdiskfile=rootfs.ext2.gz.uboot\0"    \
 948 "fdtaddr=1e00000\0"     \
 949 "bdev=sda1\0" \
 950 "jffs2nor=mtdblock3\0"  \
 951 "norbootaddr=ef080000\0"        \
 952 "norfdtaddr=ef040000\0" \
 953 "jffs2nand=mtdblock9\0" \
 954 "nandbootaddr=100000\0" \
 955 "nandfdtaddr=80000\0"           \
 956 "ramdisk_size=120000\0" \
 957 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
 958 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
 959 __stringify(__NOR_RST_CMD)"\0" \
 960 __stringify(__SPI_RST_CMD)"\0" \
 961 __stringify(__SD_RST_CMD)"\0" \
 962 __stringify(__NAND_RST_CMD)"\0" \
 963 __stringify(__PCIE_RST_CMD)"\0"
 964
 965 #define CONFIG_NFSBOOTCOMMAND   \
 966 "setenv bootargs root=/dev/nfs rw "     \
 967 "nfsroot=$serverip:$rootpath "  \
 968 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 969 "console=$consoledev,$baudrate $othbootargs;" \
 970 "tftp $loadaddr $bootfile;"     \
 971 "tftp $fdtaddr $fdtfile;"       \
 972 "bootm $loadaddr - $fdtaddr"
 973
 974 #define CONFIG_HDBOOT   \
 975 "setenv bootargs root=/dev/$bdev rw rootdelay=30 "      \
 976 "console=$consoledev,$baudrate $othbootargs;" \
 977 "usb start;"    \
 978 "ext2load usb 0:1 $loadaddr /boot/$bootfile;"   \
 979 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"     \
 980 "bootm $loadaddr - $fdtaddr"
 981
 982 #define CONFIG_USB_FAT_BOOT     \
 983 "setenv bootargs root=/dev/ram rw "     \
 984 "console=$consoledev,$baudrate $othbootargs " \
 985 "ramdisk_size=$ramdisk_size;"   \
 986 "usb start;"    \
 987 "fatload usb 0:2 $loadaddr $bootfile;"  \
 988 "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 989 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 990 "bootm $loadaddr $ramdiskaddr $fdtaddr"
 991
 992 #define CONFIG_USB_EXT2_BOOT    \
 993 "setenv bootargs root=/dev/ram rw "     \
 994 "console=$consoledev,$baudrate $othbootargs " \
 995 "ramdisk_size=$ramdisk_size;"   \
 996 "usb start;"    \
 997 "ext2load usb 0:4 $loadaddr $bootfile;" \
 998 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
 999 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
1000 "bootm $loadaddr $ramdiskaddr $fdtaddr"
1001
1002 #define CONFIG_NORBOOT  \
1003 "setenv bootargs root=/dev/$jffs2nor rw "       \
1004 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"  \
1005 "bootm $norbootaddr - $norfdtaddr"
1006
1007 #define CONFIG_RAMBOOTCOMMAND   \
1008 "setenv bootargs root=/dev/ram rw "     \
1009 "console=$consoledev,$baudrate $othbootargs " \
1010 "ramdisk_size=$ramdisk_size;"   \
1011 "tftp $ramdiskaddr $ramdiskfile;"       \
1012 "tftp $loadaddr $bootfile;"     \
1013 "tftp $fdtaddr $fdtfile;"       \
1014 "bootm $loadaddr $ramdiskaddr $fdtaddr"
1015
1016 #define CONFIG_BOOTCOMMAND      CONFIG_HDBOOT
1017
1018 #endif /* __CONFIG_H */