include/configs/p1_p2_rdb_pc.h

   1 /*
   2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * QorIQ RDB boards configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #if defined(CONFIG_TARGET_P1020MBG)
  14 #define CONFIG_BOARDNAME "P1020MBG-PC"
  15 #define CONFIG_VSC7385_ENET
  16 #define CONFIG_SLIC
  17 #define __SW_BOOT_MASK          0x03
  18 #define __SW_BOOT_NOR           0xe4
  19 #define __SW_BOOT_SD            0x54
  20 #define CONFIG_SYS_L2_SIZE      (256 << 10)
  21 #endif
  22
  23 #if defined(CONFIG_TARGET_P1020UTM)
  24 #define CONFIG_BOARDNAME "P1020UTM-PC"
  25 #define __SW_BOOT_MASK          0x03
  26 #define __SW_BOOT_NOR           0xe0
  27 #define __SW_BOOT_SD            0x50
  28 #define CONFIG_SYS_L2_SIZE      (256 << 10)
  29 #endif
  30
  31 #if defined(CONFIG_TARGET_P1020RDB_PC)
  32 #define CONFIG_BOARDNAME "P1020RDB-PC"
  33 #define CONFIG_NAND_FSL_ELBC
  34 #define CONFIG_VSC7385_ENET
  35 #define CONFIG_SLIC
  36 #define __SW_BOOT_MASK          0x03
  37 #define __SW_BOOT_NOR           0x5c
  38 #define __SW_BOOT_SPI           0x1c
  39 #define __SW_BOOT_SD            0x9c
  40 #define __SW_BOOT_NAND          0xec
  41 #define __SW_BOOT_PCIE          0x6c
  42 #define CONFIG_SYS_L2_SIZE      (256 << 10)
  43 #endif
  44
  45 /*
  46  * P1020RDB-PD board has user selectable switches for evaluating different
  47  * frequency and boot options for the P1020 device. The table that
  48  * follow describe the available options. The front six binary number was in
  49  * accordance with SW3[1:6].
  50  * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
  51  * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
  52  * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
  53  * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
  54  * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
  55  * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
  56  * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
  57  */
  58 #if defined(CONFIG_TARGET_P1020RDB_PD)
  59 #define CONFIG_BOARDNAME "P1020RDB-PD"
  60 #define CONFIG_NAND_FSL_ELBC
  61 #define CONFIG_VSC7385_ENET
  62 #define CONFIG_SLIC
  63 #define __SW_BOOT_MASK          0x03
  64 #define __SW_BOOT_NOR           0x64
  65 #define __SW_BOOT_SPI           0x34
  66 #define __SW_BOOT_SD            0x24
  67 #define __SW_BOOT_NAND          0x44
  68 #define __SW_BOOT_PCIE          0x74
  69 #define CONFIG_SYS_L2_SIZE      (256 << 10)
  70 /*
  71  * Dynamic MTD Partition support with mtdparts
  72  */
  73 #define CONFIG_MTD_DEVICE
  74 #define CONFIG_MTD_PARTITIONS
  75 #define CONFIG_CMD_MTDPARTS
  76 #define CONFIG_FLASH_CFI_MTD
  77 #define MTDIDS_DEFAULT "nor0=ec000000.nor"
  78 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \
  79                         "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
  80 #endif
  81
  82 #if defined(CONFIG_TARGET_P1021RDB)
  83 #define CONFIG_BOARDNAME "P1021RDB-PC"
  84 #define CONFIG_NAND_FSL_ELBC
  85 #define CONFIG_QE
  86 #define CONFIG_VSC7385_ENET
  87 #define CONFIG_SYS_LBC_LBCR     0x00080000      /* Implement conversion of
  88                                                 addresses in the LBC */
  89 #define __SW_BOOT_MASK          0x03
  90 #define __SW_BOOT_NOR           0x5c
  91 #define __SW_BOOT_SPI           0x1c
  92 #define __SW_BOOT_SD            0x9c
  93 #define __SW_BOOT_NAND          0xec
  94 #define __SW_BOOT_PCIE          0x6c
  95 #define CONFIG_SYS_L2_SIZE      (256 << 10)
  96 /*
  97  * Dynamic MTD Partition support with mtdparts
  98  */
  99 #define CONFIG_MTD_DEVICE
 100 #define CONFIG_MTD_PARTITIONS
 101 #define CONFIG_CMD_MTDPARTS
 102 #define CONFIG_FLASH_CFI_MTD
 103 #ifdef CONFIG_PHYS_64BIT
 104 #define MTDIDS_DEFAULT "nor0=fef000000.nor"
 105 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \
 106                         "256k(dtb),4608k(kernel),9728k(fs)," \
 107                         "256k(qe-ucode-firmware),1280k(u-boot)"
 108 #else
 109 #define MTDIDS_DEFAULT "nor0=ef000000.nor"
 110 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \
 111                         "256k(dtb),4608k(kernel),9728k(fs)," \
 112                         "256k(qe-ucode-firmware),1280k(u-boot)"
 113 #endif
 114 #endif
 115
 116 #if defined(CONFIG_TARGET_P1024RDB)
 117 #define CONFIG_BOARDNAME "P1024RDB"
 118 #define CONFIG_NAND_FSL_ELBC
 119 #define CONFIG_SLIC
 120 #define __SW_BOOT_MASK          0xf3
 121 #define __SW_BOOT_NOR           0x00
 122 #define __SW_BOOT_SPI           0x08
 123 #define __SW_BOOT_SD            0x04
 124 #define __SW_BOOT_NAND          0x0c
 125 #define CONFIG_SYS_L2_SIZE      (256 << 10)
 126 #endif
 127
 128 #if defined(CONFIG_TARGET_P1025RDB)
 129 #define CONFIG_BOARDNAME "P1025RDB"
 130 #define CONFIG_NAND_FSL_ELBC
 131 #define CONFIG_QE
 132 #define CONFIG_SLIC
 133
 134 #define CONFIG_SYS_LBC_LBCR     0x00080000      /* Implement conversion of
 135                                                 addresses in the LBC */
 136 #define __SW_BOOT_MASK          0xf3
 137 #define __SW_BOOT_NOR           0x00
 138 #define __SW_BOOT_SPI           0x08
 139 #define __SW_BOOT_SD            0x04
 140 #define __SW_BOOT_NAND          0x0c
 141 #define CONFIG_SYS_L2_SIZE      (256 << 10)
 142 #endif
 143
 144 #if defined(CONFIG_TARGET_P2020RDB)
 145 #define CONFIG_BOARDNAME "P2020RDB-PC"
 146 #define CONFIG_NAND_FSL_ELBC
 147 #define CONFIG_VSC7385_ENET
 148 #define __SW_BOOT_MASK          0x03
 149 #define __SW_BOOT_NOR           0xc8
 150 #define __SW_BOOT_SPI           0x28
 151 #define __SW_BOOT_SD            0x68 /* or 0x18 */
 152 #define __SW_BOOT_NAND          0xe8
 153 #define __SW_BOOT_PCIE          0xa8
 154 #define CONFIG_SYS_L2_SIZE      (512 << 10)
 155 /*
 156  * Dynamic MTD Partition support with mtdparts
 157  */
 158 #define CONFIG_MTD_DEVICE
 159 #define CONFIG_MTD_PARTITIONS
 160 #define CONFIG_CMD_MTDPARTS
 161 #define CONFIG_FLASH_CFI_MTD
 162 #ifdef CONFIG_PHYS_64BIT
 163 #define MTDIDS_DEFAULT "nor0=fef000000.nor"
 164 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \
 165                         "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
 166 #else
 167 #define MTDIDS_DEFAULT "nor0=ef000000.nor"
 168 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \
 169                         "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
 170 #endif
 171 #endif
 172
 173 #ifdef CONFIG_SDCARD
 174 #define CONFIG_SPL_MMC_MINIMAL
 175 #define CONFIG_SPL_FLUSH_IMAGE
 176 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
 177 #define CONFIG_FSL_LAW                 /* Use common FSL init code */
 178 #define CONFIG_SYS_TEXT_BASE            0x11001000
 179 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
 180 #define CONFIG_SPL_PAD_TO               0x20000
 181 #define CONFIG_SPL_MAX_SIZE             (128 * 1024)
 182 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
 183 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
 184 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
 185 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (128 << 10)
 186 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 187 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
 188 #define CONFIG_SPL_MMC_BOOT
 189 #ifdef CONFIG_SPL_BUILD
 190 #define CONFIG_SPL_COMMON_INIT_DDR
 191 #endif
 192 #endif
 193
 194 #ifdef CONFIG_SPIFLASH
 195 #define CONFIG_SPL_SPI_FLASH_MINIMAL
 196 #define CONFIG_SPL_FLUSH_IMAGE
 197 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
 198 #define CONFIG_FSL_LAW         /* Use common FSL init code */
 199 #define CONFIG_SYS_TEXT_BASE            0x11001000
 200 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
 201 #define CONFIG_SPL_PAD_TO               0x20000
 202 #define CONFIG_SPL_MAX_SIZE             (128 * 1024)
 203 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
 204 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
 205 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
 206 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (128 << 10)
 207 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 208 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
 209 #define CONFIG_SPL_SPI_BOOT
 210 #ifdef CONFIG_SPL_BUILD
 211 #define CONFIG_SPL_COMMON_INIT_DDR
 212 #endif
 213 #endif
 214
 215 #ifdef CONFIG_NAND
 216 #ifdef CONFIG_TPL_BUILD
 217 #define CONFIG_SPL_NAND_BOOT
 218 #define CONFIG_SPL_FLUSH_IMAGE
 219 #define CONFIG_SPL_NAND_INIT
 220 #define CONFIG_SPL_COMMON_INIT_DDR
 221 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
 222 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
 223 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 224 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (832 << 10)
 225 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
 226 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
 227 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
 228 #elif defined(CONFIG_SPL_BUILD)
 229 #define CONFIG_SPL_INIT_MINIMAL
 230 #define CONFIG_SPL_FLUSH_IMAGE
 231 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
 232 #define CONFIG_SPL_TEXT_BASE            0xff800000
 233 #define CONFIG_SPL_MAX_SIZE             4096
 234 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
 235 #define CONFIG_SYS_NAND_U_BOOT_DST      0xf8f80000
 236 #define CONFIG_SYS_NAND_U_BOOT_START    0xf8f80000
 237 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
 238 #endif /* not CONFIG_TPL_BUILD */
 239
 240 #define CONFIG_SPL_PAD_TO               0x20000
 241 #define CONFIG_TPL_PAD_TO               0x20000
 242 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
 243 #define CONFIG_SYS_TEXT_BASE            0x11001000
 244 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 245 #endif
 246
 247 #ifndef CONFIG_SYS_TEXT_BASE
 248 #define CONFIG_SYS_TEXT_BASE            0xeff40000
 249 #endif
 250
 251 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 252 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 253 #endif
 254
 255 #ifndef CONFIG_SYS_MONITOR_BASE
 256 #ifdef CONFIG_SPL_BUILD
 257 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 258 #else
 259 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 260 #endif
 261 #endif
 262
 263 /* High Level Configuration Options */
 264 #define CONFIG_BOOKE
 265 #define CONFIG_E500
 266
 267 #define CONFIG_MP
 268
 269 #define CONFIG_FSL_ELBC
 270 #define CONFIG_PCIE1    /* PCIE controller 1 (slot 1) */
 271 #define CONFIG_PCIE2    /* PCIE controller 2 (slot 2) */
 272 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 273 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 274 #define CONFIG_FSL_PCIE_RESET   /* need PCIe reset errata */
 275 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 276
 277 #define CONFIG_FSL_LAW
 278 #define CONFIG_TSEC_ENET        /* tsec ethernet support */
 279 #define CONFIG_ENV_OVERWRITE
 280
 281 #define CONFIG_CMD_SATA
 282 #define CONFIG_SATA_SIL
 283 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 284 #define CONFIG_LIBATA
 285 #define CONFIG_LBA48
 286
 287 #if defined(CONFIG_TARGET_P2020RDB)
 288 #define CONFIG_SYS_CLK_FREQ     100000000
 289 #else
 290 #define CONFIG_SYS_CLK_FREQ     66666666
 291 #endif
 292 #define CONFIG_DDR_CLK_FREQ     66666666
 293
 294 #define CONFIG_HWCONFIG
 295 /*
 296  * These can be toggled for performance analysis, otherwise use default.
 297  */
 298 #define CONFIG_L2_CACHE
 299 #define CONFIG_BTB
 300
 301 #define CONFIG_BOARD_EARLY_INIT_F       /* Call board_pre_init */
 302
 303 #define CONFIG_ENABLE_36BIT_PHYS
 304
 305 #ifdef CONFIG_PHYS_64BIT
 306 #define CONFIG_ADDR_MAP                 1
 307 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
 308 #endif
 309
 310 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 311 #define CONFIG_SYS_MEMTEST_END          0x1fffffff
 312 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 313
 314 #define CONFIG_SYS_CCSRBAR              0xffe00000
 315 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 316
 317 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
 318        SPL code*/
 319 #ifdef CONFIG_SPL_BUILD
 320 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 321 #endif
 322
 323 /* DDR Setup */
 324 #define CONFIG_SYS_FSL_DDR3
 325 #define CONFIG_SYS_DDR_RAW_TIMING
 326 #define CONFIG_DDR_SPD
 327 #define CONFIG_SYS_SPD_BUS_NUM 1
 328 #define SPD_EEPROM_ADDRESS 0x52
 329 #undef CONFIG_FSL_DDR_INTERACTIVE
 330
 331 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
 332 #define CONFIG_SYS_SDRAM_SIZE_LAW       LAW_SIZE_2G
 333 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 334 #else
 335 #define CONFIG_SYS_SDRAM_SIZE_LAW       LAW_SIZE_1G
 336 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 337 #endif
 338 #define CONFIG_SYS_SDRAM_SIZE           (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
 339 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 340 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 341
 342 #define CONFIG_NUM_DDR_CONTROLLERS      1
 343 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 344
 345 /* Default settings for DDR3 */
 346 #ifndef CONFIG_TARGET_P2020RDB
 347 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
 348 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
 349 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
 350 #define CONFIG_SYS_DDR_CS1_BNDS         0x0040007f
 351 #define CONFIG_SYS_DDR_CS1_CONFIG       0x80014302
 352 #define CONFIG_SYS_DDR_CS1_CONFIG_2     0x00000000
 353
 354 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 355 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
 356 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
 357 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
 358
 359 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 360 #define CONFIG_SYS_DDR_WRLVL_CONTROL    0x8655A608
 361 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
 362 #define CONFIG_SYS_DDR_RCW_1            0x00000000
 363 #define CONFIG_SYS_DDR_RCW_2            0x00000000
 364 #define CONFIG_SYS_DDR_CONTROL          0xC70C0000      /* Type = DDR3  */
 365 #define CONFIG_SYS_DDR_CONTROL_2        0x04401050
 366 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
 367 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 368
 369 #define CONFIG_SYS_DDR_TIMING_3         0x00020000
 370 #define CONFIG_SYS_DDR_TIMING_0         0x00330004
 371 #define CONFIG_SYS_DDR_TIMING_1         0x6f6B4846
 372 #define CONFIG_SYS_DDR_TIMING_2         0x0FA8C8CF
 373 #define CONFIG_SYS_DDR_CLK_CTRL         0x03000000
 374 #define CONFIG_SYS_DDR_MODE_1           0x40461520
 375 #define CONFIG_SYS_DDR_MODE_2           0x8000c000
 376 #define CONFIG_SYS_DDR_INTERVAL         0x0C300000
 377 #endif
 378
 379 #undef CONFIG_CLOCKS_IN_MHZ
 380
 381 /*
 382  * Memory map
 383  *
 384  * 0x0000_0000 0x7fff_ffff      DDR             Up to 2GB cacheable
 385  * 0x8000_0000 0xdfff_ffff      PCI Express Mem 1.5G non-cacheable(PCIe * 3)
 386  * 0xec00_0000 0xefff_ffff      NOR flash       Up to 64M non-cacheable CS0/1
 387  * 0xf8f8_0000 0xf8ff_ffff      L2 SRAM         Up to 512K cacheable
 388  *   (early boot only)
 389  * 0xff80_0000 0xff80_7fff      NAND flash      32K non-cacheable       CS1/0
 390  * 0xff98_0000 0xff98_ffff      PMC             64K non-cacheable       CS2
 391  * 0xffa0_0000 0xffaf_ffff      CPLD            1M non-cacheable        CS3
 392  * 0xffb0_0000 0xffbf_ffff      VSC7385 switch  1M non-cacheable        CS2
 393  * 0xffc0_0000 0xffc3_ffff      PCI IO range    256k non-cacheable
 394  * 0xffd0_0000 0xffd0_3fff      L1 for stack    16K cacheable
 395  * 0xffe0_0000 0xffef_ffff      CCSR            1M non-cacheable
 396  */
 397
 398 /*
 399  * Local Bus Definitions
 400  */
 401 #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD))
 402 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* 64M */
 403 #define CONFIG_SYS_FLASH_BASE           0xec000000
 404 #elif defined(CONFIG_TARGET_P1020UTM)
 405 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* 32M */
 406 #define CONFIG_SYS_FLASH_BASE           0xee000000
 407 #else
 408 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* 16M */
 409 #define CONFIG_SYS_FLASH_BASE           0xef000000
 410 #endif
 411
 412 #ifdef CONFIG_PHYS_64BIT
 413 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 414 #else
 415 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 416 #endif
 417
 418 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 419         | BR_PS_16 | BR_V)
 420
 421 #define CONFIG_FLASH_OR_PRELIM  0xfc000ff7
 422
 423 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 424 #define CONFIG_SYS_FLASH_QUIET_TEST
 425 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 426
 427 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 428
 429 #undef CONFIG_SYS_FLASH_CHECKSUM
 430 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 431 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 432
 433 #define CONFIG_FLASH_CFI_DRIVER
 434 #define CONFIG_SYS_FLASH_CFI
 435 #define CONFIG_SYS_FLASH_EMPTY_INFO
 436 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 437
 438 /* Nand Flash */
 439 #ifdef CONFIG_NAND_FSL_ELBC
 440 #define CONFIG_SYS_NAND_BASE            0xff800000
 441 #ifdef CONFIG_PHYS_64BIT
 442 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 443 #else
 444 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 445 #endif
 446
 447 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 448 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 449 #define CONFIG_CMD_NAND
 450 #if defined(CONFIG_TARGET_P1020RDB_PD)
 451 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 452 #else
 453 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 * 1024)
 454 #endif
 455
 456 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 457         | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 458         | BR_PS_8       /* Port Size = 8 bit */ \
 459         | BR_MS_FCM     /* MSEL = FCM */ \
 460         | BR_V) /* valid */
 461 #if defined(CONFIG_TARGET_P1020RDB_PD)
 462 #define CONFIG_SYS_NAND_OR_PRELIM       (OR_AM_32KB \
 463         | OR_FCM_PGS    /* Large Page*/ \
 464         | OR_FCM_CSCT \
 465         | OR_FCM_CST \
 466         | OR_FCM_CHT \
 467         | OR_FCM_SCY_1 \
 468         | OR_FCM_TRLX \
 469         | OR_FCM_EHTR)
 470 #else
 471 #define CONFIG_SYS_NAND_OR_PRELIM       (OR_AM_32KB     /* small page */ \
 472         | OR_FCM_CSCT \
 473         | OR_FCM_CST \
 474         | OR_FCM_CHT \
 475         | OR_FCM_SCY_1 \
 476         | OR_FCM_TRLX \
 477         | OR_FCM_EHTR)
 478 #endif
 479 #endif /* CONFIG_NAND_FSL_ELBC */
 480
 481 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 482
 483 #define CONFIG_SYS_INIT_RAM_LOCK
 484 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* stack in RAM */
 485 #ifdef CONFIG_PHYS_64BIT
 486 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 487 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 488 /* The assembler doesn't like typecast */
 489 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 490         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 491           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 492 #else
 493 /* Initial L1 address */
 494 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 495 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 496 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 497 #endif
 498 /* Size of used area in RAM */
 499 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 500
 501 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 502                                         GENERATED_GBL_DATA_SIZE)
 503 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 504
 505 #define CONFIG_SYS_MONITOR_LEN  (768 * 1024)
 506 #define CONFIG_SYS_MALLOC_LEN   (1024 * 1024)/* Reserved for malloc */
 507
 508 #define CONFIG_SYS_CPLD_BASE    0xffa00000
 509 #ifdef CONFIG_PHYS_64BIT
 510 #define CONFIG_SYS_CPLD_BASE_PHYS       0xfffa00000ull
 511 #else
 512 #define CONFIG_SYS_CPLD_BASE_PHYS       CONFIG_SYS_CPLD_BASE
 513 #endif
 514 /* CPLD config size: 1Mb */
 515 #define CONFIG_CPLD_BR_PRELIM   (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
 516                                         BR_PS_8 | BR_V)
 517 #define CONFIG_CPLD_OR_PRELIM   (0xfff009f7)
 518
 519 #define CONFIG_SYS_PMC_BASE     0xff980000
 520 #define CONFIG_SYS_PMC_BASE_PHYS        CONFIG_SYS_PMC_BASE
 521 #define CONFIG_PMC_BR_PRELIM    (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
 522                                         BR_PS_8 | BR_V)
 523 #define CONFIG_PMC_OR_PRELIM    (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
 524                                  OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
 525                                  OR_GPCM_EAD)
 526
 527 #ifdef CONFIG_NAND
 528 #define CONFIG_SYS_BR0_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
 529 #define CONFIG_SYS_OR0_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 530 #define CONFIG_SYS_BR1_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 531 #define CONFIG_SYS_OR1_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 532 #else
 533 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 534 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 535 #ifdef CONFIG_NAND_FSL_ELBC
 536 #define CONFIG_SYS_BR1_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
 537 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 538 #endif
 539 #endif
 540 #define CONFIG_SYS_BR3_PRELIM   CONFIG_CPLD_BR_PRELIM   /* CPLD Base Address */
 541 #define CONFIG_SYS_OR3_PRELIM   CONFIG_CPLD_OR_PRELIM   /* CPLD Options */
 542
 543 /* Vsc7385 switch */
 544 #ifdef CONFIG_VSC7385_ENET
 545 #define CONFIG_SYS_VSC7385_BASE         0xffb00000
 546
 547 #ifdef CONFIG_PHYS_64BIT
 548 #define CONFIG_SYS_VSC7385_BASE_PHYS    0xfffb00000ull
 549 #else
 550 #define CONFIG_SYS_VSC7385_BASE_PHYS    CONFIG_SYS_VSC7385_BASE
 551 #endif
 552
 553 #define CONFIG_SYS_VSC7385_BR_PRELIM    \
 554         (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
 555 #define CONFIG_SYS_VSC7385_OR_PRELIM    (OR_AM_128KB | OR_GPCM_CSNT | \
 556                         OR_GPCM_XACS |  OR_GPCM_SCY_15 | OR_GPCM_SETA | \
 557                         OR_GPCM_TRLX |  OR_GPCM_EHTR | OR_GPCM_EAD)
 558
 559 #define CONFIG_SYS_BR2_PRELIM   CONFIG_SYS_VSC7385_BR_PRELIM
 560 #define CONFIG_SYS_OR2_PRELIM   CONFIG_SYS_VSC7385_OR_PRELIM
 561
 562 /* The size of the VSC7385 firmware image */
 563 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 564 #endif
 565
 566 /*
 567  * Config the L2 Cache as L2 SRAM
 568 */
 569 #if defined(CONFIG_SPL_BUILD)
 570 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 571 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 572 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 573 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 574 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 575 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 576 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
 577 #define CONFIG_SPL_RELOC_STACK_SIZE     (32 << 10)
 578 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
 579 #if defined(CONFIG_TARGET_P2020RDB)
 580 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (364 << 10)
 581 #else
 582 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (108 << 10)
 583 #endif
 584 #elif defined(CONFIG_NAND)
 585 #ifdef CONFIG_TPL_BUILD
 586 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 587 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 588 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 589 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 590 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 591 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 592 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
 593 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 594 #else
 595 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 596 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 597 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 598 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x2000)
 599 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 600 #endif /* CONFIG_TPL_BUILD */
 601 #endif
 602 #endif
 603
 604 /* Serial Port - controlled on board with jumper J8
 605  * open - index 2
 606  * shorted - index 1
 607  */
 608 #define CONFIG_CONS_INDEX               1
 609 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 610 #define CONFIG_SYS_NS16550_SERIAL
 611 #define CONFIG_SYS_NS16550_REG_SIZE     1
 612 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 613 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 614 #define CONFIG_NS16550_MIN_FUNCTIONS
 615 #endif
 616
 617 #define CONFIG_SYS_BAUDRATE_TABLE       \
 618         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 619
 620 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 621 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 622
 623 /* I2C */
 624 #define CONFIG_SYS_I2C
 625 #define CONFIG_SYS_I2C_FSL
 626 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 627 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 628 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 629 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 630 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 631 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 632 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x29} }
 633 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52
 634 #define CONFIG_SYS_SPD_BUS_NUM          1 /* For rom_loc and flash bank */
 635
 636 /*
 637  * I2C2 EEPROM
 638  */
 639 #undef CONFIG_ID_EEPROM
 640
 641 #define CONFIG_RTC_PT7C4338
 642 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 643 #define CONFIG_SYS_I2C_PCA9557_ADDR     0x18
 644
 645 /* enable read and write access to EEPROM */
 646 #define CONFIG_CMD_EEPROM
 647 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 648 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 649 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 650
 651 /*
 652  * eSPI - Enhanced SPI
 653  */
 654 #define CONFIG_HARD_SPI
 655
 656 #if defined(CONFIG_SPI_FLASH)
 657 #define CONFIG_SF_DEFAULT_SPEED 10000000
 658 #define CONFIG_SF_DEFAULT_MODE  0
 659 #endif
 660
 661 #if defined(CONFIG_PCI)
 662 /*
 663  * General PCI
 664  * Memory space is mapped 1-1, but I/O space must start from 0.
 665  */
 666
 667 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 668 #define CONFIG_SYS_PCIE2_NAME           "PCIe SLOT"
 669 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 670 #ifdef CONFIG_PHYS_64BIT
 671 #define CONFIG_SYS_PCIE2_MEM_BUS        0xc0000000
 672 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 673 #else
 674 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 675 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 676 #endif
 677 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 678 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 679 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 680 #ifdef CONFIG_PHYS_64BIT
 681 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 682 #else
 683 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 684 #endif
 685 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 686
 687 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 688 #define CONFIG_SYS_PCIE1_NAME           "mini PCIe SLOT"
 689 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 690 #ifdef CONFIG_PHYS_64BIT
 691 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 692 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 693 #else
 694 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 695 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 696 #endif
 697 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 698 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 699 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 700 #ifdef CONFIG_PHYS_64BIT
 701 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
 702 #else
 703 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
 704 #endif
 705 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 706
 707 #define CONFIG_CMD_PCI
 708
 709 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 710 #define CONFIG_DOS_PARTITION
 711 #endif /* CONFIG_PCI */
 712
 713 #if defined(CONFIG_TSEC_ENET)
 714 #define CONFIG_MII              /* MII PHY management */
 715 #define CONFIG_TSEC1
 716 #define CONFIG_TSEC1_NAME       "eTSEC1"
 717 #define CONFIG_TSEC2
 718 #define CONFIG_TSEC2_NAME       "eTSEC2"
 719 #define CONFIG_TSEC3
 720 #define CONFIG_TSEC3_NAME       "eTSEC3"
 721
 722 #define TSEC1_PHY_ADDR  2
 723 #define TSEC2_PHY_ADDR  0
 724 #define TSEC3_PHY_ADDR  1
 725
 726 #define TSEC1_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 727 #define TSEC2_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 728 #define TSEC3_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 729
 730 #define TSEC1_PHYIDX    0
 731 #define TSEC2_PHYIDX    0
 732 #define TSEC3_PHYIDX    0
 733
 734 #define CONFIG_ETHPRIME "eTSEC1"
 735
 736 #define CONFIG_PHY_GIGE 1       /* Include GbE speed/duplex detection */
 737
 738 #define CONFIG_HAS_ETH0
 739 #define CONFIG_HAS_ETH1
 740 #define CONFIG_HAS_ETH2
 741 #endif /* CONFIG_TSEC_ENET */
 742
 743 #ifdef CONFIG_QE
 744 /* QE microcode/firmware address */
 745 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 746 #define CONFIG_SYS_QE_FW_ADDR   0xefec0000
 747 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 748 #endif /* CONFIG_QE */
 749
 750 #ifdef CONFIG_TARGET_P1025RDB
 751 /*
 752  * QE UEC ethernet configuration
 753  */
 754 #define CONFIG_MIIM_ADDRESS     (CONFIG_SYS_CCSRBAR + 0x82120)
 755
 756 #undef CONFIG_UEC_ETH
 757 #define CONFIG_PHY_MODE_NEED_CHANGE
 758
 759 #define CONFIG_UEC_ETH1 /* ETH1 */
 760 #define CONFIG_HAS_ETH0
 761
 762 #ifdef CONFIG_UEC_ETH1
 763 #define CONFIG_SYS_UEC1_UCC_NUM 0       /* UCC1 */
 764 #define CONFIG_SYS_UEC1_RX_CLK  QE_CLK12 /* CLK12 for MII */
 765 #define CONFIG_SYS_UEC1_TX_CLK  QE_CLK9 /* CLK9 for MII */
 766 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 767 #define CONFIG_SYS_UEC1_PHY_ADDR        0x0     /* 0x0 for MII */
 768 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 769 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 770 #endif /* CONFIG_UEC_ETH1 */
 771
 772 #define CONFIG_UEC_ETH5 /* ETH5 */
 773 #define CONFIG_HAS_ETH1
 774
 775 #ifdef CONFIG_UEC_ETH5
 776 #define CONFIG_SYS_UEC5_UCC_NUM 4       /* UCC5 */
 777 #define CONFIG_SYS_UEC5_RX_CLK  QE_CLK_NONE
 778 #define CONFIG_SYS_UEC5_TX_CLK  QE_CLK13 /* CLK 13 for RMII */
 779 #define CONFIG_SYS_UEC5_ETH_TYPE        FAST_ETH
 780 #define CONFIG_SYS_UEC5_PHY_ADDR        0x3     /* 0x3 for RMII */
 781 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 782 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
 783 #endif /* CONFIG_UEC_ETH5 */
 784 #endif /* CONFIG_TARGET_P1025RDB */
 785
 786 /*
 787  * Environment
 788  */
 789 #ifdef CONFIG_SPIFLASH
 790 #define CONFIG_ENV_IS_IN_SPI_FLASH
 791 #define CONFIG_ENV_SPI_BUS      0
 792 #define CONFIG_ENV_SPI_CS       0
 793 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 794 #define CONFIG_ENV_SPI_MODE     0
 795 #define CONFIG_ENV_SIZE         0x2000  /* 8KB */
 796 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 797 #define CONFIG_ENV_SECT_SIZE    0x10000
 798 #elif defined(CONFIG_SDCARD)
 799 #define CONFIG_ENV_IS_IN_MMC
 800 #define CONFIG_FSL_FIXED_MMC_LOCATION
 801 #define CONFIG_ENV_SIZE         0x2000
 802 #define CONFIG_SYS_MMC_ENV_DEV  0
 803 #elif defined(CONFIG_NAND)
 804 #ifdef CONFIG_TPL_BUILD
 805 #define CONFIG_ENV_SIZE         0x2000
 806 #define CONFIG_ENV_ADDR         (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 807 #else
 808 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 809 #endif
 810 #define CONFIG_ENV_IS_IN_NAND
 811 #define CONFIG_ENV_OFFSET       (1024 * 1024)
 812 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE)
 813 #elif defined(CONFIG_SYS_RAMBOOT)
 814 #define CONFIG_ENV_IS_NOWHERE   /* Store ENV in memory only */
 815 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 816 #define CONFIG_ENV_SIZE         0x2000
 817 #else
 818 #define CONFIG_ENV_IS_IN_FLASH
 819 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 820 #define CONFIG_ENV_SIZE         0x2000
 821 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 822 #endif
 823
 824 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 825 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 826
 827 /*
 828  * Command line configuration.
 829  */
 830 #define CONFIG_CMD_IRQ
 831 #define CONFIG_CMD_DATE
 832 #define CONFIG_CMD_REGINFO
 833
 834 /*
 835  * USB
 836  */
 837 #define CONFIG_HAS_FSL_DR_USB
 838
 839 #if defined(CONFIG_HAS_FSL_DR_USB)
 840 #define CONFIG_USB_EHCI
 841
 842 #ifdef CONFIG_USB_EHCI
 843 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 844 #define CONFIG_USB_EHCI_FSL
 845 #endif
 846 #endif
 847
 848 #if defined(CONFIG_TARGET_P1020RDB_PD)
 849 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
 850 #endif
 851
 852 #define CONFIG_MMC
 853
 854 #ifdef CONFIG_MMC
 855 #define CONFIG_FSL_ESDHC
 856 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 857 #define CONFIG_GENERIC_MMC
 858 #endif
 859
 860 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
 861                  || defined(CONFIG_FSL_SATA)
 862 #define CONFIG_DOS_PARTITION
 863 #endif
 864
 865 #undef CONFIG_WATCHDOG  /* watchdog disabled */
 866
 867 /*
 868  * Miscellaneous configurable options
 869  */
 870 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 871 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 872 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 873 #if defined(CONFIG_CMD_KGDB)
 874 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 875 #else
 876 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 877 #endif
 878 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 879         /* Print Buffer Size */
 880 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 881 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 882
 883 /*
 884  * For booting Linux, the board info and command line data
 885  * have to be in the first 64 MB of memory, since this is
 886  * the maximum mapped by the Linux kernel during initialization.
 887  */
 888 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux*/
 889 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 890
 891 #if defined(CONFIG_CMD_KGDB)
 892 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 893 #endif
 894
 895 /*
 896  * Environment Configuration
 897  */
 898 #define CONFIG_HOSTNAME         unknown
 899 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 900 #define CONFIG_BOOTFILE         "uImage"
 901 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 902
 903 /* default location for tftp and bootm */
 904 #define CONFIG_LOADADDR 1000000
 905
 906 #define CONFIG_BOOTARGS /* the boot command will set bootargs */
 907
 908 #define CONFIG_BAUDRATE 115200
 909
 910 #ifdef __SW_BOOT_NOR
 911 #define __NOR_RST_CMD   \
 912 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
 913 i2c mw 18 3 __SW_BOOT_MASK 1; reset
 914 #endif
 915 #ifdef __SW_BOOT_SPI
 916 #define __SPI_RST_CMD   \
 917 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
 918 i2c mw 18 3 __SW_BOOT_MASK 1; reset
 919 #endif
 920 #ifdef __SW_BOOT_SD
 921 #define __SD_RST_CMD    \
 922 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
 923 i2c mw 18 3 __SW_BOOT_MASK 1; reset
 924 #endif
 925 #ifdef __SW_BOOT_NAND
 926 #define __NAND_RST_CMD  \
 927 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
 928 i2c mw 18 3 __SW_BOOT_MASK 1; reset
 929 #endif
 930 #ifdef __SW_BOOT_PCIE
 931 #define __PCIE_RST_CMD  \
 932 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
 933 i2c mw 18 3 __SW_BOOT_MASK 1; reset
 934 #endif
 935
 936 #define CONFIG_EXTRA_ENV_SETTINGS       \
 937 "netdev=eth0\0" \
 938 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"     \
 939 "loadaddr=1000000\0"    \
 940 "bootfile=uImage\0"     \
 941 "tftpflash=tftpboot $loadaddr $uboot; " \
 942         "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 943         "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "      \
 944         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
 945         "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 946         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
 947 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"    \
 948 "consoledev=ttyS0\0"    \
 949 "ramdiskaddr=2000000\0" \
 950 "ramdiskfile=rootfs.ext2.gz.uboot\0"    \
 951 "fdtaddr=1e00000\0"     \
 952 "bdev=sda1\0" \
 953 "jffs2nor=mtdblock3\0"  \
 954 "norbootaddr=ef080000\0"        \
 955 "norfdtaddr=ef040000\0" \
 956 "jffs2nand=mtdblock9\0" \
 957 "nandbootaddr=100000\0" \
 958 "nandfdtaddr=80000\0"           \
 959 "ramdisk_size=120000\0" \
 960 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
 961 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
 962 __stringify(__NOR_RST_CMD)"\0" \
 963 __stringify(__SPI_RST_CMD)"\0" \
 964 __stringify(__SD_RST_CMD)"\0" \
 965 __stringify(__NAND_RST_CMD)"\0" \
 966 __stringify(__PCIE_RST_CMD)"\0"
 967
 968 #define CONFIG_NFSBOOTCOMMAND   \
 969 "setenv bootargs root=/dev/nfs rw "     \
 970 "nfsroot=$serverip:$rootpath "  \
 971 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 972 "console=$consoledev,$baudrate $othbootargs;" \
 973 "tftp $loadaddr $bootfile;"     \
 974 "tftp $fdtaddr $fdtfile;"       \
 975 "bootm $loadaddr - $fdtaddr"
 976
 977 #define CONFIG_HDBOOT   \
 978 "setenv bootargs root=/dev/$bdev rw rootdelay=30 "      \
 979 "console=$consoledev,$baudrate $othbootargs;" \
 980 "usb start;"    \
 981 "ext2load usb 0:1 $loadaddr /boot/$bootfile;"   \
 982 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"     \
 983 "bootm $loadaddr - $fdtaddr"
 984
 985 #define CONFIG_USB_FAT_BOOT     \
 986 "setenv bootargs root=/dev/ram rw "     \
 987 "console=$consoledev,$baudrate $othbootargs " \
 988 "ramdisk_size=$ramdisk_size;"   \
 989 "usb start;"    \
 990 "fatload usb 0:2 $loadaddr $bootfile;"  \
 991 "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 992 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 993 "bootm $loadaddr $ramdiskaddr $fdtaddr"
 994
 995 #define CONFIG_USB_EXT2_BOOT    \
 996 "setenv bootargs root=/dev/ram rw "     \
 997 "console=$consoledev,$baudrate $othbootargs " \
 998 "ramdisk_size=$ramdisk_size;"   \
 999 "usb start;"    \
1000 "ext2load usb 0:4 $loadaddr $bootfile;" \
1001 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
1002 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
1003 "bootm $loadaddr $ramdiskaddr $fdtaddr"
1004
1005 #define CONFIG_NORBOOT  \
1006 "setenv bootargs root=/dev/$jffs2nor rw "       \
1007 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"  \
1008 "bootm $norbootaddr - $norfdtaddr"
1009
1010 #define CONFIG_RAMBOOTCOMMAND   \
1011 "setenv bootargs root=/dev/ram rw "     \
1012 "console=$consoledev,$baudrate $othbootargs " \
1013 "ramdisk_size=$ramdisk_size;"   \
1014 "tftp $ramdiskaddr $ramdiskfile;"       \
1015 "tftp $loadaddr $bootfile;"     \
1016 "tftp $fdtaddr $fdtfile;"       \
1017 "bootm $loadaddr $ramdiskaddr $fdtaddr"
1018
1019 #define CONFIG_BOOTCOMMAND      CONFIG_HDBOOT
1020
1021 #endif /* __CONFIG_H */