include/configs/p1_p2_rdb_pc.h

   1 /*
   2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * QorIQ RDB boards configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #define CONFIG_DISPLAY_BOARDINFO
  14
  15 #if defined(CONFIG_P1020MBG)
  16 #define CONFIG_BOARDNAME "P1020MBG-PC"
  17 #define CONFIG_P1020
  18 #define CONFIG_VSC7385_ENET
  19 #define CONFIG_SLIC
  20 #define __SW_BOOT_MASK          0x03
  21 #define __SW_BOOT_NOR           0xe4
  22 #define __SW_BOOT_SD            0x54
  23 #define CONFIG_SYS_L2_SIZE      (256 << 10)
  24 #endif
  25
  26 #if defined(CONFIG_P1020UTM)
  27 #define CONFIG_BOARDNAME "P1020UTM-PC"
  28 #define CONFIG_P1020
  29 #define __SW_BOOT_MASK          0x03
  30 #define __SW_BOOT_NOR           0xe0
  31 #define __SW_BOOT_SD            0x50
  32 #define CONFIG_SYS_L2_SIZE      (256 << 10)
  33 #endif
  34
  35 #if defined(CONFIG_P1020RDB_PC)
  36 #define CONFIG_BOARDNAME "P1020RDB-PC"
  37 #define CONFIG_NAND_FSL_ELBC
  38 #define CONFIG_P1020
  39 #define CONFIG_VSC7385_ENET
  40 #define CONFIG_SLIC
  41 #define __SW_BOOT_MASK          0x03
  42 #define __SW_BOOT_NOR           0x5c
  43 #define __SW_BOOT_SPI           0x1c
  44 #define __SW_BOOT_SD            0x9c
  45 #define __SW_BOOT_NAND          0xec
  46 #define __SW_BOOT_PCIE          0x6c
  47 #define CONFIG_SYS_L2_SIZE      (256 << 10)
  48 #endif
  49
  50 /*
  51  * P1020RDB-PD board has user selectable switches for evaluating different
  52  * frequency and boot options for the P1020 device. The table that
  53  * follow describe the available options. The front six binary number was in
  54  * accordance with SW3[1:6].
  55  * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
  56  * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
  57  * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
  58  * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
  59  * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
  60  * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
  61  * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
  62  */
  63 #if defined(CONFIG_P1020RDB_PD)
  64 #define CONFIG_BOARDNAME "P1020RDB-PD"
  65 #define CONFIG_NAND_FSL_ELBC
  66 #define CONFIG_P1020
  67 #define CONFIG_VSC7385_ENET
  68 #define CONFIG_SLIC
  69 #define __SW_BOOT_MASK          0x03
  70 #define __SW_BOOT_NOR           0x64
  71 #define __SW_BOOT_SPI           0x34
  72 #define __SW_BOOT_SD            0x24
  73 #define __SW_BOOT_NAND          0x44
  74 #define __SW_BOOT_PCIE          0x74
  75 #define CONFIG_SYS_L2_SIZE      (256 << 10)
  76 /*
  77  * Dynamic MTD Partition support with mtdparts
  78  */
  79 #define CONFIG_MTD_DEVICE
  80 #define CONFIG_MTD_PARTITIONS
  81 #define CONFIG_CMD_MTDPARTS
  82 #define CONFIG_FLASH_CFI_MTD
  83 #define MTDIDS_DEFAULT "nor0=ec000000.nor"
  84 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \
  85                         "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)"
  86 #endif
  87
  88 #if defined(CONFIG_P1021RDB)
  89 #define CONFIG_BOARDNAME "P1021RDB-PC"
  90 #define CONFIG_NAND_FSL_ELBC
  91 #define CONFIG_P1021
  92 #define CONFIG_QE
  93 #define CONFIG_VSC7385_ENET
  94 #define CONFIG_SYS_LBC_LBCR     0x00080000      /* Implement conversion of
  95                                                 addresses in the LBC */
  96 #define __SW_BOOT_MASK          0x03
  97 #define __SW_BOOT_NOR           0x5c
  98 #define __SW_BOOT_SPI           0x1c
  99 #define __SW_BOOT_SD            0x9c
 100 #define __SW_BOOT_NAND          0xec
 101 #define __SW_BOOT_PCIE          0x6c
 102 #define CONFIG_SYS_L2_SIZE      (256 << 10)
 103 /*
 104  * Dynamic MTD Partition support with mtdparts
 105  */
 106 #define CONFIG_MTD_DEVICE
 107 #define CONFIG_MTD_PARTITIONS
 108 #define CONFIG_CMD_MTDPARTS
 109 #define CONFIG_FLASH_CFI_MTD
 110 #ifdef CONFIG_PHYS_64BIT
 111 #define MTDIDS_DEFAULT "nor0=fef000000.nor"
 112 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \
 113                         "256k(dtb),4608k(kernel),9728k(fs)," \
 114                         "256k(qe-ucode-firmware),1280k(u-boot)"
 115 #else
 116 #define MTDIDS_DEFAULT "nor0=ef000000.nor"
 117 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \
 118                         "256k(dtb),4608k(kernel),9728k(fs)," \
 119                         "256k(qe-ucode-firmware),1280k(u-boot)"
 120 #endif
 121 #endif
 122
 123 #if defined(CONFIG_P1024RDB)
 124 #define CONFIG_BOARDNAME "P1024RDB"
 125 #define CONFIG_NAND_FSL_ELBC
 126 #define CONFIG_P1024
 127 #define CONFIG_SLIC
 128 #define __SW_BOOT_MASK          0xf3
 129 #define __SW_BOOT_NOR           0x00
 130 #define __SW_BOOT_SPI           0x08
 131 #define __SW_BOOT_SD            0x04
 132 #define __SW_BOOT_NAND          0x0c
 133 #define CONFIG_SYS_L2_SIZE      (256 << 10)
 134 #endif
 135
 136 #if defined(CONFIG_P1025RDB)
 137 #define CONFIG_BOARDNAME "P1025RDB"
 138 #define CONFIG_NAND_FSL_ELBC
 139 #define CONFIG_P1025
 140 #define CONFIG_QE
 141 #define CONFIG_SLIC
 142
 143 #define CONFIG_SYS_LBC_LBCR     0x00080000      /* Implement conversion of
 144                                                 addresses in the LBC */
 145 #define __SW_BOOT_MASK          0xf3
 146 #define __SW_BOOT_NOR           0x00
 147 #define __SW_BOOT_SPI           0x08
 148 #define __SW_BOOT_SD            0x04
 149 #define __SW_BOOT_NAND          0x0c
 150 #define CONFIG_SYS_L2_SIZE      (256 << 10)
 151 #endif
 152
 153 #if defined(CONFIG_P2020RDB)
 154 #define CONFIG_BOARDNAME "P2020RDB-PCA"
 155 #define CONFIG_NAND_FSL_ELBC
 156 #define CONFIG_P2020
 157 #define CONFIG_VSC7385_ENET
 158 #define __SW_BOOT_MASK          0x03
 159 #define __SW_BOOT_NOR           0xc8
 160 #define __SW_BOOT_SPI           0x28
 161 #define __SW_BOOT_SD            0x68 /* or 0x18 */
 162 #define __SW_BOOT_NAND          0xe8
 163 #define __SW_BOOT_PCIE          0xa8
 164 #define CONFIG_SYS_L2_SIZE      (512 << 10)
 165 /*
 166  * Dynamic MTD Partition support with mtdparts
 167  */
 168 #define CONFIG_MTD_DEVICE
 169 #define CONFIG_MTD_PARTITIONS
 170 #define CONFIG_CMD_MTDPARTS
 171 #define CONFIG_FLASH_CFI_MTD
 172 #ifdef CONFIG_PHYS_64BIT
 173 #define MTDIDS_DEFAULT "nor0=fef000000.nor"
 174 #define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \
 175                         "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
 176 #else
 177 #define MTDIDS_DEFAULT "nor0=ef000000.nor"
 178 #define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \
 179                         "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)"
 180 #endif
 181 #endif
 182
 183 #ifdef CONFIG_SDCARD
 184 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
 185 #define CONFIG_SPL_SERIAL_SUPPORT
 186 #define CONFIG_SPL_MMC_SUPPORT
 187 #define CONFIG_SPL_MMC_MINIMAL
 188 #define CONFIG_SPL_FLUSH_IMAGE
 189 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
 190 #define CONFIG_FSL_LAW                 /* Use common FSL init code */
 191 #define CONFIG_SYS_TEXT_BASE            0x11001000
 192 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
 193 #define CONFIG_SPL_PAD_TO               0x20000
 194 #define CONFIG_SPL_MAX_SIZE             (128 * 1024)
 195 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
 196 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
 197 #define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
 198 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (128 << 10)
 199 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 200 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
 201 #define CONFIG_SPL_MMC_BOOT
 202 #ifdef CONFIG_SPL_BUILD
 203 #define CONFIG_SPL_COMMON_INIT_DDR
 204 #endif
 205 #endif
 206
 207 #ifdef CONFIG_SPIFLASH
 208 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
 209 #define CONFIG_SPL_SERIAL_SUPPORT
 210 #define CONFIG_SPL_SPI_SUPPORT
 211 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 212 #define CONFIG_SPL_SPI_FLASH_MINIMAL
 213 #define CONFIG_SPL_FLUSH_IMAGE
 214 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
 215 #define CONFIG_FSL_LAW         /* Use common FSL init code */
 216 #define CONFIG_SYS_TEXT_BASE            0x11001000
 217 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
 218 #define CONFIG_SPL_PAD_TO               0x20000
 219 #define CONFIG_SPL_MAX_SIZE             (128 * 1024)
 220 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
 221 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x11000000)
 222 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x11000000)
 223 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (128 << 10)
 224 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 225 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
 226 #define CONFIG_SPL_SPI_BOOT
 227 #ifdef CONFIG_SPL_BUILD
 228 #define CONFIG_SPL_COMMON_INIT_DDR
 229 #endif
 230 #endif
 231
 232 #ifdef CONFIG_NAND
 233 #ifdef CONFIG_TPL_BUILD
 234 #define CONFIG_SPL_NAND_BOOT
 235 #define CONFIG_SPL_FLUSH_IMAGE
 236 #define CONFIG_SPL_NAND_INIT
 237 #define CONFIG_TPL_SERIAL_SUPPORT
 238 #define CONFIG_TPL_NAND_SUPPORT
 239 #define CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT
 240 #define CONFIG_SPL_COMMON_INIT_DDR
 241 #define CONFIG_SPL_MAX_SIZE             (128 << 10)
 242 #define CONFIG_SPL_TEXT_BASE            0xf8f81000
 243 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 244 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (832 << 10)
 245 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x11000000)
 246 #define CONFIG_SYS_NAND_U_BOOT_START    (0x11000000)
 247 #define CONFIG_SYS_NAND_U_BOOT_OFFS     ((128 + 128) << 10)
 248 #elif defined(CONFIG_SPL_BUILD)
 249 #define CONFIG_SPL_INIT_MINIMAL
 250 #define CONFIG_SPL_SERIAL_SUPPORT
 251 #define CONFIG_SPL_NAND_SUPPORT
 252 #define CONFIG_SPL_FLUSH_IMAGE
 253 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
 254 #define CONFIG_SPL_TEXT_BASE            0xff800000
 255 #define CONFIG_SPL_MAX_SIZE             4096
 256 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (128 << 10)
 257 #define CONFIG_SYS_NAND_U_BOOT_DST      0xf8f80000
 258 #define CONFIG_SYS_NAND_U_BOOT_START    0xf8f80000
 259 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (128 << 10)
 260 #endif /* not CONFIG_TPL_BUILD */
 261
 262 #define CONFIG_SPL_PAD_TO               0x20000
 263 #define CONFIG_TPL_PAD_TO               0x20000
 264 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
 265 #define CONFIG_SYS_TEXT_BASE            0x11001000
 266 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 267 #endif
 268
 269 #ifndef CONFIG_SYS_TEXT_BASE
 270 #define CONFIG_SYS_TEXT_BASE            0xeff40000
 271 #endif
 272
 273 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 274 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 275 #endif
 276
 277 #ifndef CONFIG_SYS_MONITOR_BASE
 278 #ifdef CONFIG_SPL_BUILD
 279 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 280 #else
 281 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 282 #endif
 283 #endif
 284
 285 /* High Level Configuration Options */
 286 #define CONFIG_BOOKE
 287 #define CONFIG_E500
 288
 289 #define CONFIG_MP
 290
 291 #define CONFIG_FSL_ELBC
 292 #define CONFIG_PCI
 293 #define CONFIG_PCIE1    /* PCIE controller 1 (slot 1) */
 294 #define CONFIG_PCIE2    /* PCIE controller 2 (slot 2) */
 295 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 296 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 297 #define CONFIG_FSL_PCIE_RESET   /* need PCIe reset errata */
 298 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 299
 300 #define CONFIG_FSL_LAW
 301 #define CONFIG_TSEC_ENET        /* tsec ethernet support */
 302 #define CONFIG_ENV_OVERWRITE
 303
 304 #define CONFIG_CMD_SATA
 305 #define CONFIG_SATA_SIL
 306 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 307 #define CONFIG_LIBATA
 308 #define CONFIG_LBA48
 309
 310 #if defined(CONFIG_P2020RDB)
 311 #define CONFIG_SYS_CLK_FREQ     100000000
 312 #else
 313 #define CONFIG_SYS_CLK_FREQ     66666666
 314 #endif
 315 #define CONFIG_DDR_CLK_FREQ     66666666
 316
 317 #define CONFIG_HWCONFIG
 318 /*
 319  * These can be toggled for performance analysis, otherwise use default.
 320  */
 321 #define CONFIG_L2_CACHE
 322 #define CONFIG_BTB
 323
 324 #define CONFIG_BOARD_EARLY_INIT_F       /* Call board_pre_init */
 325
 326 #define CONFIG_ENABLE_36BIT_PHYS
 327
 328 #ifdef CONFIG_PHYS_64BIT
 329 #define CONFIG_ADDR_MAP                 1
 330 #define CONFIG_SYS_NUM_ADDR_MAP         16      /* number of TLB1 entries */
 331 #endif
 332
 333 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 334 #define CONFIG_SYS_MEMTEST_END          0x1fffffff
 335 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 336
 337 #define CONFIG_SYS_CCSRBAR              0xffe00000
 338 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 339
 340 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
 341        SPL code*/
 342 #ifdef CONFIG_SPL_BUILD
 343 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 344 #endif
 345
 346 /* DDR Setup */
 347 #define CONFIG_SYS_FSL_DDR3
 348 #define CONFIG_SYS_DDR_RAW_TIMING
 349 #define CONFIG_DDR_SPD
 350 #define CONFIG_SYS_SPD_BUS_NUM 1
 351 #define SPD_EEPROM_ADDRESS 0x52
 352 #undef CONFIG_FSL_DDR_INTERACTIVE
 353
 354 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
 355 #define CONFIG_SYS_SDRAM_SIZE_LAW       LAW_SIZE_2G
 356 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 357 #else
 358 #define CONFIG_SYS_SDRAM_SIZE_LAW       LAW_SIZE_1G
 359 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 360 #endif
 361 #define CONFIG_SYS_SDRAM_SIZE           (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
 362 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 363 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 364
 365 #define CONFIG_NUM_DDR_CONTROLLERS      1
 366 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 367
 368 /* Default settings for DDR3 */
 369 #ifndef CONFIG_P2020RDB
 370 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
 371 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
 372 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
 373 #define CONFIG_SYS_DDR_CS1_BNDS         0x0040007f
 374 #define CONFIG_SYS_DDR_CS1_CONFIG       0x80014302
 375 #define CONFIG_SYS_DDR_CS1_CONFIG_2     0x00000000
 376
 377 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 378 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
 379 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
 380 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
 381
 382 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 383 #define CONFIG_SYS_DDR_WRLVL_CONTROL    0x8655A608
 384 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
 385 #define CONFIG_SYS_DDR_RCW_1            0x00000000
 386 #define CONFIG_SYS_DDR_RCW_2            0x00000000
 387 #define CONFIG_SYS_DDR_CONTROL          0xC70C0000      /* Type = DDR3  */
 388 #define CONFIG_SYS_DDR_CONTROL_2        0x04401050
 389 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
 390 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 391
 392 #define CONFIG_SYS_DDR_TIMING_3         0x00020000
 393 #define CONFIG_SYS_DDR_TIMING_0         0x00330004
 394 #define CONFIG_SYS_DDR_TIMING_1         0x6f6B4846
 395 #define CONFIG_SYS_DDR_TIMING_2         0x0FA8C8CF
 396 #define CONFIG_SYS_DDR_CLK_CTRL         0x03000000
 397 #define CONFIG_SYS_DDR_MODE_1           0x40461520
 398 #define CONFIG_SYS_DDR_MODE_2           0x8000c000
 399 #define CONFIG_SYS_DDR_INTERVAL         0x0C300000
 400 #endif
 401
 402 #undef CONFIG_CLOCKS_IN_MHZ
 403
 404 /*
 405  * Memory map
 406  *
 407  * 0x0000_0000 0x7fff_ffff      DDR             Up to 2GB cacheable
 408  * 0x8000_0000 0xdfff_ffff      PCI Express Mem 1.5G non-cacheable(PCIe * 3)
 409  * 0xec00_0000 0xefff_ffff      NOR flash       Up to 64M non-cacheable CS0/1
 410  * 0xf8f8_0000 0xf8ff_ffff      L2 SRAM         Up to 512K cacheable
 411  *   (early boot only)
 412  * 0xff80_0000 0xff80_7fff      NAND flash      32K non-cacheable       CS1/0
 413  * 0xff98_0000 0xff98_ffff      PMC             64K non-cacheable       CS2
 414  * 0xffa0_0000 0xffaf_ffff      CPLD            1M non-cacheable        CS3
 415  * 0xffb0_0000 0xffbf_ffff      VSC7385 switch  1M non-cacheable        CS2
 416  * 0xffc0_0000 0xffc3_ffff      PCI IO range    256k non-cacheable
 417  * 0xffd0_0000 0xffd0_3fff      L1 for stack    16K cacheable
 418  * 0xffe0_0000 0xffef_ffff      CCSR            1M non-cacheable
 419  */
 420
 421 /*
 422  * Local Bus Definitions
 423  */
 424 #if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
 425 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* 64M */
 426 #define CONFIG_SYS_FLASH_BASE           0xec000000
 427 #elif defined(CONFIG_P1020UTM)
 428 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* 32M */
 429 #define CONFIG_SYS_FLASH_BASE           0xee000000
 430 #else
 431 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* 16M */
 432 #define CONFIG_SYS_FLASH_BASE           0xef000000
 433 #endif
 434
 435 #ifdef CONFIG_PHYS_64BIT
 436 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 437 #else
 438 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 439 #endif
 440
 441 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
 442         | BR_PS_16 | BR_V)
 443
 444 #define CONFIG_FLASH_OR_PRELIM  0xfc000ff7
 445
 446 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 447 #define CONFIG_SYS_FLASH_QUIET_TEST
 448 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 449
 450 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 451
 452 #undef CONFIG_SYS_FLASH_CHECKSUM
 453 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 454 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 455
 456 #define CONFIG_FLASH_CFI_DRIVER
 457 #define CONFIG_SYS_FLASH_CFI
 458 #define CONFIG_SYS_FLASH_EMPTY_INFO
 459 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 460
 461 /* Nand Flash */
 462 #ifdef CONFIG_NAND_FSL_ELBC
 463 #define CONFIG_SYS_NAND_BASE            0xff800000
 464 #ifdef CONFIG_PHYS_64BIT
 465 #define CONFIG_SYS_NAND_BASE_PHYS       0xfff800000ull
 466 #else
 467 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 468 #endif
 469
 470 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 471 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 472 #define CONFIG_CMD_NAND
 473 #if defined(CONFIG_P1020RDB_PD)
 474 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 475 #else
 476 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 * 1024)
 477 #endif
 478
 479 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 480         | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 481         | BR_PS_8       /* Port Size = 8 bit */ \
 482         | BR_MS_FCM     /* MSEL = FCM */ \
 483         | BR_V) /* valid */
 484 #if defined(CONFIG_P1020RDB_PD)
 485 #define CONFIG_SYS_NAND_OR_PRELIM       (OR_AM_32KB \
 486         | OR_FCM_PGS    /* Large Page*/ \
 487         | OR_FCM_CSCT \
 488         | OR_FCM_CST \
 489         | OR_FCM_CHT \
 490         | OR_FCM_SCY_1 \
 491         | OR_FCM_TRLX \
 492         | OR_FCM_EHTR)
 493 #else
 494 #define CONFIG_SYS_NAND_OR_PRELIM       (OR_AM_32KB     /* small page */ \
 495         | OR_FCM_CSCT \
 496         | OR_FCM_CST \
 497         | OR_FCM_CHT \
 498         | OR_FCM_SCY_1 \
 499         | OR_FCM_TRLX \
 500         | OR_FCM_EHTR)
 501 #endif
 502 #endif /* CONFIG_NAND_FSL_ELBC */
 503
 504 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 505
 506 #define CONFIG_SYS_INIT_RAM_LOCK
 507 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000 /* stack in RAM */
 508 #ifdef CONFIG_PHYS_64BIT
 509 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 510 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 511 /* The assembler doesn't like typecast */
 512 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 513         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 514           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 515 #else
 516 /* Initial L1 address */
 517 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 518 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 519 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 520 #endif
 521 /* Size of used area in RAM */
 522 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 523
 524 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 525                                         GENERATED_GBL_DATA_SIZE)
 526 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 527
 528 #define CONFIG_SYS_MONITOR_LEN  (768 * 1024)
 529 #define CONFIG_SYS_MALLOC_LEN   (1024 * 1024)/* Reserved for malloc */
 530
 531 #define CONFIG_SYS_CPLD_BASE    0xffa00000
 532 #ifdef CONFIG_PHYS_64BIT
 533 #define CONFIG_SYS_CPLD_BASE_PHYS       0xfffa00000ull
 534 #else
 535 #define CONFIG_SYS_CPLD_BASE_PHYS       CONFIG_SYS_CPLD_BASE
 536 #endif
 537 /* CPLD config size: 1Mb */
 538 #define CONFIG_CPLD_BR_PRELIM   (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
 539                                         BR_PS_8 | BR_V)
 540 #define CONFIG_CPLD_OR_PRELIM   (0xfff009f7)
 541
 542 #define CONFIG_SYS_PMC_BASE     0xff980000
 543 #define CONFIG_SYS_PMC_BASE_PHYS        CONFIG_SYS_PMC_BASE
 544 #define CONFIG_PMC_BR_PRELIM    (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
 545                                         BR_PS_8 | BR_V)
 546 #define CONFIG_PMC_OR_PRELIM    (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
 547                                  OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
 548                                  OR_GPCM_EAD)
 549
 550 #ifdef CONFIG_NAND
 551 #define CONFIG_SYS_BR0_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
 552 #define CONFIG_SYS_OR0_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 553 #define CONFIG_SYS_BR1_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 554 #define CONFIG_SYS_OR1_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 555 #else
 556 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 557 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 558 #ifdef CONFIG_NAND_FSL_ELBC
 559 #define CONFIG_SYS_BR1_PRELIM   CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
 560 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 561 #endif
 562 #endif
 563 #define CONFIG_SYS_BR3_PRELIM   CONFIG_CPLD_BR_PRELIM   /* CPLD Base Address */
 564 #define CONFIG_SYS_OR3_PRELIM   CONFIG_CPLD_OR_PRELIM   /* CPLD Options */
 565
 566 /* Vsc7385 switch */
 567 #ifdef CONFIG_VSC7385_ENET
 568 #define CONFIG_SYS_VSC7385_BASE         0xffb00000
 569
 570 #ifdef CONFIG_PHYS_64BIT
 571 #define CONFIG_SYS_VSC7385_BASE_PHYS    0xfffb00000ull
 572 #else
 573 #define CONFIG_SYS_VSC7385_BASE_PHYS    CONFIG_SYS_VSC7385_BASE
 574 #endif
 575
 576 #define CONFIG_SYS_VSC7385_BR_PRELIM    \
 577         (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
 578 #define CONFIG_SYS_VSC7385_OR_PRELIM    (OR_AM_128KB | OR_GPCM_CSNT | \
 579                         OR_GPCM_XACS |  OR_GPCM_SCY_15 | OR_GPCM_SETA | \
 580                         OR_GPCM_TRLX |  OR_GPCM_EHTR | OR_GPCM_EAD)
 581
 582 #define CONFIG_SYS_BR2_PRELIM   CONFIG_SYS_VSC7385_BR_PRELIM
 583 #define CONFIG_SYS_OR2_PRELIM   CONFIG_SYS_VSC7385_OR_PRELIM
 584
 585 /* The size of the VSC7385 firmware image */
 586 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 587 #endif
 588
 589 /*
 590  * Config the L2 Cache as L2 SRAM
 591 */
 592 #if defined(CONFIG_SPL_BUILD)
 593 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 594 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 595 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 596 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 597 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 598 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
 599 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
 600 #define CONFIG_SPL_RELOC_STACK_SIZE     (32 << 10)
 601 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
 602 #if defined(CONFIG_P2020RDB)
 603 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (364 << 10)
 604 #else
 605 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (108 << 10)
 606 #endif
 607 #elif defined(CONFIG_NAND)
 608 #ifdef CONFIG_TPL_BUILD
 609 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 610 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 611 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 612 #define CONFIG_SPL_RELOC_TEXT_BASE      0xf8f81000
 613 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
 614 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
 615 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (48 << 10)
 616 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
 617 #else
 618 #define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
 619 #define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
 620 #define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
 621 #define CONFIG_SPL_RELOC_TEXT_BASE      (CONFIG_SYS_INIT_L2_END - 0x2000)
 622 #define CONFIG_SPL_RELOC_STACK          ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
 623 #endif /* CONFIG_TPL_BUILD */
 624 #endif
 625 #endif
 626
 627 /* Serial Port - controlled on board with jumper J8
 628  * open - index 2
 629  * shorted - index 1
 630  */
 631 #define CONFIG_CONS_INDEX               1
 632 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 633 #define CONFIG_SYS_NS16550_SERIAL
 634 #define CONFIG_SYS_NS16550_REG_SIZE     1
 635 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 636 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
 637 #define CONFIG_NS16550_MIN_FUNCTIONS
 638 #endif
 639
 640 #define CONFIG_SYS_BAUDRATE_TABLE       \
 641         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 642
 643 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 644 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 645
 646 /* I2C */
 647 #define CONFIG_SYS_I2C
 648 #define CONFIG_SYS_I2C_FSL
 649 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 650 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 651 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 652 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 653 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 654 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 655 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x29} }
 656 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52
 657 #define CONFIG_SYS_SPD_BUS_NUM          1 /* For rom_loc and flash bank */
 658
 659 /*
 660  * I2C2 EEPROM
 661  */
 662 #undef CONFIG_ID_EEPROM
 663
 664 #define CONFIG_RTC_PT7C4338
 665 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 666 #define CONFIG_SYS_I2C_PCA9557_ADDR     0x18
 667
 668 /* enable read and write access to EEPROM */
 669 #define CONFIG_CMD_EEPROM
 670 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 671 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 672 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 673
 674 /*
 675  * eSPI - Enhanced SPI
 676  */
 677 #define CONFIG_HARD_SPI
 678
 679 #if defined(CONFIG_SPI_FLASH)
 680 #define CONFIG_SF_DEFAULT_SPEED 10000000
 681 #define CONFIG_SF_DEFAULT_MODE  0
 682 #endif
 683
 684 #if defined(CONFIG_PCI)
 685 /*
 686  * General PCI
 687  * Memory space is mapped 1-1, but I/O space must start from 0.
 688  */
 689
 690 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 691 #define CONFIG_SYS_PCIE2_NAME           "PCIe SLOT"
 692 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 693 #ifdef CONFIG_PHYS_64BIT
 694 #define CONFIG_SYS_PCIE2_MEM_BUS        0xc0000000
 695 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 696 #else
 697 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 698 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 699 #endif
 700 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 701 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 702 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 703 #ifdef CONFIG_PHYS_64BIT
 704 #define CONFIG_SYS_PCIE2_IO_PHYS        0xfffc10000ull
 705 #else
 706 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 707 #endif
 708 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 709
 710 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 711 #define CONFIG_SYS_PCIE1_NAME           "mini PCIe SLOT"
 712 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 713 #ifdef CONFIG_PHYS_64BIT
 714 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 715 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 716 #else
 717 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 718 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 719 #endif
 720 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 721 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 722 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 723 #ifdef CONFIG_PHYS_64BIT
 724 #define CONFIG_SYS_PCIE1_IO_PHYS        0xfffc00000ull
 725 #else
 726 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
 727 #endif
 728 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 729
 730 #define CONFIG_PCI_PNP  /* do pci plug-and-play */
 731 #define CONFIG_CMD_PCI
 732
 733 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 734 #define CONFIG_DOS_PARTITION
 735 #endif /* CONFIG_PCI */
 736
 737 #if defined(CONFIG_TSEC_ENET)
 738 #define CONFIG_MII              /* MII PHY management */
 739 #define CONFIG_TSEC1
 740 #define CONFIG_TSEC1_NAME       "eTSEC1"
 741 #define CONFIG_TSEC2
 742 #define CONFIG_TSEC2_NAME       "eTSEC2"
 743 #define CONFIG_TSEC3
 744 #define CONFIG_TSEC3_NAME       "eTSEC3"
 745
 746 #define TSEC1_PHY_ADDR  2
 747 #define TSEC2_PHY_ADDR  0
 748 #define TSEC3_PHY_ADDR  1
 749
 750 #define TSEC1_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 751 #define TSEC2_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 752 #define TSEC3_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 753
 754 #define TSEC1_PHYIDX    0
 755 #define TSEC2_PHYIDX    0
 756 #define TSEC3_PHYIDX    0
 757
 758 #define CONFIG_ETHPRIME "eTSEC1"
 759
 760 #define CONFIG_PHY_GIGE 1       /* Include GbE speed/duplex detection */
 761
 762 #define CONFIG_HAS_ETH0
 763 #define CONFIG_HAS_ETH1
 764 #define CONFIG_HAS_ETH2
 765 #endif /* CONFIG_TSEC_ENET */
 766
 767 #ifdef CONFIG_QE
 768 /* QE microcode/firmware address */
 769 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 770 #define CONFIG_SYS_QE_FW_ADDR   0xefec0000
 771 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 772 #endif /* CONFIG_QE */
 773
 774 #ifdef CONFIG_P1025RDB
 775 /*
 776  * QE UEC ethernet configuration
 777  */
 778 #define CONFIG_MIIM_ADDRESS     (CONFIG_SYS_CCSRBAR + 0x82120)
 779
 780 #undef CONFIG_UEC_ETH
 781 #define CONFIG_PHY_MODE_NEED_CHANGE
 782
 783 #define CONFIG_UEC_ETH1 /* ETH1 */
 784 #define CONFIG_HAS_ETH0
 785
 786 #ifdef CONFIG_UEC_ETH1
 787 #define CONFIG_SYS_UEC1_UCC_NUM 0       /* UCC1 */
 788 #define CONFIG_SYS_UEC1_RX_CLK  QE_CLK12 /* CLK12 for MII */
 789 #define CONFIG_SYS_UEC1_TX_CLK  QE_CLK9 /* CLK9 for MII */
 790 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 791 #define CONFIG_SYS_UEC1_PHY_ADDR        0x0     /* 0x0 for MII */
 792 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 793 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 794 #endif /* CONFIG_UEC_ETH1 */
 795
 796 #define CONFIG_UEC_ETH5 /* ETH5 */
 797 #define CONFIG_HAS_ETH1
 798
 799 #ifdef CONFIG_UEC_ETH5
 800 #define CONFIG_SYS_UEC5_UCC_NUM 4       /* UCC5 */
 801 #define CONFIG_SYS_UEC5_RX_CLK  QE_CLK_NONE
 802 #define CONFIG_SYS_UEC5_TX_CLK  QE_CLK13 /* CLK 13 for RMII */
 803 #define CONFIG_SYS_UEC5_ETH_TYPE        FAST_ETH
 804 #define CONFIG_SYS_UEC5_PHY_ADDR        0x3     /* 0x3 for RMII */
 805 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 806 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
 807 #endif /* CONFIG_UEC_ETH5 */
 808 #endif /* CONFIG_P1025RDB */
 809
 810 /*
 811  * Environment
 812  */
 813 #ifdef CONFIG_SPIFLASH
 814 #define CONFIG_ENV_IS_IN_SPI_FLASH
 815 #define CONFIG_ENV_SPI_BUS      0
 816 #define CONFIG_ENV_SPI_CS       0
 817 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 818 #define CONFIG_ENV_SPI_MODE     0
 819 #define CONFIG_ENV_SIZE         0x2000  /* 8KB */
 820 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 821 #define CONFIG_ENV_SECT_SIZE    0x10000
 822 #elif defined(CONFIG_SDCARD)
 823 #define CONFIG_ENV_IS_IN_MMC
 824 #define CONFIG_FSL_FIXED_MMC_LOCATION
 825 #define CONFIG_ENV_SIZE         0x2000
 826 #define CONFIG_SYS_MMC_ENV_DEV  0
 827 #elif defined(CONFIG_NAND)
 828 #ifdef CONFIG_TPL_BUILD
 829 #define CONFIG_ENV_SIZE         0x2000
 830 #define CONFIG_ENV_ADDR         (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 831 #else
 832 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 833 #endif
 834 #define CONFIG_ENV_IS_IN_NAND
 835 #define CONFIG_ENV_OFFSET       (1024 * 1024)
 836 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE)
 837 #elif defined(CONFIG_SYS_RAMBOOT)
 838 #define CONFIG_ENV_IS_NOWHERE   /* Store ENV in memory only */
 839 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 840 #define CONFIG_ENV_SIZE         0x2000
 841 #else
 842 #define CONFIG_ENV_IS_IN_FLASH
 843 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 844 #define CONFIG_ENV_SIZE         0x2000
 845 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 846 #endif
 847
 848 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 849 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 850
 851 /*
 852  * Command line configuration.
 853  */
 854 #define CONFIG_CMD_IRQ
 855 #define CONFIG_CMD_DATE
 856 #define CONFIG_CMD_REGINFO
 857
 858 /*
 859  * USB
 860  */
 861 #define CONFIG_HAS_FSL_DR_USB
 862
 863 #if defined(CONFIG_HAS_FSL_DR_USB)
 864 #define CONFIG_USB_EHCI
 865
 866 #ifdef CONFIG_USB_EHCI
 867 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 868 #define CONFIG_USB_EHCI_FSL
 869 #endif
 870 #endif
 871
 872 #if defined(CONFIG_P1020RDB_PD)
 873 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
 874 #endif
 875
 876 #define CONFIG_MMC
 877
 878 #ifdef CONFIG_MMC
 879 #define CONFIG_FSL_ESDHC
 880 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 881 #define CONFIG_GENERIC_MMC
 882 #endif
 883
 884 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
 885                  || defined(CONFIG_FSL_SATA)
 886 #define CONFIG_DOS_PARTITION
 887 #endif
 888
 889 #undef CONFIG_WATCHDOG  /* watchdog disabled */
 890
 891 /*
 892  * Miscellaneous configurable options
 893  */
 894 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 895 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 896 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 897 #if defined(CONFIG_CMD_KGDB)
 898 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 899 #else
 900 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 901 #endif
 902 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 903         /* Print Buffer Size */
 904 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 905 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 906
 907 /*
 908  * For booting Linux, the board info and command line data
 909  * have to be in the first 64 MB of memory, since this is
 910  * the maximum mapped by the Linux kernel during initialization.
 911  */
 912 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux*/
 913 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 914
 915 #if defined(CONFIG_CMD_KGDB)
 916 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 917 #endif
 918
 919 /*
 920  * Environment Configuration
 921  */
 922 #define CONFIG_HOSTNAME         unknown
 923 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 924 #define CONFIG_BOOTFILE         "uImage"
 925 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 926
 927 /* default location for tftp and bootm */
 928 #define CONFIG_LOADADDR 1000000
 929
 930 #define CONFIG_BOOTARGS /* the boot command will set bootargs */
 931
 932 #define CONFIG_BAUDRATE 115200
 933
 934 #ifdef __SW_BOOT_NOR
 935 #define __NOR_RST_CMD   \
 936 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
 937 i2c mw 18 3 __SW_BOOT_MASK 1; reset
 938 #endif
 939 #ifdef __SW_BOOT_SPI
 940 #define __SPI_RST_CMD   \
 941 spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
 942 i2c mw 18 3 __SW_BOOT_MASK 1; reset
 943 #endif
 944 #ifdef __SW_BOOT_SD
 945 #define __SD_RST_CMD    \
 946 sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
 947 i2c mw 18 3 __SW_BOOT_MASK 1; reset
 948 #endif
 949 #ifdef __SW_BOOT_NAND
 950 #define __NAND_RST_CMD  \
 951 nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
 952 i2c mw 18 3 __SW_BOOT_MASK 1; reset
 953 #endif
 954 #ifdef __SW_BOOT_PCIE
 955 #define __PCIE_RST_CMD  \
 956 pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
 957 i2c mw 18 3 __SW_BOOT_MASK 1; reset
 958 #endif
 959
 960 #define CONFIG_EXTRA_ENV_SETTINGS       \
 961 "netdev=eth0\0" \
 962 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"     \
 963 "loadaddr=1000000\0"    \
 964 "bootfile=uImage\0"     \
 965 "tftpflash=tftpboot $loadaddr $uboot; " \
 966         "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 967         "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "      \
 968         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
 969         "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 970         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
 971 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"    \
 972 "consoledev=ttyS0\0"    \
 973 "ramdiskaddr=2000000\0" \
 974 "ramdiskfile=rootfs.ext2.gz.uboot\0"    \
 975 "fdtaddr=1e00000\0"     \
 976 "bdev=sda1\0" \
 977 "jffs2nor=mtdblock3\0"  \
 978 "norbootaddr=ef080000\0"        \
 979 "norfdtaddr=ef040000\0" \
 980 "jffs2nand=mtdblock9\0" \
 981 "nandbootaddr=100000\0" \
 982 "nandfdtaddr=80000\0"           \
 983 "ramdisk_size=120000\0" \
 984 "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
 985 "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
 986 __stringify(__NOR_RST_CMD)"\0" \
 987 __stringify(__SPI_RST_CMD)"\0" \
 988 __stringify(__SD_RST_CMD)"\0" \
 989 __stringify(__NAND_RST_CMD)"\0" \
 990 __stringify(__PCIE_RST_CMD)"\0"
 991
 992 #define CONFIG_NFSBOOTCOMMAND   \
 993 "setenv bootargs root=/dev/nfs rw "     \
 994 "nfsroot=$serverip:$rootpath "  \
 995 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 996 "console=$consoledev,$baudrate $othbootargs;" \
 997 "tftp $loadaddr $bootfile;"     \
 998 "tftp $fdtaddr $fdtfile;"       \
 999 "bootm $loadaddr - $fdtaddr"
1000
1001 #define CONFIG_HDBOOT   \
1002 "setenv bootargs root=/dev/$bdev rw rootdelay=30 "      \
1003 "console=$consoledev,$baudrate $othbootargs;" \
1004 "usb start;"    \
1005 "ext2load usb 0:1 $loadaddr /boot/$bootfile;"   \
1006 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"     \
1007 "bootm $loadaddr - $fdtaddr"
1008
1009 #define CONFIG_USB_FAT_BOOT     \
1010 "setenv bootargs root=/dev/ram rw "     \
1011 "console=$consoledev,$baudrate $othbootargs " \
1012 "ramdisk_size=$ramdisk_size;"   \
1013 "usb start;"    \
1014 "fatload usb 0:2 $loadaddr $bootfile;"  \
1015 "fatload usb 0:2 $fdtaddr $fdtfile;"    \
1016 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
1017 "bootm $loadaddr $ramdiskaddr $fdtaddr"
1018
1019 #define CONFIG_USB_EXT2_BOOT    \
1020 "setenv bootargs root=/dev/ram rw "     \
1021 "console=$consoledev,$baudrate $othbootargs " \
1022 "ramdisk_size=$ramdisk_size;"   \
1023 "usb start;"    \
1024 "ext2load usb 0:4 $loadaddr $bootfile;" \
1025 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
1026 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
1027 "bootm $loadaddr $ramdiskaddr $fdtaddr"
1028
1029 #define CONFIG_NORBOOT  \
1030 "setenv bootargs root=/dev/$jffs2nor rw "       \
1031 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"  \
1032 "bootm $norbootaddr - $norfdtaddr"
1033
1034 #define CONFIG_RAMBOOTCOMMAND   \
1035 "setenv bootargs root=/dev/ram rw "     \
1036 "console=$consoledev,$baudrate $othbootargs " \
1037 "ramdisk_size=$ramdisk_size;"   \
1038 "tftp $ramdiskaddr $ramdiskfile;"       \
1039 "tftp $loadaddr $bootfile;"     \
1040 "tftp $fdtaddr $fdtfile;"       \
1041 "bootm $loadaddr $ramdiskaddr $fdtaddr"
1042
1043 #define CONFIG_BOOTCOMMAND      CONFIG_HDBOOT
1044
1045 #endif /* __CONFIG_H */