include/configs/p1_twr.h

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * QorIQ P1 Tower boards configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #define CONFIG_DISPLAY_BOARDINFO
  14 #if defined(CONFIG_TWR_P1025)
  15 #define CONFIG_BOARDNAME "TWR-P1025"
  16 #define CONFIG_P1025
  17 #define CONFIG_PHY_ATHEROS
  18 #define CONFIG_QE
  19 #define CONFIG_SYS_LBC_LBCR     0x00080000      /* Conversion of LBC addr */
  20 #define CONFIG_SYS_LBC_LCRR     0x80000002      /* LB clock ratio reg */
  21 #endif
  22
  23 #ifdef CONFIG_SDCARD
  24 #define CONFIG_RAMBOOT_SDCARD
  25 #define CONFIG_SYS_RAMBOOT
  26 #define CONFIG_SYS_EXTRA_ENV_RELOC
  27 #define CONFIG_SYS_TEXT_BASE            0x11000000
  28 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  29 #endif
  30
  31 #ifndef CONFIG_SYS_TEXT_BASE
  32 #define CONFIG_SYS_TEXT_BASE            0xeff40000
  33 #endif
  34
  35 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  36 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  37 #endif
  38
  39 #ifndef CONFIG_SYS_MONITOR_BASE
  40 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  41 #endif
  42
  43 /* High Level Configuration Options */
  44 #define CONFIG_BOOKE
  45 #define CONFIG_E500
  46
  47 #define CONFIG_MP
  48
  49 #define CONFIG_FSL_ELBC
  50 #define CONFIG_PCI
  51 #define CONFIG_PCIE1    /* PCIE controler 1 (slot 1) */
  52 #define CONFIG_PCIE2    /* PCIE controler 2 (slot 2) */
  53 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
  54 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
  55 #define CONFIG_FSL_PCIE_RESET   /* need PCIe reset errata */
  56 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
  57
  58 #define CONFIG_FSL_LAW
  59 #define CONFIG_TSEC_ENET        /* tsec ethernet support */
  60 #define CONFIG_ENV_OVERWRITE
  61
  62 #define CONFIG_CMD_SATA
  63 #define CONFIG_SATA_SIL3114
  64 #define CONFIG_SYS_SATA_MAX_DEVICE      2
  65 #define CONFIG_LIBATA
  66 #define CONFIG_LBA48
  67
  68 #ifndef __ASSEMBLY__
  69 extern unsigned long get_board_sys_clk(unsigned long dummy);
  70 #endif
  71 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /*sysclk for TWR-P1025 */
  72
  73 #define CONFIG_DDR_CLK_FREQ     66666666
  74
  75 #define CONFIG_HWCONFIG
  76 /*
  77  * These can be toggled for performance analysis, otherwise use default.
  78  */
  79 #define CONFIG_L2_CACHE
  80 #define CONFIG_BTB
  81
  82 #define CONFIG_BOARD_EARLY_INIT_F       /* Call board_pre_init */
  83
  84 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  85 #define CONFIG_SYS_MEMTEST_END          0x1fffffff
  86 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
  87
  88 #define CONFIG_SYS_CCSRBAR              0xffe00000
  89 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  90
  91 /* DDR Setup */
  92 #define CONFIG_SYS_FSL_DDR3
  93
  94 #define CONFIG_SYS_SDRAM_SIZE_LAW       LAW_SIZE_512M
  95 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
  96
  97 #define CONFIG_SYS_SDRAM_SIZE           (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
  98 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  99 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 100
 101 #define CONFIG_NUM_DDR_CONTROLLERS      1
 102 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 103
 104 /* Default settings for DDR3 */
 105 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000001f
 106 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
 107 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
 108 #define CONFIG_SYS_DDR_CS1_BNDS         0x00000000
 109 #define CONFIG_SYS_DDR_CS1_CONFIG       0x00000000
 110 #define CONFIG_SYS_DDR_CS1_CONFIG_2     0x00000000
 111
 112 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 113 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
 114 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
 115 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
 116
 117 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 118 #define CONFIG_SYS_DDR_WRLVL_CONTROL    0x8655a608
 119 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
 120 #define CONFIG_SYS_DDR_RCW_1            0x00000000
 121 #define CONFIG_SYS_DDR_RCW_2            0x00000000
 122 #define CONFIG_SYS_DDR_CONTROL          0xc70c0000      /* Type = DDR3  */
 123 #define CONFIG_SYS_DDR_CONTROL_2        0x04401050
 124 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
 125 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
 126
 127 #define CONFIG_SYS_DDR_TIMING_3         0x00020000
 128 #define CONFIG_SYS_DDR_TIMING_0         0x00220004
 129 #define CONFIG_SYS_DDR_TIMING_1         0x5c5b6544
 130 #define CONFIG_SYS_DDR_TIMING_2         0x0fa880de
 131 #define CONFIG_SYS_DDR_CLK_CTRL         0x03000000
 132 #define CONFIG_SYS_DDR_MODE_1           0x80461320
 133 #define CONFIG_SYS_DDR_MODE_2           0x00008000
 134 #define CONFIG_SYS_DDR_INTERVAL         0x09480000
 135
 136 /*
 137  * Memory map
 138  *
 139  * 0x0000_0000 0x1fff_ffff      DDR             Up to 512MB cacheable
 140  * 0x8000_0000 0xdfff_ffff      PCI Express Mem 1.5G non-cacheable(PCIe * 3)
 141  * 0xffc0_0000 0xffc3_ffff      PCI IO range    256k non-cacheable
 142  *
 143  * Localbus
 144  * 0xe000_0000 0xe002_0000      SSD1289         128K non-cacheable
 145  * 0xec00_0000 0xefff_ffff      FLASH           Up to 64M non-cacheable
 146  *
 147  * 0xff90_0000 0xff97_ffff      L2 SRAM         Up to 512K cacheable
 148  * 0xffd0_0000 0xffd0_3fff      init ram        16K Cacheable
 149  * 0xffe0_0000 0xffef_ffff      CCSR            1M non-cacheable
 150  */
 151
 152 /*
 153  * Local Bus Definitions
 154  */
 155 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* 64M */
 156 #define CONFIG_SYS_FLASH_BASE           0xec000000
 157
 158 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 159
 160 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
 161         | BR_PS_16 | BR_V)
 162
 163 #define CONFIG_FLASH_OR_PRELIM  0xfc0000b1
 164
 165 #define CONFIG_SYS_SSD_BASE     0xe0000000
 166 #define CONFIG_SYS_SSD_BASE_PHYS        CONFIG_SYS_SSD_BASE
 167 #define CONFIG_SSD_BR_PRELIM    (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \
 168                                         BR_PS_16 | BR_V)
 169 #define CONFIG_SSD_OR_PRELIM    (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
 170                                  OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \
 171                                  OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 172
 173 #define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM
 174 #define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM
 175
 176 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 177 #define CONFIG_SYS_FLASH_QUIET_TEST
 178 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 179
 180 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 181
 182 #undef CONFIG_SYS_FLASH_CHECKSUM
 183 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 184 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 185
 186 #define CONFIG_FLASH_CFI_DRIVER
 187 #define CONFIG_SYS_FLASH_CFI
 188 #define CONFIG_SYS_FLASH_EMPTY_INFO
 189 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 190
 191 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 192
 193 #define CONFIG_SYS_INIT_RAM_LOCK
 194 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000
 195 /* Initial L1 address */
 196 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 197 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 198 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 199 /* Size of used area in RAM */
 200 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 201
 202 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 203                                         GENERATED_GBL_DATA_SIZE)
 204 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 205
 206 #define CONFIG_SYS_MONITOR_LEN  (768 * 1024)
 207 #define CONFIG_SYS_MALLOC_LEN   (1024 * 1024)/* Reserved for malloc */
 208
 209 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 210 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 211
 212 /* Serial Port
 213  * open - index 2
 214  * shorted - index 1
 215  */
 216 #define CONFIG_CONS_INDEX               1
 217 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 218 #define CONFIG_SYS_NS16550
 219 #define CONFIG_SYS_NS16550_SERIAL
 220 #define CONFIG_SYS_NS16550_REG_SIZE     1
 221 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 222
 223 #define CONFIG_SYS_BAUDRATE_TABLE       \
 224         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 225
 226 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 227 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 228
 229 /* Use the HUSH parser */
 230 #define CONFIG_SYS_HUSH_PARSER
 231 #ifdef CONFIG_SYS_HUSH_PARSER
 232 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 233 #endif
 234
 235 /*
 236  * Pass open firmware flat tree
 237  */
 238 #define CONFIG_OF_LIBFDT
 239 #define CONFIG_OF_BOARD_SETUP
 240 #define CONFIG_OF_STDOUT_VIA_ALIAS
 241
 242 /* new uImage format support */
 243 #define CONFIG_FIT
 244 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
 245
 246 /* I2C */
 247 #define CONFIG_SYS_I2C
 248 #define CONFIG_SYS_I2C_FSL                      /* Use FSL common I2C driver */
 249 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C spd and slave address */
 250 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 251 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 252 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52
 253
 254 /*
 255  * I2C2 EEPROM
 256  */
 257 #define CONFIG_SYS_FSL_I2C2_SPEED       400000  /* I2C spd and slave address */
 258 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 259 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 260
 261 #define CONFIG_SYS_I2C_PCA9555_ADDR     0x23
 262
 263 /* enable read and write access to EEPROM */
 264 #define CONFIG_CMD_EEPROM
 265 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 266 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 267 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 268 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 269
 270 /*
 271  * eSPI - Enhanced SPI
 272  */
 273 #define CONFIG_HARD_SPI
 274 #define CONFIG_FSL_ESPI
 275
 276 #if defined(CONFIG_PCI)
 277 /*
 278  * General PCI
 279  * Memory space is mapped 1-1, but I/O space must start from 0.
 280  */
 281
 282 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 283 #define CONFIG_SYS_PCIE2_NAME           "TWR-ELEV PCIe SLOT"
 284 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 285 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 286 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 287 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 288 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 289 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 290 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 291 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 292
 293 /* controller 1, tgtid 1, Base address a000 */
 294 #define CONFIG_SYS_PCIE1_NAME           "mini PCIe SLOT"
 295 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 296 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 297 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 298 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 299 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 300 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 301 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
 302 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 303
 304 #define CONFIG_PCI_PNP  /* do pci plug-and-play */
 305 #define CONFIG_CMD_PCI
 306
 307 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 308 #define CONFIG_DOS_PARTITION
 309 #endif /* CONFIG_PCI */
 310
 311 #if defined(CONFIG_TSEC_ENET)
 312
 313 #define CONFIG_MII              /* MII PHY management */
 314 #define CONFIG_TSEC1
 315 #define CONFIG_TSEC1_NAME       "eTSEC1"
 316 #undef CONFIG_TSEC2
 317 #undef CONFIG_TSEC2_NAME
 318 #define CONFIG_TSEC3
 319 #define CONFIG_TSEC3_NAME       "eTSEC3"
 320
 321 #define TSEC1_PHY_ADDR  2
 322 #define TSEC2_PHY_ADDR  0
 323 #define TSEC3_PHY_ADDR  1
 324
 325 #define TSEC1_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 326 #define TSEC2_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 327 #define TSEC3_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 328
 329 #define TSEC1_PHYIDX    0
 330 #define TSEC2_PHYIDX    0
 331 #define TSEC3_PHYIDX    0
 332
 333 #define CONFIG_ETHPRIME "eTSEC1"
 334
 335 #define CONFIG_PHY_GIGE 1       /* Include GbE speed/duplex detection */
 336
 337 #define CONFIG_HAS_ETH0
 338 #define CONFIG_HAS_ETH1
 339 #undef CONFIG_HAS_ETH2
 340 #endif /* CONFIG_TSEC_ENET */
 341
 342 #ifdef CONFIG_QE
 343 /* QE microcode/firmware address */
 344 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 345 #define CONFIG_SYS_QE_FW_ADDR   0xefec0000
 346 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 347 #endif /* CONFIG_QE */
 348
 349 #ifdef CONFIG_TWR_P1025
 350 /*
 351  * QE UEC ethernet configuration
 352  */
 353 #define CONFIG_MIIM_ADDRESS     (CONFIG_SYS_CCSRBAR + 0x82120)
 354
 355 #undef CONFIG_UEC_ETH
 356 #define CONFIG_PHY_MODE_NEED_CHANGE
 357
 358 #define CONFIG_UEC_ETH1 /* ETH1 */
 359 #define CONFIG_HAS_ETH0
 360
 361 #ifdef CONFIG_UEC_ETH1
 362 #define CONFIG_SYS_UEC1_UCC_NUM 0       /* UCC1 */
 363 #define CONFIG_SYS_UEC1_RX_CLK  QE_CLK12 /* CLK12 for MII */
 364 #define CONFIG_SYS_UEC1_TX_CLK  QE_CLK9 /* CLK9 for MII */
 365 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 366 #define CONFIG_SYS_UEC1_PHY_ADDR        0x18    /* 0x18 for MII */
 367 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
 368 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 369 #endif /* CONFIG_UEC_ETH1 */
 370
 371 #define CONFIG_UEC_ETH5 /* ETH5 */
 372 #define CONFIG_HAS_ETH1
 373
 374 #ifdef CONFIG_UEC_ETH5
 375 #define CONFIG_SYS_UEC5_UCC_NUM 4       /* UCC5 */
 376 #define CONFIG_SYS_UEC5_RX_CLK  QE_CLK_NONE
 377 #define CONFIG_SYS_UEC5_TX_CLK  QE_CLK13 /* CLK 13 for RMII */
 378 #define CONFIG_SYS_UEC5_ETH_TYPE        FAST_ETH
 379 #define CONFIG_SYS_UEC5_PHY_ADDR        0x19    /* 0x19 for RMII */
 380 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 381 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
 382 #endif /* CONFIG_UEC_ETH5 */
 383 #endif /* CONFIG_TWR-P1025 */
 384
 385 /*
 386  * Dynamic MTD Partition support with mtdparts
 387  */
 388 #define CONFIG_MTD_DEVICE
 389 #define CONFIG_MTD_PARTITIONS
 390 #define CONFIG_CMD_MTDPARTS
 391 #define CONFIG_FLASH_CFI_MTD
 392 #define MTDIDS_DEFAULT "nor0=ec000000.nor"
 393 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:256k(vsc7385-firmware)," \
 394                         "256k(dtb),5632k(kernel),57856k(fs)," \
 395                         "256k(qe-ucode-firmware),1280k(u-boot)"
 396
 397 /*
 398  * Environment
 399  */
 400 #ifdef CONFIG_SYS_RAMBOOT
 401 #ifdef CONFIG_RAMBOOT_SDCARD
 402 #define CONFIG_ENV_IS_IN_MMC
 403 #define CONFIG_ENV_SIZE         0x2000
 404 #define CONFIG_SYS_MMC_ENV_DEV  0
 405 #else
 406 #define CONFIG_ENV_IS_NOWHERE   /* Store ENV in memory only */
 407 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 408 #define CONFIG_ENV_SIZE         0x2000
 409 #endif
 410 #else
 411 #define CONFIG_ENV_IS_IN_FLASH
 412 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 413 #define CONFIG_ENV_SIZE         0x2000
 414 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 415 #endif
 416
 417 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 418 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 419
 420 /*
 421  * Command line configuration.
 422  */
 423 #define CONFIG_CMD_IRQ
 424 #define CONFIG_CMD_PING
 425 #define CONFIG_CMD_I2C
 426 #define CONFIG_CMD_MII
 427 #define CONFIG_CMD_REGINFO
 428
 429 /*
 430  * USB
 431  */
 432 #define CONFIG_HAS_FSL_DR_USB
 433
 434 #if defined(CONFIG_HAS_FSL_DR_USB)
 435 #define CONFIG_USB_EHCI
 436
 437 #ifdef CONFIG_USB_EHCI
 438 #define CONFIG_CMD_USB
 439 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 440 #define CONFIG_USB_EHCI_FSL
 441 #define CONFIG_USB_STORAGE
 442 #endif
 443 #endif
 444
 445 #define CONFIG_MMC
 446
 447 #ifdef CONFIG_MMC
 448 #define CONFIG_FSL_ESDHC
 449 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 450 #define CONFIG_CMD_MMC
 451 #define CONFIG_GENERIC_MMC
 452 #endif
 453
 454 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
 455                  || defined(CONFIG_FSL_SATA)
 456 #define CONFIG_CMD_EXT2
 457 #define CONFIG_CMD_FAT
 458 #define CONFIG_DOS_PARTITION
 459 #endif
 460
 461 #undef CONFIG_WATCHDOG  /* watchdog disabled */
 462
 463 /*
 464  * Miscellaneous configurable options
 465  */
 466 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 467 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 468 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 469 #if defined(CONFIG_CMD_KGDB)
 470 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 471 #else
 472 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 473 #endif
 474 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 475         /* Print Buffer Size */
 476 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 477 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 478
 479 /*
 480  * For booting Linux, the board info and command line data
 481  * have to be in the first 64 MB of memory, since this is
 482  * the maximum mapped by the Linux kernel during initialization.
 483  */
 484 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux*/
 485 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 486
 487 /*
 488  * Environment Configuration
 489  */
 490 #define CONFIG_HOSTNAME         unknown
 491 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 492 #define CONFIG_BOOTFILE         "uImage"
 493 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 494
 495 /* default location for tftp and bootm */
 496 #define CONFIG_LOADADDR 1000000
 497
 498 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 499 #define CONFIG_BOOTARGS /* the boot command will set bootargs */
 500
 501 #define CONFIG_BAUDRATE 115200
 502
 503 #define CONFIG_EXTRA_ENV_SETTINGS       \
 504 "netdev=eth0\0" \
 505 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"     \
 506 "loadaddr=1000000\0"    \
 507 "bootfile=uImage\0"     \
 508 "dtbfile=twr-p1025twr.dtb\0"    \
 509 "ramdiskfile=rootfs.ext2.gz.uboot\0"    \
 510 "qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0"   \
 511 "tftpflash=tftpboot $loadaddr $uboot; " \
 512         "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 513         "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "      \
 514         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
 515         "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 516         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
 517 "kernelflash=tftpboot $loadaddr $bootfile; "    \
 518         "protect off 0xefa80000 +$filesize; "   \
 519         "erase 0xefa80000 +$filesize; " \
 520         "cp.b $loadaddr 0xefa80000 $filesize; " \
 521         "protect on 0xefa80000 +$filesize; "    \
 522         "cmp.b $loadaddr 0xefa80000 $filesize\0"        \
 523 "dtbflash=tftpboot $loadaddr $dtbfile; "        \
 524         "protect off 0xefe80000 +$filesize; "   \
 525         "erase 0xefe80000 +$filesize; " \
 526         "cp.b $loadaddr 0xefe80000 $filesize; " \
 527         "protect on 0xefe80000 +$filesize; "    \
 528         "cmp.b $loadaddr 0xefe80000 $filesize\0"        \
 529 "ramdiskflash=tftpboot $loadaddr $ramdiskfile; "        \
 530         "protect off 0xeeb80000 +$filesize; "   \
 531         "erase 0xeeb80000 +$filesize; " \
 532         "cp.b $loadaddr 0xeeb80000 $filesize; " \
 533         "protect on 0xeeb80000 +$filesize; "    \
 534         "cmp.b $loadaddr 0xeeb80000 $filesize\0"        \
 535 "qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; "  \
 536         "protect off 0xefec0000 +$filesize; "   \
 537         "erase 0xefec0000 +$filesize; " \
 538         "cp.b $loadaddr 0xefec0000 $filesize; " \
 539         "protect on 0xefec0000 +$filesize; "    \
 540         "cmp.b $loadaddr 0xefec0000 $filesize\0"        \
 541 "consoledev=ttyS0\0"    \
 542 "ramdiskaddr=2000000\0" \
 543 "ramdiskfile=rootfs.ext2.gz.uboot\0"    \
 544 "fdtaddr=c00000\0"      \
 545 "bdev=sda1\0"   \
 546 "norbootaddr=ef080000\0"        \
 547 "norfdtaddr=ef040000\0" \
 548 "ramdisk_size=120000\0" \
 549 "usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \
 550 "console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000"
 551
 552 #define CONFIG_NFSBOOTCOMMAND   \
 553 "setenv bootargs root=/dev/nfs rw "     \
 554 "nfsroot=$serverip:$rootpath "  \
 555 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 556 "console=$consoledev,$baudrate $othbootargs;" \
 557 "tftp $loadaddr $bootfile&&"    \
 558 "tftp $fdtaddr $fdtfile&&"      \
 559 "bootm $loadaddr - $fdtaddr"
 560
 561 #define CONFIG_HDBOOT   \
 562 "setenv bootargs root=/dev/$bdev rw rootdelay=30 "      \
 563 "console=$consoledev,$baudrate $othbootargs;" \
 564 "usb start;"    \
 565 "ext2load usb 0:1 $loadaddr /boot/$bootfile;"   \
 566 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"     \
 567 "bootm $loadaddr - $fdtaddr"
 568
 569 #define CONFIG_USB_FAT_BOOT     \
 570 "setenv bootargs root=/dev/ram rw "     \
 571 "console=$consoledev,$baudrate $othbootargs " \
 572 "ramdisk_size=$ramdisk_size;"   \
 573 "usb start;"    \
 574 "fatload usb 0:2 $loadaddr $bootfile;"  \
 575 "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 576 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 577 "bootm $loadaddr $ramdiskaddr $fdtaddr"
 578
 579 #define CONFIG_USB_EXT2_BOOT    \
 580 "setenv bootargs root=/dev/ram rw "     \
 581 "console=$consoledev,$baudrate $othbootargs " \
 582 "ramdisk_size=$ramdisk_size;"   \
 583 "usb start;"    \
 584 "ext2load usb 0:4 $loadaddr $bootfile;" \
 585 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
 586 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
 587 "bootm $loadaddr $ramdiskaddr $fdtaddr"
 588
 589 #define CONFIG_NORBOOT  \
 590 "setenv bootargs root=/dev/mtdblock3 rw "       \
 591 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"  \
 592 "bootm $norbootaddr - $norfdtaddr"
 593
 594 #define CONFIG_RAMBOOTCOMMAND_TFTP      \
 595 "setenv bootargs root=/dev/ram rw "     \
 596 "console=$consoledev,$baudrate $othbootargs " \
 597 "ramdisk_size=$ramdisk_size;"   \
 598 "tftp $ramdiskaddr $ramdiskfile;"       \
 599 "tftp $loadaddr $bootfile;"     \
 600 "tftp $fdtaddr $fdtfile;"       \
 601 "bootm $loadaddr $ramdiskaddr $fdtaddr"
 602
 603 #define CONFIG_RAMBOOTCOMMAND   \
 604 "setenv bootargs root=/dev/ram rw "     \
 605 "console=$consoledev,$baudrate $othbootargs " \
 606 "ramdisk_size=$ramdisk_size;"   \
 607 "bootm 0xefa80000 0xeeb80000 0xefe80000"
 608
 609 #define CONFIG_BOOTCOMMAND      CONFIG_RAMBOOTCOMMAND
 610
 611 #endif /* __CONFIG_H */