include/configs/p3p440.h

   1 /*
   2  * (C) Copyright 2005-2006
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 /************************************************************************
  27  * board/config_p3p440.h - configuration for Prodrive P3P440
  28  ***********************************************************************/
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 /*-----------------------------------------------------------------------
  34  * High Level Configuration Options
  35  *----------------------------------------------------------------------*/
  36 #define CONFIG_P3P440           1           /* Board is P3P440          */
  37 #define CONFIG_440GP            1           /* Specifc GP support       */
  38 #define CONFIG_440              1           /* ... PPC440 family        */
  39 #define CONFIG_4xx              1           /* ... PPC4xx family        */
  40 #define CONFIG_BOARD_EARLY_INIT_F 1         /* Call board_early_init_f  */
  41 #define CONFIG_MISC_INIT_R      1           /* Call misc_init_r         */
  42 #define CONFIG_SYS_CLK_FREQ     33333333    /* external freq to pll     */
  43
  44 /*-----------------------------------------------------------------------
  45  * Base addresses -- Note these are effective addresses where the
  46  * actual resources get mapped (not physical addresses)
  47  *----------------------------------------------------------------------*/
  48 #define CFG_SDRAM_BASE      0x00000000      /* _must_ be 0              */
  49 #define CFG_FLASH_BASE      0xff800000      /* start of FLASH           */
  50 #define CFG_MONITOR_BASE    0xfffc0000      /* start of monitor         */
  51 #define CFG_PCI_MEMBASE     0x80000000      /* mapped pci memory        */
  52 #define CFG_PERIPHERAL_BASE 0xe0000000      /* internal peripherals     */
  53 #define CFG_ISRAM_BASE      0xc0000000      /* internal SRAM            */
  54 #define CFG_PCI_BASE        0xd0000000      /* internal PCI regs        */
  55
  56 #define CFG_USB_BASE        (CFG_PERIPHERAL_BASE + 0x00000000)
  57
  58 /*-----------------------------------------------------------------------
  59  * Initial RAM & stack pointer (placed in internal SRAM)
  60  *----------------------------------------------------------------------*/
  61 #define CFG_INIT_RAM_ADDR       CFG_ISRAM_BASE  /* Initial RAM address  */
  62 #define CFG_INIT_RAM_END        0x2000      /* End of used area in RAM  */
  63 #define CFG_GBL_DATA_SIZE       128         /* num bytes initial data   */
  64
  65 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  66 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
  67
  68 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Mon*/
  69 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserve 128 kB for malloc*/
  70
  71 /*-----------------------------------------------------------------------
  72  * DDR SDRAM
  73  *----------------------------------------------------------------------*/
  74 #define CONFIG_SDRAM_BANK0      1       /* init onboard DDR SDRAM bank 0*/
  75 #define CONFIG_SDRAM_ECC                /* enable ECC support           */
  76 #define CFG_SDRAM_TABLE { \
  77                 {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
  78                 {(64 << 20),  12, 0x00082001}} /* 64MB mode 2, 12x9(4)  */
  79
  80 /*-----------------------------------------------------------------------
  81  * Serial Port
  82  *----------------------------------------------------------------------*/
  83 #undef CFG_EXT_SERIAL_CLOCK
  84 #define CONFIG_BAUDRATE         115200
  85
  86 #define CFG_BAUDRATE_TABLE                                              \
  87         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,               \
  88                         57600, 115200, 230400, 460800, 921600 }
  89
  90 /*-----------------------------------------------------------------------
  91  * I2C
  92  *----------------------------------------------------------------------*/
  93 #define CONFIG_HARD_I2C         1       /* I2C with hardware support    */
  94 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
  95 #define CFG_I2C_SPEED           100000  /* I2C speed and slave address  */
  96 #define CFG_I2C_SLAVE           0x7F
  97 #define CFG_I2C_NOPROBES        {0x69}  /* Don't probe these addrs      */
  98
  99 /*-----------------------------------------------------------------------
 100  * I2C RTC
 101  *----------------------------------------------------------------------*/
 102 #define CONFIG_RTC_MAX6900      1               /* MAX6900 RTC          */
 103
 104 /*-----------------------------------------------------------------------
 105  * I2C EEPROM (PCF8594C) for environment
 106  *----------------------------------------------------------------------*/
 107 #define CFG_I2C_EEPROM_ADDR     0x54    /* EEPROM PCF8594C              */
 108 #define CFG_I2C_EEPROM_ADDR_LEN 1       /* Bytes of address             */
 109 /* mask of address bits that overflow into the "EEPROM chip address"    */
 110 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x07
 111 #define CFG_EEPROM_PAGE_WRITE_BITS 3    /* The Philips PCF8594C has     */
 112                                         /* 8 byte page write mode using */
 113                                         /* last 3 bits of the address   */
 114 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  40   /* and takes up to 40 msec */
 115 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 116
 117 /*-----------------------------------------------------------------------
 118  * Default configuration (environment varibles...)
 119  *----------------------------------------------------------------------*/
 120 #define CONFIG_PREBOOT  "echo;" \
 121         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 122         "echo"
 123
 124 #undef  CONFIG_BOOTARGS
 125
 126 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 127         "netdev=eth0\0"                                                 \
 128         "hostname=p3p440\0"                                             \
 129         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 130                 "nfsroot=${serverip}:${rootpath}\0"                     \
 131         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 132         "addip=setenv bootargs ${bootargs} "                            \
 133                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 134                 ":${hostname}:${netdev}:off panic=1\0"                  \
 135         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 136         "flash_nfs=run nfsargs addip addtty;"                           \
 137                 "bootm ${kernel_addr}\0"                                \
 138         "flash_self=run ramargs addip addtty;"                          \
 139                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 140         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 141                 "bootm\0"                                               \
 142         "rootpath=/opt/eldk/ppc_4xx\0"                                  \
 143         "bootfile=/tftpboot/p3p440/uImage\0"                            \
 144         "kernel_addr=ff800000\0"                                        \
 145         "ramdisk_addr=ff810000\0"                                       \
 146         "load=tftp 100000 /tftpboot/p3p440/u-boot.bin\0"                \
 147         "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"   \
 148                 "cp.b 100000 fffc0000 40000;"                           \
 149                 "setenv filesize;saveenv\0"                             \
 150         "upd=run load;run update\0"                                     \
 151         "unlock=yes\0"                                                  \
 152         ""
 153 #define CONFIG_BOOTCOMMAND      "run net_nfs"
 154
 155 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 156
 157 #define CONFIG_BAUDRATE         115200
 158
 159 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 160 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 161
 162 #define CONFIG_MII              1       /* MII PHY management           */
 163 #define CONFIG_PHY_ADDR         0x1c    /* PHY address                  */
 164 #define CONFIG_HAS_ETH1
 165 #define CONFIG_PHY1_ADDR        0x1d    /* EMAC1 PHY address            */
 166 #define CONFIG_NET_MULTI        1
 167 #define CFG_RX_ETH_BUFFER       32      /* Number of ethernet rx buffers & descriptors */
 168
 169 #define CONFIG_NETCONSOLE               /* include NetConsole support   */
 170
 171
 172 /*
 173  * Command line configuration.
 174  */
 175 #include <config_cmd_default.h>
 176
 177 #define CONFIG_CMD_ASKENV
 178 #define CONFIG_CMD_DATE
 179 #define CONFIG_CMD_DHCP
 180 #define CONFIG_CMD_DIAG
 181 #define CONFIG_CMD_ELF
 182 #define CONFIG_CMD_I2C
 183 #define CONFIG_CMD_IRQ
 184 #define CONFIG_CMD_MII
 185 #define CONFIG_CMD_NET
 186 #define CONFIG_CMD_NFS
 187 #define CONFIG_CMD_PCI
 188 #define CONFIG_CMD_PING
 189 #define CONFIG_CMD_REGINFO
 190 #define CONFIG_CMD_EEPROM
 191 #define CONFIG_CMD_SNTP
 192
 193
 194 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 195
 196 /*-----------------------------------------------------------------------
 197  * Miscellaneous configurable options
 198  *----------------------------------------------------------------------*/
 199 #define CFG_LONGHELP                    /* undef to save memory         */
 200 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 201 #if defined(CONFIG_CMD_KGDB)
 202 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 203 #else
 204 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 205 #endif
 206 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 207 #define CFG_MAXARGS     16              /* max number of command args   */
 208 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 209
 210 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 211 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 212
 213 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 214 #define CFG_EXTBDINFO           1       /* To use extended board_into (bd_t) */
 215
 216 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 217
 218 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
 219 #define CONFIG_LOOPW            1       /* enable loopw command         */
 220 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 221 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 222
 223 /*-----------------------------------------------------------------------
 224  * PCI stuff
 225  *----------------------------------------------------------------------*/
 226 /* General PCI */
 227 #define CONFIG_PCI                                  /* include pci support              */
 228 #define CONFIG_PCI_PNP                          /* do pci plug-and-play         */
 229 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 230 #define CFG_PCI_TARGBASE    0x80000000  /* PCIaddr mapped to CFG_PCI_MEMBASE */
 231
 232 /* Board-specific PCI */
 233 #define CFG_PCI_TARGET_INIT                 /* let board init pci target    */
 234
 235 #define CONFIG_DISABLE_PISE_TEST        /* disable PISE test (PCIX only)*/
 236
 237 #define CFG_PCI_SUBSYS_VENDORID 0x10e8  /* AMCC */
 238 #define CFG_PCI_SUBSYS_DEVICEID 0xcafe  /* Whatever */
 239
 240 /*-----------------------------------------------------------------------
 241  * External Bus Controller (EBC) Setup
 242  *----------------------------------------------------------------------*/
 243 #define CFG_FLASH0              0xFF800000
 244 #define CFG_FLASH1              0xFF000000
 245 #define CFG_FLASH2              0xFE800000
 246 #define CFG_FLASH3              0xFE000000
 247 #define CFG_USB                 0xF0000000
 248
 249 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 250 #define CFG_EBC_PB0AP           0x03050200
 251 #define CFG_EBC_PB0CR           (CFG_FLASH0 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
 252
 253 /* Memory Bank 1 (Flash Bank 1, NOR-FLASH) initialization                       */
 254 #define CFG_EBC_PB1AP           0x03050200
 255 #define CFG_EBC_PB1CR           (CFG_FLASH1 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
 256
 257 /* Memory Bank 2 (Flash Bank 2, NOR-FLASH) initialization                       */
 258 #define CFG_EBC_PB2AP           0x03050200
 259 #define CFG_EBC_PB2CR           (CFG_FLASH2 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
 260
 261 /* Memory Bank 3 (Flash Bank 3, NOR-FLASH) initialization                       */
 262 #define CFG_EBC_PB3AP           0x03050200
 263 #define CFG_EBC_PB3CR           (CFG_FLASH3 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
 264
 265 /* Memory Bank 7 (USB controller) initialization                                */
 266 #define CFG_EBC_PB7AP           0x02015000
 267 #define CFG_EBC_PB7CR           (CFG_USB | 0xFE000) /* BAS=0xF00,BS=128MB,BU=R/W,BW=16bit*/
 268
 269 /*-----------------------------------------------------------------------
 270  * FLASH related
 271  *----------------------------------------------------------------------*/
 272 #define CFG_FLASH_CFI                           /* The flash is CFI compatible  */
 273 #define CFG_FLASH_CFI_DRIVER                    /* Use common CFI driver        */
 274
 275 #define CFG_FLASH_BANKS_LIST { CFG_FLASH3, CFG_FLASH2, CFG_FLASH1, CFG_FLASH0 }
 276
 277 #define CFG_MAX_FLASH_BANKS     4       /* max number of memory banks           */
 278 #define CFG_MAX_FLASH_SECT      512     /* max number of sectors on one chip    */
 279
 280 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 281 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 282
 283 #define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
 284 #define CFG_FLASH_PROTECTION    1       /* use hardware flash protection        */
 285
 286 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 287 #define CFG_FLASH_QUIET_TEST    1       /* don't warn upon unknown flash        */
 288
 289 #define CFG_ENV_IS_IN_FLASH     1       /* use FLASH for environment vars       */
 290
 291 #define CFG_ENV_SECT_SIZE       0x20000 /* size of one complete sector          */
 292 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
 293 #define CFG_ENV_SIZE            0x2000  /* Total Size of Environment Sector     */
 294
 295 /* Address and size of Redundant Environment Sector     */
 296 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
 297 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 298
 299 /*
 300  * For booting Linux, the board info and command line data
 301  * have to be in the first 8 MB of memory, since this is
 302  * the maximum mapped by the Linux kernel during initialization.
 303  */
 304 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 305 /*-----------------------------------------------------------------------
 306  * Cache Configuration
 307  */
 308 #define CFG_DCACHE_SIZE         (32<<10)        /* For AMCC 405 CPUs            */
 309 #define CFG_CACHELINE_SIZE      32      /* ...                                  */
 310 #if defined(CONFIG_CMD_KGDB)
 311 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value        */
 312 #endif
 313
 314 /*
 315  * Internal Definitions
 316  *
 317  * Boot Flags
 318  */
 319 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 320 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 321
 322 #if defined(CONFIG_CMD_KGDB)
 323 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 324 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 325 #endif
 326 #endif  /* __CONFIG_H */