include/configs/pcs440ep.h

   1 /*
   2  * (C) Copyright 2006
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /************************************************************************
  25  * pcs440ep.h - configuration for PCS440EP board
  26  ***********************************************************************/
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /*-----------------------------------------------------------------------
  31  * High Level Configuration Options
  32  *----------------------------------------------------------------------*/
  33 #define CONFIG_PCS440EP         1       /* Board is PCS440EP            */
  34 #define CONFIG_440EP            1       /* Specific PPC440EP support    */
  35 #define CONFIG_4xx              1       /* ... PPC4xx family            */
  36 #define CONFIG_SYS_CLK_FREQ     33333333    /* external freq to pll     */
  37
  38 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  39 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  40
  41 /*-----------------------------------------------------------------------
  42  * Base addresses -- Note these are effective addresses where the
  43  * actual resources get mapped (not physical addresses)
  44  *----------------------------------------------------------------------*/
  45 #define CFG_MONITOR_LEN         (384 * 1024)    /* Reserve 384 kB for Monitor   */
  46 #define CFG_MALLOC_LEN          (256 * 1024)    /* Reserve 256 kB for malloc()  */
  47 #define CFG_MONITOR_BASE        (-CFG_MONITOR_LEN)
  48 #define CFG_SDRAM_BASE          0x00000000          /* _must_ be 0      */
  49 #define CFG_FLASH_BASE          0xfff00000          /* start of FLASH   */
  50 #define CFG_PCI_MEMBASE         0xa0000000          /* mapped pci memory*/
  51 #define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
  52 #define CFG_PCI_MEMBASE2        CFG_PCI_MEMBASE1 + 0x10000000
  53 #define CFG_PCI_MEMBASE3        CFG_PCI_MEMBASE2 + 0x10000000
  54
  55 /*Don't change either of these*/
  56 #define CFG_PERIPHERAL_BASE     0xef600000          /* internal peripherals*/
  57 #define CFG_PCI_BASE            0xe0000000          /* internal PCI regs*/
  58 /*Don't change either of these*/
  59
  60 #define CFG_USB_DEVICE          0x50000000
  61 #define CFG_BOOT_BASE_ADDR      0xf0000000
  62
  63 /*-----------------------------------------------------------------------
  64  * Initial RAM & stack pointer (placed in SDRAM)
  65  *----------------------------------------------------------------------*/
  66 #define CFG_INIT_RAM_DCACHE     1               /* d-cache as init ram  */
  67 #define CFG_INIT_RAM_ADDR       0x70000000              /* DCache       */
  68 #define CFG_INIT_RAM_END        (8 << 10)
  69 #define CFG_GBL_DATA_SIZE       256                     /* num bytes initial data*/
  70 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  71 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
  72
  73 /*-----------------------------------------------------------------------
  74  * Serial Port
  75  *----------------------------------------------------------------------*/
  76 #undef CFG_EXT_SERIAL_CLOCK             /* no external clk used         */
  77 #define CONFIG_BAUDRATE         115200
  78 #define CONFIG_SERIAL_MULTI     1
  79 /*define this if you want console on UART1*/
  80 #undef CONFIG_UART1_CONSOLE
  81
  82 #define CFG_BAUDRATE_TABLE  \
  83     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  84
  85 /*-----------------------------------------------------------------------
  86  * Environment
  87  *----------------------------------------------------------------------*/
  88 #define CFG_ENV_IS_IN_FLASH     1       /* use FLASH for environment vars       */
  89
  90 /*-----------------------------------------------------------------------
  91  * FLASH related
  92  *----------------------------------------------------------------------*/
  93 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
  94 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
  95
  96 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
  97 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
  98
  99 #define CFG_FLASH_WORD_SIZE     unsigned char   /* flash word size (width)      */
 100 #define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
 101 #define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
 102
 103 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 104
 105 #ifdef CFG_ENV_IS_IN_FLASH
 106 #define CFG_ENV_SECT_SIZE       0x10000         /* size of one complete sector  */
 107 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
 108 #define CFG_ENV_SIZE            0x2000  /* Total Size of Environment Sector     */
 109
 110 /* Address and size of Redundant Environment Sector     */
 111 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
 112 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 113 #endif /* CFG_ENV_IS_IN_FLASH */
 114
 115 /*-----------------------------------------------------------------------
 116  * DDR SDRAM
 117  *----------------------------------------------------------------------*/
 118 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup             */
 119 #undef CONFIG_DDR_ECC                   /* don't use ECC                        */
 120 #define SPD_EEPROM_ADDRESS      {0x50}
 121
 122 /*-----------------------------------------------------------------------
 123  * I2C
 124  *----------------------------------------------------------------------*/
 125 #define CONFIG_HARD_I2C         1           /* I2C with hardware support        */
 126 #undef  CONFIG_SOFT_I2C                     /* I2C bit-banged           */
 127 #define CFG_I2C_SPEED           100000  /* I2C speed and slave address  */
 128 #define CFG_I2C_SLAVE           0x7F
 129
 130 #define CFG_I2C_EEPROM_ADDR     (0xa4>>1)
 131 #define CFG_I2C_EEPROM_ADDR_LEN 1
 132 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 133 #define CFG_EEPROM_PAGE_WRITE_BITS 3
 134 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
 135
 136 #define CONFIG_PREBOOT  "echo;" \
 137         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 138         "echo"
 139
 140 #undef  CONFIG_BOOTARGS
 141
 142 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 143         "netdev=eth0\0"                                                 \
 144         "hostname=pcs440ep\0"                                           \
 145         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 146                 "nfsroot=${serverip}:${rootpath}\0"                     \
 147         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 148         "addip=setenv bootargs ${bootargs} "                            \
 149                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 150                 ":${hostname}:${netdev}:off panic=1\0"                  \
 151         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 152         "flash_nfs=run nfsargs addip addtty;"                           \
 153                 "bootm ${kernel_addr}\0"                                \
 154         "flash_self=run ramargs addip addtty;"                          \
 155                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 156         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 157                 "bootm\0"                                               \
 158         "rootpath=/opt/eldk/ppc_4xx\0"                                  \
 159         "bootfile=/tftpboot/pcs440ep/uImage\0"                          \
 160         "kernel_addr=FFF00000\0"                                        \
 161         "ramdisk_addr=FFF00000\0"                                       \
 162         "load=tftp 100000 /tftpboot/pcs440ep/u-boot.bin\0"              \
 163         "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"   \
 164                 "cp.b 100000 FFFA0000 60000\0"                          \
 165         "upd=run load;run update\0"                                     \
 166         ""
 167 #define CONFIG_BOOTCOMMAND      "run flash_self"
 168
 169 #if 0
 170 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
 171 #else
 172 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 173 #endif
 174
 175 #define CONFIG_BAUDRATE         115200
 176
 177 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 178 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 179
 180 #define CONFIG_MII              1       /* MII PHY management           */
 181 #define CONFIG_NET_MULTI        1       /* required for netconsole      */
 182 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 183 #define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
 184 #define CONFIG_PHY1_ADDR        2
 185
 186 #define CFG_RX_ETH_BUFFER       32      /* Number of ethernet rx buffers & descriptors */
 187
 188 #define CONFIG_NETCONSOLE               /* include NetConsole support   */
 189
 190 /* Partitions */
 191 #define CONFIG_MAC_PARTITION
 192 #define CONFIG_DOS_PARTITION
 193 #define CONFIG_ISO_PARTITION
 194
 195 #ifdef CONFIG_440EP
 196 /* USB */
 197 #define CONFIG_USB_OHCI
 198 #define CONFIG_USB_STORAGE
 199
 200 /*Comment this out to enable USB 1.1 device*/
 201 #define USB_2_0_DEVICE
 202 #endif /*CONFIG_440EP*/
 203
 204 #ifdef DEBUG
 205 #define CONFIG_PANIC_HANG
 206 #else
 207 #define CONFIG_HW_WATCHDOG                      /* watchdog */
 208 #endif
 209
 210 #define CONFIG_COMMANDS        (CONFIG_CMD_DFL  | \
 211                                 CFG_CMD_ASKENV  | \
 212                                 CFG_CMD_DHCP    | \
 213                                 CFG_CMD_DIAG    | \
 214                                 CFG_CMD_EEPROM  | \
 215                                 CFG_CMD_ELF     | \
 216                                 CFG_CMD_I2C     | \
 217                                 CFG_CMD_IRQ     | \
 218                                 CFG_CMD_MII     | \
 219                                 CFG_CMD_NET     | \
 220                                 CFG_CMD_NFS     | \
 221                                 CFG_CMD_PCI     | \
 222                                 CFG_CMD_PING    | \
 223                                 CFG_CMD_REGINFO | \
 224                                 CFG_CMD_SDRAM   | \
 225                                 CFG_CMD_EXT2    | \
 226                                 CFG_CMD_FAT     | \
 227                                 CFG_CMD_USB     )
 228
 229
 230 #define CONFIG_SUPPORT_VFAT
 231
 232 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 233 #include <cmd_confdefs.h>
 234
 235 /*
 236  * Miscellaneous configurable options
 237  */
 238 #define CFG_LONGHELP                    /* undef to save memory         */
 239 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
 240 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 241 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size      */
 242 #else
 243 #define CFG_CBSIZE              256     /* Console I/O Buffer Size      */
 244 #endif
 245 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 246 #define CFG_MAXARGS             16      /* max number of command args   */
 247 #define CFG_BARGSIZE            CFG_CBSIZE /* Boot Argument Buffer Size */
 248
 249 #define CFG_MEMTEST_START       0x0400000 /* memtest works on           */
 250 #define CFG_MEMTEST_END         0x0C00000 /* 4 ... 12 MB in DRAM        */
 251
 252 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 253 #define CFG_EXTBDINFO           1       /* To use extended board_into (bd_t) */
 254 #define CONFIG_LYNXKDI          1       /* support kdi files            */
 255
 256 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 257
 258 /*-----------------------------------------------------------------------
 259  * PCI stuff
 260  *-----------------------------------------------------------------------
 261  */
 262 /* General PCI */
 263 #define CONFIG_PCI                      /* include pci support          */
 264 #undef  CONFIG_PCI_PNP                  /* do (not) pci plug-and-play   */
 265 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 266 #define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
 267
 268 /* Board-specific PCI */
 269 #define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
 270 #define CFG_PCI_TARGET_INIT
 271 #define CFG_PCI_MASTER_INIT
 272
 273 #define CFG_PCI_SUBSYS_VENDORID 0x10e8  /* AMCC */
 274 #define CFG_PCI_SUBSYS_ID       0xcafe  /* Whatever */
 275
 276 /*
 277  * For booting Linux, the board info and command line data
 278  * have to be in the first 8 MB of memory, since this is
 279  * the maximum mapped by the Linux kernel during initialization.
 280  */
 281 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 282
 283 /*-----------------------------------------------------------------------
 284  * External Bus Controller (EBC) Setup
 285  *----------------------------------------------------------------------*/
 286 #define FLASH_BASE0_PRELIM      0xFFF00000      /* FLASH bank #0        */
 287 #define FLASH_BASE1_PRELIM      0xFFF80000      /* FLASH bank #1        */
 288
 289 #define CFG_FLASH               FLASH_BASE0_PRELIM
 290 #define CFG_SRAM                0xF1000000
 291 #define CFG_FPGA                0xF2000000
 292 #define CFG_CF1                 0xF0000000
 293 #define CFG_CF2                 0xF0100000
 294
 295 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 296 #define CFG_EBC_PB0AP           0x02010000      /* TWT=4,OEN=1                  */
 297 #define CFG_EBC_PB0CR           (CFG_FLASH | 0x18000) /* BS=1MB,BU=R/W,BW=8bit  */
 298
 299 /* Memory Bank 1 (SRAM) initialization                                          */
 300 #define CFG_EBC_PB1AP           0x01810040      /* TWT=3,OEN=1,BEM=1            */
 301 #define CFG_EBC_PB1CR           (CFG_SRAM | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit  */
 302
 303 /* Memory Bank 2 (FPGA) initialization                                          */
 304 #define CFG_EBC_PB2AP           0x01010440      /* TWT=2,OEN=1,TH=2,BEM=1       */
 305 #define CFG_EBC_PB2CR           (CFG_FPGA | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit  */
 306
 307 /* Memory Bank 3 (CompactFlash) initialization                                  */
 308 #define CFG_EBC_PB3AP           0x080BD400
 309 #define CFG_EBC_PB3CR           (CFG_CF1 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit   */
 310
 311 /* Memory Bank 4 (CompactFlash) initialization                                  */
 312 #define CFG_EBC_PB4AP           0x080BD400
 313 #define CFG_EBC_PB4CR           (CFG_CF2 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit   */
 314
 315 /*-----------------------------------------------------------------------
 316  * PPC440 GPIO Configuration
 317  */
 318 #define CFG_440_GPIO_TABLE { /*         GPIO    Alternate1      Alternate2      Alternate3 */ \
 319 {                                                                                       \
 320 /* GPIO Core 0 */                                                                       \
 321 { GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO0   EBC_ADDR(7)     DMA_REQ(2)      */      \
 322 { GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO1   EBC_ADDR(6)     DMA_ACK(2)      */      \
 323 { GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO2   EBC_ADDR(5)     DMA_EOT/TC(2)   */      \
 324 { GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO3   EBC_ADDR(4)     DMA_REQ(3)      */      \
 325 { GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO4   EBC_ADDR(3)     DMA_ACK(3)      */      \
 326 { GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO5   EBC_ADDR(2)     DMA_EOT/TC(3)   */      \
 327 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO6   EBC_CS_N(1)                     */      \
 328 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO7   EBC_CS_N(2)                     */      \
 329 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO8   EBC_CS_N(3)                     */      \
 330 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO9   EBC_CS_N(4)                     */      \
 331 { GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO10  EBC_CS_N(5)                     */      \
 332 { GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO11  EBC_BUS_ERR                     */      \
 333 { GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO12  ZII_p0Rxd(0)                    */      \
 334 { GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO13  ZII_p0Rxd(1)                    */      \
 335 { GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO14  ZII_p0Rxd(2)                    */      \
 336 { GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO15  ZII_p0Rxd(3)                    */      \
 337 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO16  ZII_p0Txd(0)                    */      \
 338 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO17  ZII_p0Txd(1)                    */      \
 339 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO18  ZII_p0Txd(2)                    */      \
 340 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO19  ZII_p0Txd(3)                    */      \
 341 { GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO20  ZII_p0Rx_er                     */      \
 342 { GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO21  ZII_p0Rx_dv                     */      \
 343 { GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO22  ZII_p0RxCrs                     */      \
 344 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO23  ZII_p0Tx_er                     */      \
 345 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO24  ZII_p0Tx_en                     */      \
 346 { GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO25  ZII_p0Col                       */      \
 347 { GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO26                  USB2D_RXVALID   */      \
 348 { GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO27  EXT_EBC_REQ     USB2D_RXERROR   */      \
 349 { GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO28                  USB2D_TXVALID   */      \
 350 { GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO29  EBC_EXT_HDLA    USB2D_PAD_SUSPNDM */    \
 351 { GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO30  EBC_EXT_ACK     USB2D_XCVRSELECT*/      \
 352 { GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO31  EBC_EXR_BUSREQ  USB2D_TERMSELECT*/      \
 353 },                                                                                      \
 354 {                                                                                       \
 355 /* GPIO Core 1 */                                                                       \
 356 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO32  USB2D_OPMODE0                   */      \
 357 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO33  USB2D_OPMODE1                   */      \
 358 { GPIO1_BASE, GPIO_OUT, GPIO_ALT3 }, /* GPIO34  UART0_DCD_N     UART1_DSR_CTS_N UART2_SOUT*/ \
 359 { GPIO1_BASE, GPIO_IN,  GPIO_ALT3 }, /* GPIO35  UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 360 { GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO36  UART0_8PIN_CTS_N                UART3_SIN*/ \
 361 { GPIO1_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO37  UART0_RTS_N                     */      \
 362 { GPIO1_BASE, GPIO_OUT, GPIO_ALT2 }, /* GPIO38  UART0_DTR_N     UART1_SOUT      */      \
 363 { GPIO1_BASE, GPIO_IN,  GPIO_ALT2 }, /* GPIO39  UART0_RI_N      UART1_SIN       */      \
 364 { GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO40  UIC_IRQ(0)                      */      \
 365 { GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO41  UIC_IRQ(1)                      */      \
 366 { GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO42  UIC_IRQ(2)                      */      \
 367 { GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO43  UIC_IRQ(3)                      */      \
 368 { GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO44  UIC_IRQ(4)      DMA_ACK(1)      */      \
 369 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO45  UIC_IRQ(6)      DMA_EOT/TC(1)   */      \
 370 { GPIO1_BASE, GPIO_BI,  GPIO_SEL },  /* GPIO46  UIC_IRQ(7)      DMA_REQ(0)      */      \
 371 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO47  UIC_IRQ(8)      DMA_ACK(0)      */      \
 372 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO48  UIC_IRQ(9)      DMA_EOT/TC(0)   */      \
 373 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO49  Unselect via TraceSelect Bit    */      \
 374 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO50  Unselect via TraceSelect Bit    */      \
 375 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO51  Unselect via TraceSelect Bit    */      \
 376 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO52  Unselect via TraceSelect Bit    */      \
 377 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO53  Unselect via TraceSelect Bit    */      \
 378 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO54  Unselect via TraceSelect Bit    */      \
 379 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO55  Unselect via TraceSelect Bit    */      \
 380 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO56  Unselect via TraceSelect Bit    */      \
 381 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO57  Unselect via TraceSelect Bit    */      \
 382 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO58  Unselect via TraceSelect Bit    */      \
 383 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO59  Unselect via TraceSelect Bit    */      \
 384 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO60  Unselect via TraceSelect Bit    */      \
 385 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO61  Unselect via TraceSelect Bit    */      \
 386 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO62  Unselect via TraceSelect Bit    */      \
 387 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO63  Unselect via TraceSelect Bit    */      \
 388 }                                                                                       \
 389 }
 390
 391 /*-----------------------------------------------------------------------
 392  * Cache Configuration
 393  */
 394 #define CFG_DCACHE_SIZE         (32<<10) /* For AMCC 440 CPUs                   */
 395 #define CFG_CACHELINE_SIZE      32      /* ...                  */
 396 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 397 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value        */
 398 #endif
 399
 400 /*
 401  * Internal Definitions
 402  *
 403  * Boot Flags
 404  */
 405 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 406 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 407
 408 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 409 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 410 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 411 #endif
 412
 413 #endif  /* __CONFIG_H */