include/configs/pcs440ep.h

   1 /*
   2  * (C) Copyright 2006
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /************************************************************************
  25  * pcs440ep.h - configuration for PCS440EP board
  26  ***********************************************************************/
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /*-----------------------------------------------------------------------
  31  * High Level Configuration Options
  32  *----------------------------------------------------------------------*/
  33 #define CONFIG_PCS440EP         1       /* Board is PCS440EP            */
  34 #define CONFIG_440EP            1       /* Specific PPC440EP support    */
  35 #define CONFIG_4xx              1       /* ... PPC4xx family            */
  36 #define CONFIG_SYS_CLK_FREQ     33333333    /* external freq to pll     */
  37
  38 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  39 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  40
  41 /*-----------------------------------------------------------------------
  42  * Base addresses -- Note these are effective addresses where the
  43  * actual resources get mapped (not physical addresses)
  44  *----------------------------------------------------------------------*/
  45 #define CFG_MONITOR_LEN         (384 * 1024)    /* Reserve 384 kB for Monitor   */
  46 #define CFG_MALLOC_LEN          (256 * 1024)    /* Reserve 256 kB for malloc()  */
  47 #define CFG_MONITOR_BASE        (-CFG_MONITOR_LEN)
  48 #define CFG_SDRAM_BASE          0x00000000          /* _must_ be 0      */
  49 #define CFG_FLASH_BASE          0xfff00000          /* start of FLASH   */
  50 #define CFG_PCI_MEMBASE         0xa0000000          /* mapped pci memory*/
  51 #define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
  52 #define CFG_PCI_MEMBASE2        CFG_PCI_MEMBASE1 + 0x10000000
  53 #define CFG_PCI_MEMBASE3        CFG_PCI_MEMBASE2 + 0x10000000
  54
  55 /*Don't change either of these*/
  56 #define CFG_PERIPHERAL_BASE     0xef600000          /* internal peripherals*/
  57 #define CFG_PCI_BASE            0xe0000000          /* internal PCI regs*/
  58 /*Don't change either of these*/
  59
  60 #define CFG_USB_DEVICE          0x50000000
  61 #define CFG_BOOT_BASE_ADDR      0xf0000000
  62
  63 /*-----------------------------------------------------------------------
  64  * Initial RAM & stack pointer (placed in SDRAM)
  65  *----------------------------------------------------------------------*/
  66 #define CFG_INIT_RAM_DCACHE     1               /* d-cache as init ram  */
  67 #define CFG_INIT_RAM_ADDR       0x70000000              /* DCache       */
  68 #define CFG_INIT_RAM_END        (8 << 10)
  69 #define CFG_GBL_DATA_SIZE       256                     /* num bytes initial data*/
  70 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  71 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
  72
  73 /*-----------------------------------------------------------------------
  74  * Serial Port
  75  *----------------------------------------------------------------------*/
  76 #undef CFG_EXT_SERIAL_CLOCK             /* no external clk used         */
  77 #define CONFIG_BAUDRATE         115200
  78 #define CONFIG_SERIAL_MULTI     1
  79 /*define this if you want console on UART1*/
  80 #undef CONFIG_UART1_CONSOLE
  81
  82 #define CFG_BAUDRATE_TABLE  \
  83     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  84
  85 /*-----------------------------------------------------------------------
  86  * Environment
  87  *----------------------------------------------------------------------*/
  88 #define CFG_ENV_IS_IN_FLASH     1       /* use FLASH for environment vars       */
  89
  90 /*-----------------------------------------------------------------------
  91  * FLASH related
  92  *----------------------------------------------------------------------*/
  93 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
  94 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
  95
  96 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
  97 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
  98
  99 #define CFG_FLASH_WORD_SIZE     unsigned char   /* flash word size (width)      */
 100 #define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
 101 #define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
 102
 103 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 104
 105 #ifdef CFG_ENV_IS_IN_FLASH
 106 #define CFG_ENV_SECT_SIZE       0x10000         /* size of one complete sector  */
 107 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
 108 #define CFG_ENV_SIZE            0x2000  /* Total Size of Environment Sector     */
 109
 110 #define CONFIG_ENV_OVERWRITE    1
 111
 112 /* Address and size of Redundant Environment Sector     */
 113 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
 114 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 115 #endif /* CFG_ENV_IS_IN_FLASH */
 116
 117 #define ENV_NAME_REVLEV "revision_level"
 118 #define ENV_NAME_SOLDER "solder_switch"
 119 #define ENV_NAME_DIP    "dip"
 120
 121 /*-----------------------------------------------------------------------
 122  * DDR SDRAM
 123  *----------------------------------------------------------------------*/
 124 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup             */
 125 #undef CONFIG_DDR_ECC                   /* don't use ECC                        */
 126 #define SPD_EEPROM_ADDRESS      {0x50}
 127 #define CONFIG_PROG_SDRAM_TLB   1
 128 #define CONFIG_PPC4xx_USE_SPD_DDR_INIT_HANG     1
 129
 130 /*-----------------------------------------------------------------------
 131  * I2C
 132  *----------------------------------------------------------------------*/
 133 #define CONFIG_HARD_I2C         1           /* I2C with hardware support        */
 134 #undef  CONFIG_SOFT_I2C                     /* I2C bit-banged           */
 135 #define CFG_I2C_SPEED           100000  /* I2C speed and slave address  */
 136 #define CFG_I2C_SLAVE           0x7F
 137
 138 #define CFG_I2C_EEPROM_ADDR     (0xa4>>1)
 139 #define CFG_I2C_EEPROM_ADDR_LEN 1
 140 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 141 #define CFG_EEPROM_PAGE_WRITE_BITS 3
 142 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
 143
 144 #define CONFIG_PREBOOT  "echo;" \
 145         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 146         "echo"
 147
 148 #undef  CONFIG_BOOTARGS
 149
 150 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 151         "netdev=eth0\0"                                                 \
 152         "hostname=pcs440ep\0"                                           \
 153         "use_eeprom_ethaddr=default\0"                                  \
 154         "cs_test=off\0"                                                 \
 155         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 156                 "nfsroot=${serverip}:${rootpath}\0"                     \
 157         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 158         "addip=setenv bootargs ${bootargs} "                            \
 159                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 160                 ":${hostname}:${netdev}:off panic=1\0"                  \
 161         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 162         "flash_nfs=run nfsargs addip addtty;"                           \
 163                 "bootm ${kernel_addr}\0"                                \
 164         "flash_self=run ramargs addip addtty;"                          \
 165                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 166         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 167                 "bootm\0"                                               \
 168         "rootpath=/opt/eldk/ppc_4xx\0"                                  \
 169         "bootfile=/tftpboot/pcs440ep/uImage\0"                          \
 170         "kernel_addr=FFF00000\0"                                        \
 171         "ramdisk_addr=FFF00000\0"                                       \
 172         "load=tftp 100000 /tftpboot/pcs440ep/u-boot.bin\0"              \
 173         "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"   \
 174                 "cp.b 100000 FFFA0000 60000\0"                          \
 175         "upd=run load;run update\0"                                     \
 176         ""
 177 #define CONFIG_BOOTCOMMAND      "run flash_self"
 178
 179 #if 0
 180 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
 181 #else
 182 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 183 #endif
 184
 185 #define CONFIG_PREBOOT  "echo;" \
 186         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 187         "echo"
 188
 189 /* check U-Boot image with SHA1 sum */
 190 #define CONFIG_SHA1_CHECK_UB_IMG        1
 191 #define CONFIG_SHA1_START               CFG_MONITOR_BASE
 192 #define CONFIG_SHA1_LEN                 CFG_MONITOR_LEN
 193
 194 /*-----------------------------------------------------------------------
 195  * Definitions for status LED
 196  */
 197 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
 198 #define CONFIG_BOARD_SPECIFIC_LED       1
 199
 200 #define STATUS_LED_BIT          0x08                    /* LED 1 is on GPIO_PPC_1 */
 201 #define STATUS_LED_PERIOD       ((CFG_HZ / 2) / 5)      /* blink at 5 Hz */
 202 #define STATUS_LED_STATE        STATUS_LED_OFF
 203 #define STATUS_LED_BIT1         0x04                    /* LED 2 is on GPIO_PPC_2 */
 204 #define STATUS_LED_PERIOD1      ((CFG_HZ / 2) / 5)      /* blink at 5 Hz */
 205 #define STATUS_LED_STATE1       STATUS_LED_ON
 206 #define STATUS_LED_BIT2         0x02                    /* LED 3 is on GPIO_PPC_3 */
 207 #define STATUS_LED_PERIOD2      ((CFG_HZ / 2) / 5)      /* blink at 5 Hz */
 208 #define STATUS_LED_STATE2       STATUS_LED_OFF
 209 #define STATUS_LED_BIT3         0x01                    /* LED 4 is on GPIO_PPC_4 */
 210 #define STATUS_LED_PERIOD3      ((CFG_HZ / 2) / 5)      /* blink at 5 Hz */
 211 #define STATUS_LED_STATE3       STATUS_LED_OFF
 212
 213 #define CONFIG_SHOW_BOOT_PROGRESS       1
 214
 215 #define CONFIG_BAUDRATE         115200
 216
 217 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 218 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 219
 220 #define CONFIG_MII              1       /* MII PHY management           */
 221 #define CONFIG_NET_MULTI        1       /* required for netconsole      */
 222 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 223 #define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
 224 #define CONFIG_PHY1_ADDR        2
 225
 226 #define CFG_RX_ETH_BUFFER       32      /* Number of ethernet rx buffers & descriptors */
 227
 228 #define CONFIG_NETCONSOLE               /* include NetConsole support   */
 229
 230 /* Partitions */
 231 #define CONFIG_MAC_PARTITION
 232 #define CONFIG_DOS_PARTITION
 233 #define CONFIG_ISO_PARTITION
 234
 235 #ifdef CONFIG_440EP
 236 /* USB */
 237 #define CONFIG_USB_OHCI
 238 #define CONFIG_USB_STORAGE
 239
 240 /*Comment this out to enable USB 1.1 device*/
 241 #define USB_2_0_DEVICE
 242 #endif /*CONFIG_440EP*/
 243
 244 #ifdef DEBUG
 245 #define CONFIG_PANIC_HANG
 246 #else
 247 #define CONFIG_HW_WATCHDOG                      /* watchdog */
 248 #endif
 249
 250 #define CONFIG_COMMANDS        (CONFIG_CMD_DFL  | \
 251                                 CFG_CMD_ASKENV  | \
 252                                 CFG_CMD_DHCP    | \
 253                                 CFG_CMD_DIAG    | \
 254                                 CFG_CMD_EEPROM  | \
 255                                 CFG_CMD_ELF     | \
 256                                 CFG_CMD_EXT2    | \
 257                                 CFG_CMD_FAT     | \
 258                                 CFG_CMD_I2C     | \
 259                                 CFG_CMD_IDE     | \
 260                                 CFG_CMD_IRQ     | \
 261                                 CFG_CMD_MII     | \
 262                                 CFG_CMD_NET     | \
 263                                 CFG_CMD_NFS     | \
 264                                 CFG_CMD_PCI     | \
 265                                 CFG_CMD_PING    | \
 266                                 CFG_CMD_REGINFO | \
 267                                 CFG_CMD_REISER  | \
 268                                 CFG_CMD_SDRAM   | \
 269                                 CFG_CMD_USB     )
 270
 271
 272 #define CONFIG_SUPPORT_VFAT
 273
 274 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 275 #include <cmd_confdefs.h>
 276
 277 /*
 278  * Miscellaneous configurable options
 279  */
 280 #define CFG_LONGHELP                    /* undef to save memory         */
 281 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
 282 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 283 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size      */
 284 #else
 285 #define CFG_CBSIZE              256     /* Console I/O Buffer Size      */
 286 #endif
 287 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 288 #define CFG_MAXARGS             16      /* max number of command args   */
 289 #define CFG_BARGSIZE            CFG_CBSIZE /* Boot Argument Buffer Size */
 290
 291 #define CFG_MEMTEST_START       0x0400000 /* memtest works on           */
 292 #define CFG_MEMTEST_END         0x0C00000 /* 4 ... 12 MB in DRAM        */
 293
 294 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 295 #define CFG_EXTBDINFO           1       /* To use extended board_into (bd_t) */
 296 #define CONFIG_LYNXKDI          1       /* support kdi files            */
 297
 298 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 299
 300 /*-----------------------------------------------------------------------
 301  * PCI stuff
 302  *-----------------------------------------------------------------------
 303  */
 304 /* General PCI */
 305 #define CONFIG_PCI                      /* include pci support          */
 306 #undef  CONFIG_PCI_PNP                  /* do (not) pci plug-and-play   */
 307 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 308 #define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
 309
 310 /* Board-specific PCI */
 311 #define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
 312 #define CFG_PCI_TARGET_INIT
 313 #define CFG_PCI_MASTER_INIT
 314
 315 #define CFG_PCI_SUBSYS_VENDORID 0x10e8  /* AMCC */
 316 #define CFG_PCI_SUBSYS_ID       0xcafe  /* Whatever */
 317
 318 /*
 319  * For booting Linux, the board info and command line data
 320  * have to be in the first 8 MB of memory, since this is
 321  * the maximum mapped by the Linux kernel during initialization.
 322  */
 323 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 324
 325 /*-----------------------------------------------------------------------
 326  * External Bus Controller (EBC) Setup
 327  *----------------------------------------------------------------------*/
 328 #define FLASH_BASE0_PRELIM      0xFFF00000      /* FLASH bank #0        */
 329 #define FLASH_BASE1_PRELIM      0xFFF80000      /* FLASH bank #1        */
 330
 331 #define CFG_FLASH               FLASH_BASE0_PRELIM
 332 #define CFG_SRAM                0xF1000000
 333 #define CFG_FPGA                0xF2000000
 334 #define CFG_CF1                 0xF0000000
 335 #define CFG_CF2                 0xF0100000
 336
 337 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 338 #define CFG_EBC_PB0AP           0x02010000      /* TWT=4,OEN=1                  */
 339 #define CFG_EBC_PB0CR           (CFG_FLASH | 0x18000) /* BS=1MB,BU=R/W,BW=8bit  */
 340
 341 /* Memory Bank 1 (SRAM) initialization                                          */
 342 #define CFG_EBC_PB1AP           0x01810040      /* TWT=3,OEN=1,BEM=1            */
 343 #define CFG_EBC_PB1CR           (CFG_SRAM | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit  */
 344
 345 /* Memory Bank 2 (FPGA) initialization                                          */
 346 #define CFG_EBC_PB2AP           0x01010440      /* TWT=2,OEN=1,TH=2,BEM=1       */
 347 #define CFG_EBC_PB2CR           (CFG_FPGA | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit  */
 348
 349 /* Memory Bank 3 (CompactFlash) initialization                                  */
 350 #define CFG_EBC_PB3AP           0x080BD400
 351 #define CFG_EBC_PB3CR           (CFG_CF1 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit   */
 352
 353 /* Memory Bank 4 (CompactFlash) initialization                                  */
 354 #define CFG_EBC_PB4AP           0x080BD400
 355 #define CFG_EBC_PB4CR           (CFG_CF2 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit   */
 356
 357 /*-----------------------------------------------------------------------
 358  * PPC440 GPIO Configuration
 359  */
 360 #define CFG_440_GPIO_TABLE { /*         GPIO    Alternate1      Alternate2      Alternate3 */ \
 361 {                                                                                       \
 362 /* GPIO Core 0 */                                                                       \
 363 { GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO0   EBC_ADDR(7)     DMA_REQ(2)      */      \
 364 { GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO1   EBC_ADDR(6)     DMA_ACK(2)      */      \
 365 { GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO2   EBC_ADDR(5)     DMA_EOT/TC(2)   */      \
 366 { GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO3   EBC_ADDR(4)     DMA_REQ(3)      */      \
 367 { GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO4   EBC_ADDR(3)     DMA_ACK(3)      */      \
 368 { GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO5   EBC_ADDR(2)     DMA_EOT/TC(3)   */      \
 369 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO6   EBC_CS_N(1)                     */      \
 370 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO7   EBC_CS_N(2)                     */      \
 371 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO8   EBC_CS_N(3)                     */      \
 372 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO9   EBC_CS_N(4)                     */      \
 373 { GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO10  EBC_CS_N(5)                     */      \
 374 { GPIO0_BASE, GPIO_OUT, GPIO_SEL },  /* GPIO11  EBC_BUS_ERR                     */      \
 375 { GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO12  ZII_p0Rxd(0)                    */      \
 376 { GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO13  ZII_p0Rxd(1)                    */      \
 377 { GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO14  ZII_p0Rxd(2)                    */      \
 378 { GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO15  ZII_p0Rxd(3)                    */      \
 379 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO16  ZII_p0Txd(0)                    */      \
 380 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO17  ZII_p0Txd(1)                    */      \
 381 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO18  ZII_p0Txd(2)                    */      \
 382 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO19  ZII_p0Txd(3)                    */      \
 383 { GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO20  ZII_p0Rx_er                     */      \
 384 { GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO21  ZII_p0Rx_dv                     */      \
 385 { GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO22  ZII_p0RxCrs                     */      \
 386 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO23  ZII_p0Tx_er                     */      \
 387 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO24  ZII_p0Tx_en                     */      \
 388 { GPIO0_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO25  ZII_p0Col                       */      \
 389 { GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO26                  USB2D_RXVALID   */      \
 390 { GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO27  EXT_EBC_REQ     USB2D_RXERROR   */      \
 391 { GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO28                  USB2D_TXVALID   */      \
 392 { GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO29  EBC_EXT_HDLA    USB2D_PAD_SUSPNDM */    \
 393 { GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO30  EBC_EXT_ACK     USB2D_XCVRSELECT*/      \
 394 { GPIO0_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO31  EBC_EXR_BUSREQ  USB2D_TERMSELECT*/      \
 395 },                                                                                      \
 396 {                                                                                       \
 397 /* GPIO Core 1 */                                                                       \
 398 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO32  USB2D_OPMODE0                   */      \
 399 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO33  USB2D_OPMODE1                   */      \
 400 { GPIO1_BASE, GPIO_OUT, GPIO_ALT3 }, /* GPIO34  UART0_DCD_N     UART1_DSR_CTS_N UART2_SOUT*/ \
 401 { GPIO1_BASE, GPIO_IN,  GPIO_ALT3 }, /* GPIO35  UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 402 { GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO36  UART0_8PIN_CTS_N                UART3_SIN*/ \
 403 { GPIO1_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO37  UART0_RTS_N                     */      \
 404 { GPIO1_BASE, GPIO_OUT, GPIO_ALT2 }, /* GPIO38  UART0_DTR_N     UART1_SOUT      */      \
 405 { GPIO1_BASE, GPIO_IN,  GPIO_ALT2 }, /* GPIO39  UART0_RI_N      UART1_SIN       */      \
 406 { GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO40  UIC_IRQ(0)                      */      \
 407 { GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO41  UIC_IRQ(1)                      */      \
 408 { GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO42  UIC_IRQ(2)                      */      \
 409 { GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO43  UIC_IRQ(3)                      */      \
 410 { GPIO1_BASE, GPIO_IN,  GPIO_ALT1 }, /* GPIO44  UIC_IRQ(4)      DMA_ACK(1)      */      \
 411 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO45  UIC_IRQ(6)      DMA_EOT/TC(1)   */      \
 412 { GPIO1_BASE, GPIO_BI,  GPIO_SEL },  /* GPIO46  UIC_IRQ(7)      DMA_REQ(0)      */      \
 413 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO47  UIC_IRQ(8)      DMA_ACK(0)      */      \
 414 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO48  UIC_IRQ(9)      DMA_EOT/TC(0)   */      \
 415 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO49  Unselect via TraceSelect Bit    */      \
 416 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO50  Unselect via TraceSelect Bit    */      \
 417 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO51  Unselect via TraceSelect Bit    */      \
 418 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO52  Unselect via TraceSelect Bit    */      \
 419 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO53  Unselect via TraceSelect Bit    */      \
 420 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO54  Unselect via TraceSelect Bit    */      \
 421 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO55  Unselect via TraceSelect Bit    */      \
 422 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO56  Unselect via TraceSelect Bit    */      \
 423 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO57  Unselect via TraceSelect Bit    */      \
 424 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO58  Unselect via TraceSelect Bit    */      \
 425 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO59  Unselect via TraceSelect Bit    */      \
 426 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO60  Unselect via TraceSelect Bit    */      \
 427 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO61  Unselect via TraceSelect Bit    */      \
 428 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO62  Unselect via TraceSelect Bit    */      \
 429 { GPIO1_BASE, GPIO_IN,  GPIO_SEL },  /* GPIO63  Unselect via TraceSelect Bit    */      \
 430 }                                                                                       \
 431 }
 432
 433 /*-----------------------------------------------------------------------
 434  * Cache Configuration
 435  */
 436 #define CFG_DCACHE_SIZE         (32<<10) /* For AMCC 440 CPUs                   */
 437 #define CFG_CACHELINE_SIZE      32      /* ...                  */
 438 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 439 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value        */
 440 #endif
 441
 442 /*
 443  * Internal Definitions
 444  *
 445  * Boot Flags
 446  */
 447 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 448 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 449
 450 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 451 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 452 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 453 #endif
 454
 455 /*-----------------------------------------------------------------------
 456  * IDE/ATA stuff Supports IDE harddisk
 457  *-----------------------------------------------------------------------
 458  */
 459
 460 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 461
 462 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 463 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 464
 465 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 466 #define CFG_IDE_MAXDEVICE       1       /* max. 2 drives per IDE bus    */
 467
 468 #define CONFIG_IDE_PREINIT      1
 469 #define CONFIG_IDE_RESET        1
 470
 471 #define CFG_ATA_IDE0_OFFSET     0x0000
 472
 473 #define CFG_ATA_BASE_ADDR       CFG_CF1
 474
 475 /* Offset for data I/O                  */
 476 #define CFG_ATA_DATA_OFFSET     0
 477
 478 /* Offset for normal register accesses  */
 479 #define CFG_ATA_REG_OFFSET      (CFG_ATA_DATA_OFFSET)
 480
 481 /* Offset for alternate registers       */
 482 #define CFG_ATA_ALT_OFFSET      (0x0000)
 483
 484 /* This addresses need to be shifted one place to the left
 485  * ( bus per_addr 20 -30 is connectsd on CF bus A10-A0)
 486  * This values are shifted
 487  */
 488 #define CFG_ATA_PORT_ADDR(port) ((port) << 1)
 489
 490 #endif  /* __CONFIG_H */