include/configs/pdm360ng.h

   1 /*
   2  * (C) Copyright 2009-2010
   3  * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * pdm360ng board configuration file
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 #define CONFIG_PDM360NG 1
  16
  17 /*
  18  * Memory map for the PDM360NG board:
  19  *
  20  * 0x0000_0000 - 0x1FFF_FFFF    DDR RAM (512 MB)
  21  * 0x2000_0000 - 0x3FFF_FFFF    reserved (DDR RAM (512 MB)
  22  * 0x5000_0000 - 0x5001_FFFF    SRAM (128 KB)
  23  * 0x5004_0000 - 0x5005_FFFF    MRAM (CS2) (128 KB)
  24  * 0x8000_0000 - 0x803F_FFFF    IMMR (4 MB)
  25  * 0xF000_0000 - 0xF7FF_FFFF    NOR FLASH (CS0) (128 MB)
  26  * 0xF800_0000 - 0xFFFF_FFFF    NOR FLASH (CS1) (128 MB) optional
  27  */
  28
  29 /*
  30  * High Level Configuration Options
  31  */
  32 #define CONFIG_E300             1       /* E300 Family */
  33 #define CONFIG_FSL_DIU_FB       1       /* FSL DIU */
  34
  35 #define CONFIG_SYS_TEXT_BASE    0xF0000000
  36
  37 /* Used for silent command in environment */
  38 #define CONFIG_SYS_DEVICE_NULLDEV
  39
  40 /* Video */
  41
  42 #if defined(CONFIG_VIDEO)
  43 #define CONFIG_SPLASH_SCREEN
  44 #define CONFIG_VIDEO_LOGO
  45 #define CONFIG_VIDEO_BMP_RLE8
  46 #endif
  47
  48 #define CONFIG_SYS_MPC512X_CLKIN        33333333        /* in Hz */
  49
  50 #define CONFIG_MISC_INIT_R
  51
  52 #define CONFIG_SYS_IMMR                 0x80000000
  53 #define CONFIG_SYS_DIU_ADDR             ((CONFIG_SYS_IMMR) + 0x2100)
  54
  55 /*
  56  * DDR Setup
  57  */
  58
  59 /* DDR is system memory */
  60 #define CONFIG_SYS_DDR_BASE             0x00000000
  61 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  62 #define CONFIG_SYS_MAX_RAM_SIZE         0x40000000
  63
  64 /* DDR pin mux and slew rate */
  65 #define CONFIG_SYS_IOCTRL_MUX_DDR       0x00000012
  66
  67 /* Manually set all parameters as there's no SPD etc. */
  68 /*
  69  * DDR Controller Configuration for Micron DDR2 SDRAM MT47H128M8-3
  70  *
  71  * SYS_CFG:
  72  *      [31:31] MDDRC Soft Reset:       Diabled
  73  *      [30:30] DRAM CKE pin:           Enabled
  74  *      [29:29] DRAM CLK:               Enabled
  75  *      [28:28] Command Mode:           Enabled (For initialization only)
  76  *      [27:25] DRAM Row Select:        dram_row[15:0] = magenta_address[25:10]
  77  *      [24:21] DRAM Bank Select:       dram_bank[1:0] = magenta_address[11:10]
  78  *      [20:19] Read Test:              DON'T USE
  79  *      [18:18] Self Refresh:           Enabled
  80  *      [17:17] 16bit Mode:             Disabled
  81  *      [16:13] Read Delay:             3
  82  *      [12:12] Half DQS Delay:         Disabled
  83  *      [11:11] Quarter DQS Delay:      Disabled
  84  *      [10:08] Write Delay:            2
  85  *      [07:07] Early ODT:              Disabled
  86  *      [06:06] On DIE Termination:     Enabled
  87  *      [05:05] FIFO Overflow Clear:    DON'T USE here
  88  *      [04:04] FIFO Underflow Clear:   DON'T USE here
  89  *      [03:03] FIFO Overflow Pending:  DON'T USE here
  90  *      [02:02] FIFO Underlfow Pending: DON'T USE here
  91  *      [01:01] FIFO Overlfow Enabled:  Enabled
  92  *      [00:00] FIFO Underflow Enabled: Enabled
  93  * TIME_CFG0
  94  *      [31:16] DRAM Refresh Time:      0 CSB clocks
  95  *      [15:8]  DRAM Command Time:      0 CSB clocks
  96  *      [07:00] DRAM Precharge Time:    0 CSB clocks
  97  * TIME_CFG1
  98  *      [31:26] DRAM tRFC:
  99  *      [25:21] DRAM tWR1:
 100  *      [20:17] DRAM tWRT1:
 101  *      [16:11] DRAM tDRR:
 102  *      [10:05] DRAM tRC:
 103  *      [04:00] DRAM tRAS:
 104  * TIME_CFG2
 105  *      [31:28] DRAM tRCD:
 106  *      [27:23] DRAM tFAW:
 107  *      [22:19] DRAM tRTW1:
 108  *      [18:15] DRAM tCCD:
 109  *      [14:10] DRAM tRTP:
 110  *      [09:05] DRAM tRP:
 111  *      [04:00] DRAM tRPA
 112  */
 113 #define CONFIG_SYS_MDDRC_SYS_CFG        0xEA804A40
 114 #define CONFIG_SYS_MDDRC_TIME_CFG0      0x030C3D2E
 115 #define CONFIG_SYS_MDDRC_TIME_CFG1      0x68EC1168
 116 #define CONFIG_SYS_MDDRC_TIME_CFG2      0x34310864
 117
 118 /*
 119  * Alternative 1: small RAM (128 MB) configuration
 120  */
 121 #define CONFIG_SYS_MDDRC_SYS_CFG_ALT1   0xE8604A40
 122 #define CONFIG_SYS_MDDRC_TIME_CFG0_ALT1 0x030C3D2E
 123 #define CONFIG_SYS_MDDRC_TIME_CFG1_ALT1 0x3CEC1168
 124 #define CONFIG_SYS_MDDRC_TIME_CFG2_ALT1 0x33310863
 125
 126 #define CONFIG_SYS_MDDRC_SYS_CFG_EN     0xF0000000
 127
 128 #define CONFIG_SYS_DDRCMD_NOP           0x01380000
 129 #define CONFIG_SYS_DDRCMD_PCHG_ALL      0x01100400
 130 #define CONFIG_SYS_DDRCMD_EM2           0x01020000  /* EMR2 */
 131 #define CONFIG_SYS_DDRCMD_EM3           0x01030000  /* EMR3 */
 132 /* EMR with 150 ohm ODT todo: verify */
 133 #define CONFIG_SYS_DDRCMD_EN_DLL        0x01010040
 134 #define CONFIG_SYS_DDRCMD_RES_DLL       0x01000100
 135 #define CONFIG_SYS_DDRCMD_RFSH          0x01080000
 136 #define CONFIG_SYS_MICRON_INIT_DEV_OP   0x01000432
 137 /* EMR with 150 ohm ODT todo: verify */
 138 #define CONFIG_SYS_DDRCMD_OCD_DEFAULT   0x010107C0
 139 /* EMR new command with 150 ohm ODT todo: verify */
 140 #define CONFIG_SYS_DDRCMD_OCD_EXIT      0x01010440
 141
 142 /* DDR Priority Manager Configuration */
 143 #define CONFIG_SYS_MDDRCGRP_PM_CFG1     0x00077777
 144 #define CONFIG_SYS_MDDRCGRP_PM_CFG2     0x00000000
 145 #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG  0x00000001
 146 #define CONFIG_SYS_MDDRCGRP_LUT0_MU     0xFFEEDDCC
 147 #define CONFIG_SYS_MDDRCGRP_LUT0_ML     0xBBAAAAAA
 148 #define CONFIG_SYS_MDDRCGRP_LUT1_MU     0x66666666
 149 #define CONFIG_SYS_MDDRCGRP_LUT1_ML     0x55555555
 150 #define CONFIG_SYS_MDDRCGRP_LUT2_MU     0x44444444
 151 #define CONFIG_SYS_MDDRCGRP_LUT2_ML     0x44444444
 152 #define CONFIG_SYS_MDDRCGRP_LUT3_MU     0x55555555
 153 #define CONFIG_SYS_MDDRCGRP_LUT3_ML     0x55555558
 154 #define CONFIG_SYS_MDDRCGRP_LUT4_MU     0x11111111
 155 #define CONFIG_SYS_MDDRCGRP_LUT4_ML     0x11111122
 156 #define CONFIG_SYS_MDDRCGRP_LUT0_AU     0xaaaaaaaa
 157 #define CONFIG_SYS_MDDRCGRP_LUT0_AL     0xaaaaaaaa
 158 #define CONFIG_SYS_MDDRCGRP_LUT1_AU     0x66666666
 159 #define CONFIG_SYS_MDDRCGRP_LUT1_AL     0x66666666
 160 #define CONFIG_SYS_MDDRCGRP_LUT2_AU     0x11111111
 161 #define CONFIG_SYS_MDDRCGRP_LUT2_AL     0x11111111
 162 #define CONFIG_SYS_MDDRCGRP_LUT3_AU     0x11111111
 163 #define CONFIG_SYS_MDDRCGRP_LUT3_AL     0x11111111
 164 #define CONFIG_SYS_MDDRCGRP_LUT4_AU     0x11111111
 165 #define CONFIG_SYS_MDDRCGRP_LUT4_AL     0x11111111
 166
 167 /*
 168  * NOR FLASH on the Local Bus
 169  */
 170 #define CONFIG_SYS_FLASH_CFI            /* use Common Flash Interface */
 171 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 172 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 173
 174 #define CONFIG_SYS_FLASH_BASE           0xF0000000 /* start of FLASH-Bank0 */
 175 #define CONFIG_SYS_FLASH_SIZE           0x08000000 /* max size of a Bank */
 176 /* start of FLASH-Bank1 */
 177 #define CONFIG_SYS_FLASH1_BASE          (CONFIG_SYS_FLASH_BASE + \
 178                                          CONFIG_SYS_FLASH_SIZE)
 179 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max sectors per device */
 180 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 181 #define CONFIG_SYS_FLASH_BANKS_LIST \
 182         {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH1_BASE}
 183
 184 #define CONFIG_SYS_SRAM_BASE            0x50000000
 185 #define CONFIG_SYS_SRAM_SIZE            0x00020000      /* 128 KB */
 186
 187 #define CONFIG_SYS_CS1_START            CONFIG_SYS_FLASH1_BASE
 188 #define CONFIG_SYS_CS1_SIZE             CONFIG_SYS_FLASH_SIZE
 189
 190 /* ALE active low, data size 4 bytes */
 191 #define CONFIG_SYS_CS0_CFG              0x05059350
 192 /* ALE active low, data size 4 bytes */
 193 #define CONFIG_SYS_CS1_CFG              0x05059350
 194
 195 #define CONFIG_SYS_MRAM_BASE            0x50040000
 196 #define CONFIG_SYS_MRAM_SIZE            0x00020000
 197 #define CONFIG_SYS_CS2_START            CONFIG_SYS_MRAM_BASE
 198 #define CONFIG_SYS_CS2_SIZE             CONFIG_SYS_MRAM_SIZE
 199
 200 /* ALE active low, data size 4 bytes */
 201 #define CONFIG_SYS_CS2_CFG              0x05059110
 202
 203 /* alt. CS timing for CS0, CS1, CS2 */
 204 #define CONFIG_SYS_CS_ALETIMING         0x00000007
 205
 206 /*
 207  * NAND FLASH
 208  */
 209 #define CONFIG_CMD_NAND                 /* enable NAND support */
 210 #define CONFIG_NAND_MPC5121_NFC
 211 #define CONFIG_SYS_NAND_BASE            0x40000000
 212 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 213 #define CONFIG_SYS_NAND_SELECT_DEVICE   /* driver supports mutipl. chips */
 214
 215 /*
 216  * Configuration parameters for MPC5121 NAND driver
 217  */
 218 #define CONFIG_FSL_NFC_WIDTH 1
 219 #define CONFIG_FSL_NFC_WRITE_SIZE 2048
 220 #define CONFIG_FSL_NFC_SPARE_SIZE 64
 221 #define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
 222
 223 /*
 224  * Dynamic MTD partition support
 225  */
 226 #define CONFIG_CMD_MTDPARTS
 227 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
 228 #define CONFIG_FLASH_CFI_MTD
 229 #define MTDIDS_DEFAULT          "nor0=f0000000.flash,nor1=f8000000.flash," \
 230                                                 "nand0=MPC5121 NAND"
 231
 232 /*
 233  * Flash layout
 234  */
 235 #define MTDPARTS_DEFAULT        "mtdparts=f0000000.flash:512k(u-boot)," \
 236                                                 "256k(environment1),"   \
 237                                                 "256k(environment2),"   \
 238                                                 "256k(splash-factory)," \
 239                                                 "2m(FIT: recovery),"    \
 240                                                 "4608k(fs-recovery),"   \
 241                                                 "256k(splash-customer),"\
 242                                                 "5m(FIT: kernel+dtb),"  \
 243                                                 "64m(rootfs squash)ro," \
 244                                                 "51m(userfs ubi);"      \
 245                                         "f8000000.flash:-(unused);"     \
 246                                         "MPC5121 NAND:1024m(extended-userfs)"
 247
 248 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* Start of monitor */
 249 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* 512 kB for monitor */
 250 #ifdef  CONFIG_FSL_DIU_FB
 251 #define CONFIG_SYS_MALLOC_LEN           (6 * 1024 * 1024) /* for malloc */
 252 #else
 253 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
 254 #endif
 255
 256 /*
 257  * Serial Port
 258  */
 259 #define CONFIG_CONS_INDEX     1
 260
 261 /*
 262  * Serial console configuration
 263  */
 264 #define CONFIG_PSC_CONSOLE      6       /* console is on PSC6 */
 265 #if CONFIG_PSC_CONSOLE != 6
 266 #error CONFIG_PSC_CONSOLE must be 6
 267 #endif
 268
 269 #define CONSOLE_FIFO_TX_SIZE    FIFOC_PSC6_TX_SIZE
 270 #define CONSOLE_FIFO_TX_ADDR    FIFOC_PSC6_TX_ADDR
 271 #define CONSOLE_FIFO_RX_SIZE    FIFOC_PSC6_RX_SIZE
 272 #define CONSOLE_FIFO_RX_ADDR    FIFOC_PSC6_RX_ADDR
 273
 274 /*
 275  * Clocks in use
 276  */
 277 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN |                           \
 278                          CLOCK_SCCR1_LPC_EN |                           \
 279                          CLOCK_SCCR1_NFC_EN |                           \
 280                          CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |       \
 281                          CLOCK_SCCR1_PSCFIFO_EN |                       \
 282                          CLOCK_SCCR1_DDR_EN |                           \
 283                          CLOCK_SCCR1_FEC_EN |                           \
 284                          CLOCK_SCCR1_TPR_EN)
 285
 286 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN |           \
 287                          CLOCK_SCCR2_SPDIF_EN |         \
 288                          CLOCK_SCCR2_DIU_EN |           \
 289                          CLOCK_SCCR2_I2C_EN)
 290
 291 /*
 292  * Used PSC UART devices
 293  */
 294 #define CONFIG_SYS_PSC1
 295 #define CONFIG_SYS_PSC4
 296 #define CONFIG_SYS_PSC6
 297
 298 /*
 299  * Co-processor communication parameters
 300  */
 301 #define CONFIG_SYS_PDM360NG_COPROC_READ_DELAY   5000
 302 #define CONFIG_SYS_PDM360NG_COPROC_BAUDRATE     38400
 303
 304 /*
 305  * I2C
 306  */
 307 #define CONFIG_HARD_I2C                 /* I2C with hardware support */
 308 #define CONFIG_I2C_MULTI_BUS
 309 #define CONFIG_I2C_CMD_TREE
 310 /* I2C speed and slave address */
 311 #define CONFIG_SYS_I2C_SPEED            100000
 312 #define CONFIG_SYS_I2C_SLAVE            0x7F
 313
 314 /*
 315  * IIM - IC Identification Module
 316  */
 317 #undef CONFIG_FSL_IIM
 318
 319 /*
 320  * EEPROM configuration
 321  */
 322 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2       /* 16-bit EEPROM addr */
 323 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* ST AT24C01 */
 324 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* 10ms of delay */
 325 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4       /* 16-Byte Write Mode */
 326
 327 /*
 328  * MAC addr in EEPROM
 329  */
 330 #define CONFIG_SYS_I2C_EEPROM_BUS_NUM           0
 331 #define CONFIG_SYS_I2C_EEPROM_MAC_OFFSET        0x10
 332 /*
 333  * Enabled only to delete "ethaddr" before testing
 334  * "ethaddr" setting from EEPROM
 335  */
 336 #define CONFIG_ENV_OVERWRITE
 337
 338 /*
 339  * Ethernet configuration
 340  */
 341 #define CONFIG_MPC512x_FEC      1
 342 #define CONFIG_PHY_ADDR         0x1F
 343 #define CONFIG_MII              1       /* MII PHY management   */
 344 #define CONFIG_FEC_AN_TIMEOUT   1
 345 #define CONFIG_HAS_ETH0
 346
 347 /*
 348  * Configure on-board RTC
 349  */
 350 #define CONFIG_RTC_M41T62                       /* use M41T00 rtc via i2c */
 351 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* at address 0x68      */
 352
 353 /*
 354  * Environment
 355  */
 356 #define CONFIG_ENV_IS_IN_FLASH  1
 357 /* This has to be a multiple of the Flash sector size */
 358 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 359                                  CONFIG_SYS_MONITOR_LEN)
 360 #define CONFIG_ENV_SIZE         0x2000
 361 #define CONFIG_ENV_SECT_SIZE    0x40000         /* one sector (256K) for env */
 362
 363 /* Address and size of Redundant Environment Sector     */
 364 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 365 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 366
 367 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 368 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 369
 370 #define CONFIG_CMD_DATE
 371 #define CONFIG_CMD_EEPROM
 372 #define CONFIG_CMD_REGINFO
 373
 374 #undef CONFIG_CMD_FUSE
 375
 376 /*
 377  * Miscellaneous configurable options
 378  */
 379 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 380 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 381
 382 #ifdef CONFIG_CMD_KGDB
 383         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 384 #else
 385         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 386 #endif
 387
 388 /* Print Buffer Size */
 389 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 390 /* Max number of command args */
 391 #define CONFIG_SYS_MAXARGS      16
 392 /* Boot Argument Buffer Size */
 393 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 394 /* Decrementer freq: 1ms ticks */
 395
 396 /*
 397  * For booting Linux, the board info and command line data
 398  * have to be in the first 256 MB of memory, since this is
 399  * the maximum mapped by the Linux kernel during initialization.
 400  */
 401 /* Initial Memory map for Linux */
 402 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 403
 404 /* Cache Configuration */
 405 #define CONFIG_SYS_DCACHE_SIZE          32768
 406 #define CONFIG_SYS_CACHELINE_SIZE       32
 407 #ifdef CONFIG_CMD_KGDB
 408 /* log base 2 of the above value */
 409 #define CONFIG_SYS_CACHELINE_SHIFT      5
 410 #endif
 411
 412 #define CONFIG_SYS_HID0_INIT    0x000000000
 413 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
 414 #define CONFIG_SYS_HID2 HID2_HBE
 415
 416 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 417
 418 #ifdef CONFIG_CMD_KGDB
 419 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 420 #endif
 421
 422 /* POST support */
 423 #define CONFIG_POST             (CONFIG_SYS_POST_COPROC)
 424
 425 /*
 426  * Environment Configuration
 427  */
 428 #define CONFIG_TIMESTAMP
 429
 430 #define CONFIG_HOSTNAME         pdm360ng
 431 /* default location for tftp and bootm */
 432 #define CONFIG_LOADADDR         400000
 433
 434
 435 #define CONFIG_PREBOOT  "echo;" \
 436         "echo PDM360NG SAMPLE;" \
 437         "echo"
 438
 439 #define CONFIG_BOOTCOMMAND      "run env_cont"
 440
 441 #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES      1
 442
 443 #define OF_CPU                  "PowerPC,5121@0"
 444 #define OF_SOC_COMPAT           "fsl,mpc5121-immr"
 445 #define OF_TBCLK                (bd->bi_busfreq / 4)
 446 #define OF_STDOUT_PATH          "/soc@80000000/serial@11600"
 447
 448 /*
 449  * Include common options for all mpc5121 boards
 450  */
 451 #include "mpc5121-common.h"
 452
 453 #endif  /* __CONFIG_H */