include/configs/pdm360ng.h

   1 /*
   2  * (C) Copyright 2009-2010
   3  * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * pdm360ng board configuration file
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 #define CONFIG_PDM360NG 1
  32
  33 /*
  34  * Memory map for the PDM360NG board:
  35  *
  36  * 0x0000_0000 - 0x1FFF_FFFF    DDR RAM (512 MB)
  37  * 0x2000_0000 - 0x3FFF_FFFF    reserved (DDR RAM (512 MB)
  38  * 0x5000_0000 - 0x5001_FFFF    SRAM (128 KB)
  39  * 0x5004_0000 - 0x5005_FFFF    MRAM (CS2) (128 KB)
  40  * 0x8000_0000 - 0x803F_FFFF    IMMR (4 MB)
  41  * 0xF000_0000 - 0xF7FF_FFFF    NOR FLASH (CS0) (128 MB)
  42  * 0xF800_0000 - 0xFFFF_FFFF    NOR FLASH (CS1) (128 MB) optional
  43  */
  44
  45 /*
  46  * High Level Configuration Options
  47  */
  48 #define CONFIG_E300             1       /* E300 Family */
  49 #define CONFIG_MPC512X          1       /* MPC512X family */
  50 #define CONFIG_FSL_DIU_FB       1       /* FSL DIU */
  51
  52 #define CONFIG_SYS_TEXT_BASE    0xF0000000
  53
  54 /* Used for silent command in environment */
  55 #define CONFIG_SYS_DEVICE_NULLDEV
  56 #define CONFIG_SILENT_CONSOLE
  57
  58 /* Video */
  59 #define CONFIG_VIDEO
  60
  61 #if defined(CONFIG_VIDEO)
  62 #define CONFIG_CFB_CONSOLE
  63 #define CONFIG_VGA_AS_SINGLE_DEVICE
  64 #define CONFIG_SPLASH_SCREEN
  65 #define CONFIG_VIDEO_LOGO
  66 #define CONFIG_VIDEO_BMP_RLE8
  67 #endif
  68
  69 #define CONFIG_SYS_MPC512X_CLKIN        33333333        /* in Hz */
  70
  71 #define CONFIG_MISC_INIT_R
  72
  73 #define CONFIG_SYS_IMMR                 0x80000000
  74 #define CONFIG_SYS_DIU_ADDR             ((CONFIG_SYS_IMMR) + 0x2100)
  75
  76 /*
  77  * DDR Setup
  78  */
  79
  80 /* DDR is system memory */
  81 #define CONFIG_SYS_DDR_BASE             0x00000000
  82 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  83 #define CONFIG_SYS_MAX_RAM_SIZE         0x40000000
  84
  85 /* DDR pin mux and slew rate */
  86 #define CONFIG_SYS_IOCTRL_MUX_DDR       0x00000012
  87
  88 /* Manually set all parameters as there's no SPD etc. */
  89 /*
  90  * DDR Controller Configuration for Micron DDR2 SDRAM MT47H128M8-3
  91  *
  92  * SYS_CFG:
  93  *      [31:31] MDDRC Soft Reset:       Diabled
  94  *      [30:30] DRAM CKE pin:           Enabled
  95  *      [29:29] DRAM CLK:               Enabled
  96  *      [28:28] Command Mode:           Enabled (For initialization only)
  97  *      [27:25] DRAM Row Select:        dram_row[15:0] = magenta_address[25:10]
  98  *      [24:21] DRAM Bank Select:       dram_bank[1:0] = magenta_address[11:10]
  99  *      [20:19] Read Test:              DON'T USE
 100  *      [18:18] Self Refresh:           Enabled
 101  *      [17:17] 16bit Mode:             Disabled
 102  *      [16:13] Read Delay:             3
 103  *      [12:12] Half DQS Delay:         Disabled
 104  *      [11:11] Quarter DQS Delay:      Disabled
 105  *      [10:08] Write Delay:            2
 106  *      [07:07] Early ODT:              Disabled
 107  *      [06:06] On DIE Termination:     Enabled
 108  *      [05:05] FIFO Overflow Clear:    DON'T USE here
 109  *      [04:04] FIFO Underflow Clear:   DON'T USE here
 110  *      [03:03] FIFO Overflow Pending:  DON'T USE here
 111  *      [02:02] FIFO Underlfow Pending: DON'T USE here
 112  *      [01:01] FIFO Overlfow Enabled:  Enabled
 113  *      [00:00] FIFO Underflow Enabled: Enabled
 114  * TIME_CFG0
 115  *      [31:16] DRAM Refresh Time:      0 CSB clocks
 116  *      [15:8]  DRAM Command Time:      0 CSB clocks
 117  *      [07:00] DRAM Precharge Time:    0 CSB clocks
 118  * TIME_CFG1
 119  *      [31:26] DRAM tRFC:
 120  *      [25:21] DRAM tWR1:
 121  *      [20:17] DRAM tWRT1:
 122  *      [16:11] DRAM tDRR:
 123  *      [10:05] DRAM tRC:
 124  *      [04:00] DRAM tRAS:
 125  * TIME_CFG2
 126  *      [31:28] DRAM tRCD:
 127  *      [27:23] DRAM tFAW:
 128  *      [22:19] DRAM tRTW1:
 129  *      [18:15] DRAM tCCD:
 130  *      [14:10] DRAM tRTP:
 131  *      [09:05] DRAM tRP:
 132  *      [04:00] DRAM tRPA
 133  */
 134 #define CONFIG_SYS_MDDRC_SYS_CFG        0xEA804A40
 135 #define CONFIG_SYS_MDDRC_TIME_CFG0      0x030C3D2E
 136 #define CONFIG_SYS_MDDRC_TIME_CFG1      0x68EC1168
 137 #define CONFIG_SYS_MDDRC_TIME_CFG2      0x34310864
 138
 139 /*
 140  * Alternative 1: small RAM (128 MB) configuration
 141  */
 142 #define CONFIG_SYS_MDDRC_SYS_CFG_ALT1   0xE8604A40
 143 #define CONFIG_SYS_MDDRC_TIME_CFG0_ALT1 0x030C3D2E
 144 #define CONFIG_SYS_MDDRC_TIME_CFG1_ALT1 0x3CEC1168
 145 #define CONFIG_SYS_MDDRC_TIME_CFG2_ALT1 0x33310863
 146
 147 #define CONFIG_SYS_MDDRC_SYS_CFG_EN     0xF0000000
 148
 149 #define CONFIG_SYS_DDRCMD_NOP           0x01380000
 150 #define CONFIG_SYS_DDRCMD_PCHG_ALL      0x01100400
 151 #define CONFIG_SYS_DDRCMD_EM2           0x01020000  /* EMR2 */
 152 #define CONFIG_SYS_DDRCMD_EM3           0x01030000  /* EMR3 */
 153 /* EMR with 150 ohm ODT todo: verify */
 154 #define CONFIG_SYS_DDRCMD_EN_DLL        0x01010040
 155 #define CONFIG_SYS_DDRCMD_RES_DLL       0x01000100
 156 #define CONFIG_SYS_DDRCMD_RFSH          0x01080000
 157 #define CONFIG_SYS_MICRON_INIT_DEV_OP   0x01000432
 158 /* EMR with 150 ohm ODT todo: verify */
 159 #define CONFIG_SYS_DDRCMD_OCD_DEFAULT   0x010107C0
 160 /* EMR new command with 150 ohm ODT todo: verify */
 161 #define CONFIG_SYS_DDRCMD_OCD_EXIT      0x01010440
 162
 163 /* DDR Priority Manager Configuration */
 164 #define CONFIG_SYS_MDDRCGRP_PM_CFG1     0x00077777
 165 #define CONFIG_SYS_MDDRCGRP_PM_CFG2     0x00000000
 166 #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG  0x00000001
 167 #define CONFIG_SYS_MDDRCGRP_LUT0_MU     0xFFEEDDCC
 168 #define CONFIG_SYS_MDDRCGRP_LUT0_ML     0xBBAAAAAA
 169 #define CONFIG_SYS_MDDRCGRP_LUT1_MU     0x66666666
 170 #define CONFIG_SYS_MDDRCGRP_LUT1_ML     0x55555555
 171 #define CONFIG_SYS_MDDRCGRP_LUT2_MU     0x44444444
 172 #define CONFIG_SYS_MDDRCGRP_LUT2_ML     0x44444444
 173 #define CONFIG_SYS_MDDRCGRP_LUT3_MU     0x55555555
 174 #define CONFIG_SYS_MDDRCGRP_LUT3_ML     0x55555558
 175 #define CONFIG_SYS_MDDRCGRP_LUT4_MU     0x11111111
 176 #define CONFIG_SYS_MDDRCGRP_LUT4_ML     0x11111122
 177 #define CONFIG_SYS_MDDRCGRP_LUT0_AU     0xaaaaaaaa
 178 #define CONFIG_SYS_MDDRCGRP_LUT0_AL     0xaaaaaaaa
 179 #define CONFIG_SYS_MDDRCGRP_LUT1_AU     0x66666666
 180 #define CONFIG_SYS_MDDRCGRP_LUT1_AL     0x66666666
 181 #define CONFIG_SYS_MDDRCGRP_LUT2_AU     0x11111111
 182 #define CONFIG_SYS_MDDRCGRP_LUT2_AL     0x11111111
 183 #define CONFIG_SYS_MDDRCGRP_LUT3_AU     0x11111111
 184 #define CONFIG_SYS_MDDRCGRP_LUT3_AL     0x11111111
 185 #define CONFIG_SYS_MDDRCGRP_LUT4_AU     0x11111111
 186 #define CONFIG_SYS_MDDRCGRP_LUT4_AL     0x11111111
 187
 188 /*
 189  * NOR FLASH on the Local Bus
 190  */
 191 #define CONFIG_SYS_FLASH_CFI            /* use Common Flash Interface */
 192 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 193 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 194
 195 #define CONFIG_SYS_FLASH_BASE           0xF0000000 /* start of FLASH-Bank0 */
 196 #define CONFIG_SYS_FLASH_SIZE           0x08000000 /* max size of a Bank */
 197 /* start of FLASH-Bank1 */
 198 #define CONFIG_SYS_FLASH1_BASE          (CONFIG_SYS_FLASH_BASE + \
 199                                          CONFIG_SYS_FLASH_SIZE)
 200 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max sectors per device */
 201 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 202 #define CONFIG_SYS_FLASH_BANKS_LIST \
 203         {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH1_BASE}
 204
 205 #define CONFIG_SYS_SRAM_BASE            0x50000000
 206 #define CONFIG_SYS_SRAM_SIZE            0x00020000      /* 128 KB */
 207
 208 #define CONFIG_SYS_CS1_START            CONFIG_SYS_FLASH1_BASE
 209 #define CONFIG_SYS_CS1_SIZE             CONFIG_SYS_FLASH_SIZE
 210
 211 /* ALE active low, data size 4 bytes */
 212 #define CONFIG_SYS_CS0_CFG              0x05059350
 213 /* ALE active low, data size 4 bytes */
 214 #define CONFIG_SYS_CS1_CFG              0x05059350
 215
 216 #define CONFIG_SYS_MRAM_BASE            0x50040000
 217 #define CONFIG_SYS_MRAM_SIZE            0x00020000
 218 #define CONFIG_SYS_CS2_START            CONFIG_SYS_MRAM_BASE
 219 #define CONFIG_SYS_CS2_SIZE             CONFIG_SYS_MRAM_SIZE
 220
 221 /* ALE active low, data size 4 bytes */
 222 #define CONFIG_SYS_CS2_CFG              0x05059110
 223
 224 /* alt. CS timing for CS0, CS1, CS2 */
 225 #define CONFIG_SYS_CS_ALETIMING         0x00000007
 226
 227 /*
 228  * NAND FLASH
 229  */
 230 #define CONFIG_CMD_NAND                 /* enable NAND support */
 231 #define CONFIG_NAND_MPC5121_NFC
 232 #define CONFIG_SYS_NAND_BASE            0x40000000
 233 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 234 #define CONFIG_SYS_NAND_SELECT_DEVICE   /* driver supports mutipl. chips */
 235
 236 /*
 237  * Configuration parameters for MPC5121 NAND driver
 238  */
 239 #define CONFIG_FSL_NFC_WIDTH 1
 240 #define CONFIG_FSL_NFC_WRITE_SIZE 2048
 241 #define CONFIG_FSL_NFC_SPARE_SIZE 64
 242 #define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
 243
 244 /*
 245  * Dynamic MTD partition support
 246  */
 247 #define CONFIG_CMD_MTDPARTS
 248 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
 249 #define CONFIG_FLASH_CFI_MTD
 250 #define MTDIDS_DEFAULT          "nor0=f0000000.flash,nor1=f8000000.flash," \
 251                                                 "nand0=MPC5121 NAND"
 252
 253 /*
 254  * Flash layout
 255  */
 256 #define MTDPARTS_DEFAULT        "mtdparts=f0000000.flash:512k(u-boot)," \
 257                                                 "256k(environment1),"   \
 258                                                 "256k(environment2),"   \
 259                                                 "256k(splash-factory)," \
 260                                                 "2m(FIT: recovery),"    \
 261                                                 "4608k(fs-recovery),"   \
 262                                                 "256k(splash-customer),"\
 263                                                 "5m(FIT: kernel+dtb),"  \
 264                                                 "64m(rootfs squash)ro," \
 265                                                 "51m(userfs ubi);"      \
 266                                         "f8000000.flash:-(unused);"     \
 267                                         "MPC5121 NAND:1024m(extended-userfs)"
 268
 269 /*
 270  * Override partitions in device tree using info
 271  * in "mtdparts" environment variable
 272  */
 273 #ifdef CONFIG_CMD_MTDPARTS
 274 #define CONFIG_FDT_FIXUP_PARTITIONS
 275 #endif
 276
 277 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* Start of monitor */
 278 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* 512 kB for monitor */
 279 #ifdef  CONFIG_FSL_DIU_FB
 280 #define CONFIG_SYS_MALLOC_LEN           (6 * 1024 * 1024) /* for malloc */
 281 #else
 282 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
 283 #endif
 284
 285 /*
 286  * Serial Port
 287  */
 288 #define CONFIG_CONS_INDEX     1
 289
 290 /*
 291  * Serial console configuration
 292  */
 293 #define CONFIG_PSC_CONSOLE      6       /* console is on PSC6 */
 294 #if CONFIG_PSC_CONSOLE != 6
 295 #error CONFIG_PSC_CONSOLE must be 6
 296 #endif
 297
 298 #define CONSOLE_FIFO_TX_SIZE    FIFOC_PSC6_TX_SIZE
 299 #define CONSOLE_FIFO_TX_ADDR    FIFOC_PSC6_TX_ADDR
 300 #define CONSOLE_FIFO_RX_SIZE    FIFOC_PSC6_RX_SIZE
 301 #define CONSOLE_FIFO_RX_ADDR    FIFOC_PSC6_RX_ADDR
 302
 303 /*
 304  * Clocks in use
 305  */
 306 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN |                           \
 307                          CLOCK_SCCR1_LPC_EN |                           \
 308                          CLOCK_SCCR1_NFC_EN |                           \
 309                          CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |       \
 310                          CLOCK_SCCR1_PSCFIFO_EN |                       \
 311                          CLOCK_SCCR1_DDR_EN |                           \
 312                          CLOCK_SCCR1_FEC_EN |                           \
 313                          CLOCK_SCCR1_TPR_EN)
 314
 315 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN |           \
 316                          CLOCK_SCCR2_SPDIF_EN |         \
 317                          CLOCK_SCCR2_DIU_EN |           \
 318                          CLOCK_SCCR2_I2C_EN)
 319
 320 /*
 321  * Used PSC UART devices
 322  */
 323 #define CONFIG_SYS_PSC1
 324 #define CONFIG_SYS_PSC4
 325 #define CONFIG_SYS_PSC6
 326
 327 /*
 328  * Co-processor communication parameters
 329  */
 330 #define CONFIG_SYS_PDM360NG_COPROC_READ_DELAY   5000
 331 #define CONFIG_SYS_PDM360NG_COPROC_BAUDRATE     38400
 332
 333 /*
 334  * I2C
 335  */
 336 #define CONFIG_HARD_I2C                 /* I2C with hardware support */
 337 #define CONFIG_I2C_MULTI_BUS
 338 #define CONFIG_I2C_CMD_TREE
 339 /* I2C speed and slave address */
 340 #define CONFIG_SYS_I2C_SPEED            100000
 341 #define CONFIG_SYS_I2C_SLAVE            0x7F
 342
 343 /*
 344  * EEPROM configuration
 345  */
 346 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2       /* 16-bit EEPROM addr */
 347 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* ST AT24C01 */
 348 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* 10ms of delay */
 349 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4       /* 16-Byte Write Mode */
 350
 351 /*
 352  * MAC addr in EEPROM
 353  */
 354 #define CONFIG_SYS_I2C_EEPROM_BUS_NUM           0
 355 #define CONFIG_SYS_I2C_EEPROM_MAC_OFFSET        0x10
 356 /*
 357  * Enabled only to delete "ethaddr" before testing
 358  * "ethaddr" setting from EEPROM
 359  */
 360 #define CONFIG_ENV_OVERWRITE
 361
 362 /*
 363  * Ethernet configuration
 364  */
 365 #define CONFIG_MPC512x_FEC      1
 366 #define CONFIG_PHY_ADDR         0x1F
 367 #define CONFIG_MII              1       /* MII PHY management   */
 368 #define CONFIG_FEC_AN_TIMEOUT   1
 369 #define CONFIG_HAS_ETH0
 370
 371 /*
 372  * Configure on-board RTC
 373  */
 374 #define CONFIG_RTC_M41T62                       /* use M41T00 rtc via i2c */
 375 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* at address 0x68      */
 376
 377 /*
 378  * Environment
 379  */
 380 #define CONFIG_ENV_IS_IN_FLASH  1
 381 /* This has to be a multiple of the Flash sector size */
 382 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 383                                  CONFIG_SYS_MONITOR_LEN)
 384 #define CONFIG_ENV_SIZE         0x2000
 385 #define CONFIG_ENV_SECT_SIZE    0x40000         /* one sector (256K) for env */
 386
 387 /* Address and size of Redundant Environment Sector     */
 388 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 389 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 390
 391 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 392 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 393
 394 #include <config_cmd_default.h>
 395
 396 #define CONFIG_CMD_ASKENV
 397 #define CONFIG_CMD_DATE
 398 #define CONFIG_CMD_DHCP
 399 #define CONFIG_CMD_EEPROM
 400 #define CONFIG_CMD_I2C
 401 #define CONFIG_CMD_MII
 402 #define CONFIG_CMD_PING
 403 #define CONFIG_CMD_REGINFO
 404
 405 #ifdef CONFIG_VIDEO
 406 #define CONFIG_CMD_BMP
 407 #endif
 408
 409 /*
 410  * Miscellaneous configurable options
 411  */
 412 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 413 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 414 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 415
 416 #ifdef CONFIG_CMD_KGDB
 417         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 418 #else
 419         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 420 #endif
 421
 422 /* Print Buffer Size */
 423 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 424 /* Max number of command args */
 425 #define CONFIG_SYS_MAXARGS      16
 426 /* Boot Argument Buffer Size */
 427 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 428 /* Decrementer freq: 1ms ticks */
 429 #define CONFIG_SYS_HZ           1000
 430
 431 /*
 432  * For booting Linux, the board info and command line data
 433  * have to be in the first 256 MB of memory, since this is
 434  * the maximum mapped by the Linux kernel during initialization.
 435  */
 436 /* Initial Memory map for Linux */
 437 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 438
 439 /* Cache Configuration */
 440 #define CONFIG_SYS_DCACHE_SIZE          32768
 441 #define CONFIG_SYS_CACHELINE_SIZE       32
 442 #ifdef CONFIG_CMD_KGDB
 443 /* log base 2 of the above value */
 444 #define CONFIG_SYS_CACHELINE_SHIFT      5
 445 #endif
 446
 447 #define CONFIG_SYS_HID0_INIT    0x000000000
 448 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
 449 #define CONFIG_SYS_HID2 HID2_HBE
 450
 451 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 452
 453 #ifdef CONFIG_CMD_KGDB
 454 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 455 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 456 #endif
 457
 458 /* POST support */
 459 #define CONFIG_POST             (CONFIG_SYS_POST_COPROC)
 460
 461 /*
 462  * Environment Configuration
 463  */
 464 #define CONFIG_TIMESTAMP
 465
 466 #define CONFIG_HOSTNAME         pdm360ng
 467 /* default location for tftp and bootm */
 468 #define CONFIG_LOADADDR         400000
 469
 470 #define CONFIG_BOOTDELAY        5       /* -1 disables auto-boot */
 471
 472 #define CONFIG_PREBOOT  "echo;" \
 473         "echo PDM360NG SAMPLE;" \
 474         "echo"
 475
 476 #define CONFIG_BOOTCOMMAND      "run env_cont"
 477
 478 #define CONFIG_OF_LIBFDT        1
 479 #define CONFIG_OF_BOARD_SETUP   1
 480 #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES      1
 481 #define CONFIG_FIT
 482 #define CONFIG_FIT_VERBOSE
 483
 484 #define OF_CPU                  "PowerPC,5121@0"
 485 #define OF_SOC_COMPAT           "fsl,mpc5121-immr"
 486 #define OF_TBCLK                (bd->bi_busfreq / 4)
 487 #define OF_STDOUT_PATH          "/soc@80000000/serial@11600"
 488
 489 /*
 490  * Include common options for all mpc5121 boards
 491  */
 492 #include "mpc5121-common.h"
 493
 494 #endif  /* __CONFIG_H */