include/configs/pf5200.h

   1 /*
   2  * (C) Copyright 2003-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*************************************************************************
  25  * (c) 2005 esd gmbh Hannover
  26  *
  27  *
  28  * from IceCube.h file
  29  * by Reinhard Arlt reinhard.arlt@esd-electronics.com
  30  *
  31  *************************************************************************/
  32
  33 #ifndef __CONFIG_H
  34 #define __CONFIG_H
  35
  36 /*
  37  * High Level Configuration Options
  38  * (easy to change)
  39  */
  40
  41 #define CONFIG_MPC5200          1       /* This is an MPC5xxx CPU */
  42 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU */
  43 #define CONFIG_ICECUBE          1       /* ... on IceCube board */
  44 #define CONFIG_PF5200           1       /* ... on PF5200  board */
  45 #define CONFIG_MPC5200_DDR      1       /* ... use DDR RAM      */
  46
  47 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000        /* ... running at 33.000000MHz */
  48
  49 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH  */
  50 #define BOOTFLAG_WARM           0x02    /* Software reboot           */
  51
  52 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
  53 /*
  54  * Serial console configuration
  55  */
  56 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  57 #if 0                           /* test-only */
  58 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
  59 #else
  60 #define CONFIG_BAUDRATE         9600    /* ... at 115200 bps */
  61 #endif
  62 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  63
  64 #ifdef CONFIG_MPC5200           /* MPC5100 PCI is not supported yet. */
  65 /*
  66  * PCI Mapping:
  67  * 0x40000000 - 0x4fffffff - PCI Memory
  68  * 0x50000000 - 0x50ffffff - PCI IO Space
  69  */
  70 #define CONFIG_PCI              1
  71 #define CONFIG_PCI_PNP          1
  72 #define CONFIG_PCI_SCAN_SHOW    1
  73 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  74
  75 #define CONFIG_PCI_MEM_BUS      0x40000000
  76 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  77 #define CONFIG_PCI_MEM_SIZE     0x10000000
  78
  79 #define CONFIG_PCI_IO_BUS       0x50000000
  80 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  81 #define CONFIG_PCI_IO_SIZE      0x01000000
  82
  83 #define CONFIG_MII              1
  84 #if 0                           /* test-only !!! */
  85 #define CONFIG_NET_MULTI        1
  86 #define CONFIG_EEPRO100         1
  87 #define CONFIG_SYS_RX_ETH_BUFFER        8       /* use 8 rx buffer on eepro100  */
  88 #define CONFIG_NS8382X          1
  89 #endif
  90 #endif
  91
  92 /* Partitions */
  93 #define CONFIG_MAC_PARTITION
  94 #define CONFIG_DOS_PARTITION
  95
  96 /* USB */
  97 #if 0
  98 #define CONFIG_USB_OHCI
  99 #define CONFIG_USB_STORAGE
 100 #endif
 101
 102
 103 /*
 104  * BOOTP options
 105  */
 106 #define CONFIG_BOOTP_BOOTFILESIZE
 107 #define CONFIG_BOOTP_BOOTPATH
 108 #define CONFIG_BOOTP_GATEWAY
 109 #define CONFIG_BOOTP_HOSTNAME
 110
 111
 112 /*
 113  * Command line configuration.
 114  */
 115 #include <config_cmd_default.h>
 116
 117 #define CONFIG_CMD_BSP
 118 #define CONFIG_CMD_EEPROM
 119 #define CONFIG_CMD_ELF
 120 #define CONFIG_CMD_FAT
 121 #define CONFIG_CMD_I2C
 122 #define CONFIG_CMD_IDE
 123
 124 #ifdef CONFIG_MPC5200
 125 #define CONFIG_CMD_PCI
 126 #endif
 127
 128
 129 #if (TEXT_BASE == 0xFF000000)   /* Boot low with 16 MB Flash */
 130 #   define CONFIG_SYS_LOWBOOT           1
 131 #   define CONFIG_SYS_LOWBOOT16 1
 132 #endif
 133 #if (TEXT_BASE == 0xFF800000)   /* Boot low with  8 MB Flash */
 134 #   define CONFIG_SYS_LOWBOOT           1
 135 #   define CONFIG_SYS_LOWBOOT08 1
 136 #endif
 137
 138 /*
 139  * Autobooting
 140  */
 141 #define CONFIG_BOOTDELAY        3       /* autoboot after 5 seconds */
 142
 143 #define CONFIG_PREBOOT  "echo;" \
 144         "echo Welcome to ParaFinder pf5200;" \
 145         "echo"
 146
 147 #undef  CONFIG_BOOTARGS
 148
 149 #define CONFIG_EXTRA_ENV_SETTINGS \
 150         "netdev=eth0\0" \
 151         "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
 152         "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
 153         "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
 154         "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
 155         "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
 156         "loadaddr=01000000\0" \
 157         "serverip=192.168.2.99\0" \
 158         "gatewayip=10.0.0.79\0" \
 159         "user=mu\0" \
 160         "target=pf5200.esd\0" \
 161         "script=pf5200.bat\0" \
 162         "image=/tftpboot/vxWorks_pf5200\0" \
 163         "ipaddr=10.0.13.196\0" \
 164         "netmask=255.255.0.0\0" \
 165         ""
 166
 167 #define CONFIG_BOOTCOMMAND      "run flash_vxworks0"
 168
 169 #if defined(CONFIG_MPC5200)
 170 /*
 171  * IPB Bus clocking configuration.
 172  */
 173 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK          /* define for 133MHz speed */
 174 #endif
 175 /*
 176  * I2C configuration
 177  */
 178 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 179 #define CONFIG_SYS_I2C_MODULE           2       /* Select I2C module #1 or #2 */
 180
 181 #define CONFIG_SYS_I2C_SPEED            86000   /* 100 kHz */
 182 #define CONFIG_SYS_I2C_SLAVE            0x7F
 183
 184 /*
 185  * EEPROM configuration
 186  */
 187 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x */
 188 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 189 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5
 190 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   20
 191 #define CONFIG_SYS_I2C_MULTI_EEPROMS            1
 192 /*
 193  * Flash configuration
 194  */
 195 #define CONFIG_SYS_FLASH_BASE           0xFE000000
 196 #define CONFIG_SYS_FLASH_SIZE           0x02000000
 197 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00000000)
 198 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks      */
 199 #define CONFIG_SYS_MAX_FLASH_SECT       512
 200
 201 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 202 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 203
 204 /*
 205  * Environment settings
 206  */
 207 #if 1                           /* test-only */
 208 #define CONFIG_ENV_IS_IN_FLASH
 209 #define CONFIG_ENV_SIZE         0x10000
 210 #define CONFIG_ENV_SECT_SIZE    0x10000
 211 #define CONFIG_ENV_OVERWRITE    1
 212 #else
 213 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 214 #define CONFIG_ENV_OFFSET               0x0000  /* environment starts at the beginning of the EEPROM */
 215 #define CONFIG_ENV_SIZE         0x0400  /* 8192 bytes may be used for env vars */
 216                                    /* total size of a CAT24WC32 is 8192 bytes */
 217 #define CONFIG_ENV_OVERWRITE    1
 218 #endif
 219
 220 /*
 221  * Memory map
 222  */
 223 #define CONFIG_SYS_MBAR         0xF0000000
 224 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 225 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 226
 227 /* Use SRAM until RAM will be available */
 228 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 229 #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE       /* End of used area in DPRAM */
 230
 231 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* size in bytes reserved for initial data */
 232 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 233 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 234
 235 #define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
 236 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 237 #   define CONFIG_SYS_RAMBOOT           1
 238 #endif
 239
 240 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor   */
 241 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 242 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 243
 244 /*
 245  * Ethernet configuration
 246  */
 247 #define CONFIG_MPC5xxx_FEC      1
 248 #define CONFIG_MPC5xxx_FEC_MII100
 249 /*
 250  * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 251  */
 252 /* #define CONFIG_MPC5xxx_FEC_MII10 */
 253 #define CONFIG_PHY_ADDR         0x00
 254 #define CONFIG_UDP_CHECKSUM     1
 255
 256 /*
 257  * GPIO configuration
 258  */
 259 #define CONFIG_SYS_GPS_PORT_CONFIG      0x01052444
 260
 261 /*
 262  * Miscellaneous configurable options
 263  */
 264 #define CONFIG_SYS_LONGHELP             /* undef to save memory     */
 265 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt   */
 266 #if defined(CONFIG_CMD_KGDB)
 267 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 268 #else
 269 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 270 #endif
 271 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
 272 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 273 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 274
 275 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 276 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 277
 278 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 279
 280 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 281
 282 #define CONFIG_SYS_VXWORKS_MAC_PTR      0x00000000      /* Pass Ethernet MAC to VxWorks */
 283
 284 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs */
 285 #if defined(CONFIG_CMD_KGDB)
 286 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 287 #endif
 288
 289 /*
 290  * Various low-level settings
 291  */
 292 #if defined(CONFIG_MPC5200)
 293 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 294 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 295 #else
 296 #define CONFIG_SYS_HID0_INIT            0
 297 #define CONFIG_SYS_HID0_FINAL           0
 298 #endif
 299
 300 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 301 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 302 #define CONFIG_SYS_BOOTCS_CFG           0x0004DD00
 303
 304 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 305 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 306
 307 #define CONFIG_SYS_CS1_START            0xfd000000
 308 #define CONFIG_SYS_CS1_SIZE             0x00010000
 309 #define CONFIG_SYS_CS1_CFG              0x10101410
 310
 311 #define CONFIG_SYS_CS_BURST             0x00000000
 312 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
 313
 314 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
 315
 316 /*-----------------------------------------------------------------------
 317  * USB stuff
 318  *-----------------------------------------------------------------------
 319  */
 320 #define CONFIG_USB_CLOCK        0x0001BBBB
 321 #define CONFIG_USB_CONFIG       0x00001000
 322
 323 /*-----------------------------------------------------------------------
 324  * IDE/ATA stuff Supports IDE harddisk
 325  *-----------------------------------------------------------------------
 326  */
 327
 328 #undef  CONFIG_IDE_8xx_PCCARD   /* Use IDE with PC Card Adapter */
 329
 330 #undef  CONFIG_IDE_8xx_DIRECT   /* Direct IDE    not supported  */
 331 #undef  CONFIG_IDE_LED          /* LED   for ide not supported  */
 332
 333 #define CONFIG_IDE_RESET        /* reset for ide supported      */
 334 #define CONFIG_IDE_PREINIT
 335
 336 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 337 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 338
 339 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 340
 341 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 342
 343 /* Offset for data I/O                  */
 344 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 345
 346 /* Offset for normal register accesses  */
 347 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 348
 349 /* Offset for alternate registers       */
 350 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 351
 352 /* Interval between registers                                                */
 353 #define CONFIG_SYS_ATA_STRIDE           4
 354
 355 /*-----------------------------------------------------------------------
 356  * CPLD stuff
 357  */
 358 #define CONFIG_SYS_FPGA_XC95XL          1       /* using Xilinx XC95XL CPLD      */
 359 #define CONFIG_SYS_FPGA_MAX_SIZE        32*1024 /* 32kByte is enough for CPLD    */
 360
 361 /* CPLD program pin configuration */
 362 #define CONFIG_SYS_FPGA_PRG             0x20000000      /* JTAG TMS pin (ppc output)           */
 363 #define CONFIG_SYS_FPGA_CLK             0x10000000      /* JTAG TCK pin (ppc output)           */
 364 #define CONFIG_SYS_FPGA_DATA            0x20000000      /* JTAG TDO->TDI data pin (ppc output) */
 365 #define CONFIG_SYS_FPGA_DONE            0x10000000      /* JTAG TDI->TDO pin (ppc input)       */
 366
 367 #define JTAG_GPIO_ADDR_TMS      (CONFIG_SYS_MBAR + 0xB10)       /* JTAG TMS pin (GPS data out value reg.)      */
 368 #define JTAG_GPIO_ADDR_TCK      (CONFIG_SYS_MBAR + 0xC0C)       /* JTAG TCK pin (GPW data out value reg.)      */
 369 #define JTAG_GPIO_ADDR_TDI      (CONFIG_SYS_MBAR + 0xC0C)       /* JTAG TDO->TDI pin (GPW data out value reg.) */
 370 #define JTAG_GPIO_ADDR_TDO      (CONFIG_SYS_MBAR + 0xB14)       /* JTAG TDI->TDO pin (GPS data in value reg.)  */
 371
 372 #define JTAG_GPIO_ADDR_CFG      (CONFIG_SYS_MBAR + 0xB00)
 373 #define JTAG_GPIO_CFG_SET       0x00000000
 374 #define JTAG_GPIO_CFG_RESET     0x00F00000
 375
 376 #define JTAG_GPIO_ADDR_EN_TMS   (CONFIG_SYS_MBAR + 0xB04)
 377 #define JTAG_GPIO_TMS_EN_SET    0x20000000      /* Enable for GPIO */
 378 #define JTAG_GPIO_TMS_EN_RESET  0x00000000
 379 #define JTAG_GPIO_ADDR_DDR_TMS  (CONFIG_SYS_MBAR + 0xB0C)
 380 #define JTAG_GPIO_TMS_DDR_SET   0x20000000      /* Set as output   */
 381 #define JTAG_GPIO_TMS_DDR_RESET 0x00000000
 382
 383 #define JTAG_GPIO_ADDR_EN_TCK   (CONFIG_SYS_MBAR + 0xC00)
 384 #define JTAG_GPIO_TCK_EN_SET    0x20000000      /* Enable for GPIO */
 385 #define JTAG_GPIO_TCK_EN_RESET  0x00000000
 386 #define JTAG_GPIO_ADDR_DDR_TCK  (CONFIG_SYS_MBAR + 0xC08)
 387 #define JTAG_GPIO_TCK_DDR_SET   0x20000000      /* Set as output   */
 388 #define JTAG_GPIO_TCK_DDR_RESET 0x00000000
 389
 390 #define JTAG_GPIO_ADDR_EN_TDI   (CONFIG_SYS_MBAR + 0xC00)
 391 #define JTAG_GPIO_TDI_EN_SET    0x10000000      /* Enable as GPIO  */
 392 #define JTAG_GPIO_TDI_EN_RESET  0x00000000
 393 #define JTAG_GPIO_ADDR_DDR_TDI  (CONFIG_SYS_MBAR + 0xC08)
 394 #define JTAG_GPIO_TDI_DDR_SET   0x10000000      /* Set as output   */
 395 #define JTAG_GPIO_TDI_DDR_RESET 0x00000000
 396
 397 #define JTAG_GPIO_ADDR_EN_TDO   (CONFIG_SYS_MBAR + 0xB04)
 398 #define JTAG_GPIO_TDO_EN_SET    0x10000000      /* Enable as GPIO  */
 399 #define JTAG_GPIO_TDO_EN_RESET  0x00000000
 400 #define JTAG_GPIO_ADDR_DDR_TDO  (CONFIG_SYS_MBAR + 0xB0C)
 401 #define JTAG_GPIO_TDO_DDR_SET   0x00000000
 402 #define JTAG_GPIO_TDO_DDR_RESET 0x10000000      /* Set as input    */
 403
 404 #endif                          /* __CONFIG_H */