include/configs/pf5200.h

   1 /*
   2  * (C) Copyright 2003-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*************************************************************************
  25  * (c) 2005 esd gmbh Hannover
  26  *
  27  *
  28  * from IceCube.h file
  29  * by Reinhard Arlt reinhard.arlt@esd-electronics.com
  30  *
  31  *************************************************************************/
  32
  33 #ifndef __CONFIG_H
  34 #define __CONFIG_H
  35
  36 /*
  37  * High Level Configuration Options
  38  * (easy to change)
  39  */
  40
  41 #define CONFIG_MPC5200          1       /* This is an MPC5xxx CPU */
  42 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU */
  43 #define CONFIG_ICECUBE          1       /* ... on IceCube board */
  44 #define CONFIG_PF5200           1       /* ... on PF5200  board */
  45 #define CONFIG_MPC5200_DDR      1       /* ... use DDR RAM      */
  46
  47 #define CFG_MPC5XXX_CLKIN       33000000        /* ... running at 33.000000MHz */
  48
  49 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH  */
  50 #define BOOTFLAG_WARM           0x02    /* Software reboot           */
  51
  52 /*
  53  * Serial console configuration
  54  */
  55 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  56 #if 0                           /* test-only */
  57 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
  58 #else
  59 #define CONFIG_BAUDRATE         9600    /* ... at 115200 bps */
  60 #endif
  61 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
  62
  63 #ifdef CONFIG_MPC5200           /* MPC5100 PCI is not supported yet. */
  64 /*
  65  * PCI Mapping:
  66  * 0x40000000 - 0x4fffffff - PCI Memory
  67  * 0x50000000 - 0x50ffffff - PCI IO Space
  68  */
  69 #define CONFIG_PCI              1
  70 #define CONFIG_PCI_PNP          1
  71 #define CONFIG_PCI_SCAN_SHOW    1
  72
  73 #define CONFIG_PCI_MEM_BUS      0x40000000
  74 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  75 #define CONFIG_PCI_MEM_SIZE     0x10000000
  76
  77 #define CONFIG_PCI_IO_BUS       0x50000000
  78 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  79 #define CONFIG_PCI_IO_SIZE      0x01000000
  80
  81 #define CONFIG_MII              1
  82 #if 0                           /* test-only !!! */
  83 #define CONFIG_NET_MULTI        1
  84 #define CONFIG_EEPRO100         1
  85 #define CFG_RX_ETH_BUFFER       8       /* use 8 rx buffer on eepro100  */
  86 #define CONFIG_NS8382X          1
  87 #endif
  88 #endif
  89
  90 /* Partitions */
  91 #define CONFIG_MAC_PARTITION
  92 #define CONFIG_DOS_PARTITION
  93
  94 /* USB */
  95 #if 0
  96 #define CONFIG_USB_OHCI
  97 #define CONFIG_USB_STORAGE
  98 #endif
  99
 100
 101 /*
 102  * BOOTP options
 103  */
 104 #define CONFIG_BOOTP_BOOTFILESIZE
 105 #define CONFIG_BOOTP_BOOTPATH
 106 #define CONFIG_BOOTP_GATEWAY
 107 #define CONFIG_BOOTP_HOSTNAME
 108
 109
 110 /*
 111  * Command line configuration.
 112  */
 113 #include <config_cmd_default.h>
 114
 115 #define CONFIG_CMD_BSP
 116 #define CONFIG_CMD_EEPROM
 117 #define CONFIG_CMD_ELF
 118 #define CONFIG_CMD_FAT
 119 #define CONFIG_CMD_I2C
 120 #define CONFIG_CMD_IDE
 121
 122 #ifdef CONFIG_MPC5200
 123 #define CONFIG_CMD_PCI
 124 #endif
 125
 126
 127 #if (TEXT_BASE == 0xFF000000)   /* Boot low with 16 MB Flash */
 128 #   define CFG_LOWBOOT          1
 129 #   define CFG_LOWBOOT16        1
 130 #endif
 131 #if (TEXT_BASE == 0xFF800000)   /* Boot low with  8 MB Flash */
 132 #   define CFG_LOWBOOT          1
 133 #   define CFG_LOWBOOT08        1
 134 #endif
 135
 136 /*
 137  * Autobooting
 138  */
 139 #define CONFIG_BOOTDELAY        3       /* autoboot after 5 seconds */
 140
 141 #define CONFIG_PREBOOT  "echo;" \
 142         "echo Welcome to ParaFinder pf5200;" \
 143         "echo"
 144
 145 #undef  CONFIG_BOOTARGS
 146
 147 #define CONFIG_EXTRA_ENV_SETTINGS \
 148         "netdev=eth0\0" \
 149         "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
 150         "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
 151         "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
 152         "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
 153         "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
 154         "loadaddr=01000000\0" \
 155         "serverip=192.168.2.99\0" \
 156         "gatewayip=10.0.0.79\0" \
 157         "user=mu\0" \
 158         "target=pf5200.esd\0" \
 159         "script=pf5200.bat\0" \
 160         "image=/tftpboot/vxWorks_pf5200\0" \
 161         "ipaddr=10.0.13.196\0" \
 162         "netmask=255.255.0.0\0" \
 163         ""
 164
 165 #define CONFIG_BOOTCOMMAND      "run flash_vxworks0"
 166
 167 #if defined(CONFIG_MPC5200)
 168 /*
 169  * IPB Bus clocking configuration.
 170  */
 171 #undef CFG_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
 172 #endif
 173 /*
 174  * I2C configuration
 175  */
 176 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 177 #define CFG_I2C_MODULE          2       /* Select I2C module #1 or #2 */
 178
 179 #define CFG_I2C_SPEED           86000   /* 100 kHz */
 180 #define CFG_I2C_SLAVE           0x7F
 181
 182 /*
 183  * EEPROM configuration
 184  */
 185 #define CFG_I2C_EEPROM_ADDR             0x50    /* 1010000x */
 186 #define CFG_I2C_EEPROM_ADDR_LEN         2
 187 #define CFG_EEPROM_PAGE_WRITE_BITS      5
 188 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  20
 189 #define CFG_I2C_MULTI_EEPROMS           1
 190 /*
 191  * Flash configuration
 192  */
 193 #define CFG_FLASH_BASE          0xFE000000
 194 #define CFG_FLASH_SIZE          0x02000000
 195 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x00000000)
 196 #define CFG_MAX_FLASH_BANKS     1       /* max num of memory banks      */
 197 #define CFG_MAX_FLASH_SECT      512
 198
 199 #define CFG_FLASH_ERASE_TOUT    240000  /* Flash Erase Timeout (in ms)  */
 200 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 201
 202 /*
 203  * Environment settings
 204  */
 205 #if 1                           /* test-only */
 206 #define CFG_ENV_IS_IN_FLASH     0
 207 #define CFG_ENV_SIZE            0x10000
 208 #define CFG_ENV_SECT_SIZE       0x10000
 209 #define CONFIG_ENV_OVERWRITE    1
 210 #else
 211 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 212 #define CFG_ENV_OFFSET          0x0000  /* environment starts at the beginning of the EEPROM */
 213 #define CFG_ENV_SIZE            0x0400  /* 8192 bytes may be used for env vars */
 214                                    /* total size of a CAT24WC32 is 8192 bytes */
 215 #define CONFIG_ENV_OVERWRITE    1
 216 #endif
 217
 218 /*
 219  * Memory map
 220  */
 221 #define CFG_MBAR                0xF0000000
 222 #define CFG_SDRAM_BASE          0x00000000
 223 #define CFG_DEFAULT_MBAR        0x80000000
 224
 225 /* Use SRAM until RAM will be available */
 226 #define CFG_INIT_RAM_ADDR       MPC5XXX_SRAM
 227 #define CFG_INIT_RAM_END        MPC5XXX_SRAM_SIZE       /* End of used area in DPRAM */
 228
 229 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 230 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 231 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 232
 233 #define CFG_MONITOR_BASE    TEXT_BASE
 234 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 235 #   define CFG_RAMBOOT          1
 236 #endif
 237
 238 #define CFG_MONITOR_LEN         (192 << 10)     /* Reserve 192 kB for Monitor   */
 239 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 240 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 241
 242 /*
 243  * Ethernet configuration
 244  */
 245 #define CONFIG_MPC5xxx_FEC      1
 246 /*
 247  * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 248  */
 249 /* #define CONFIG_FEC_10MBIT 1 */
 250 #define CONFIG_PHY_ADDR         0x00
 251 #define CONFIG_UDP_CHECKSUM     1
 252
 253 /*
 254  * GPIO configuration
 255  */
 256 #define CFG_GPS_PORT_CONFIG     0x01052444
 257
 258 /*
 259  * Miscellaneous configurable options
 260  */
 261 #define CFG_LONGHELP            /* undef to save memory     */
 262 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt   */
 263 #if defined(CONFIG_CMD_KGDB)
 264 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size  */
 265 #else
 266 #define CFG_CBSIZE              256     /* Console I/O Buffer Size  */
 267 #endif
 268 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size */
 269 #define CFG_MAXARGS             16      /* max number of command args   */
 270 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 271
 272 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 273 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM  */
 274
 275 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 276
 277 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 278
 279 #define CFG_VXWORKS_MAC_PTR     0x00000000      /* Pass Ethernet MAC to VxWorks */
 280
 281 #define CFG_CACHELINE_SIZE      32      /* For MPC5xxx CPUs */
 282 #if defined(CONFIG_CMD_KGDB)
 283 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
 284 #endif
 285
 286 /*
 287  * Various low-level settings
 288  */
 289 #if defined(CONFIG_MPC5200)
 290 #define CFG_HID0_INIT           HID0_ICE | HID0_ICFI
 291 #define CFG_HID0_FINAL          HID0_ICE
 292 #else
 293 #define CFG_HID0_INIT           0
 294 #define CFG_HID0_FINAL          0
 295 #endif
 296
 297 #define CFG_BOOTCS_START        CFG_FLASH_BASE
 298 #define CFG_BOOTCS_SIZE         CFG_FLASH_SIZE
 299 #define CFG_BOOTCS_CFG          0x0004DD00
 300
 301 #define CFG_CS0_START           CFG_FLASH_BASE
 302 #define CFG_CS0_SIZE            CFG_FLASH_SIZE
 303
 304 #define CFG_CS1_START           0xfd000000
 305 #define CFG_CS1_SIZE            0x00010000
 306 #define CFG_CS1_CFG             0x10101410
 307
 308 #define CFG_CS_BURST            0x00000000
 309 #define CFG_CS_DEADCYCLE        0x33333333
 310
 311 #define CFG_RESET_ADDRESS       0xff000000
 312
 313 /*-----------------------------------------------------------------------
 314  * USB stuff
 315  *-----------------------------------------------------------------------
 316  */
 317 #define CONFIG_USB_CLOCK        0x0001BBBB
 318 #define CONFIG_USB_CONFIG       0x00001000
 319
 320 /*-----------------------------------------------------------------------
 321  * IDE/ATA stuff Supports IDE harddisk
 322  *-----------------------------------------------------------------------
 323  */
 324
 325 #undef  CONFIG_IDE_8xx_PCCARD   /* Use IDE with PC Card Adapter */
 326
 327 #undef  CONFIG_IDE_8xx_DIRECT   /* Direct IDE    not supported  */
 328 #undef  CONFIG_IDE_LED          /* LED   for ide not supported  */
 329
 330 #define CONFIG_IDE_RESET        /* reset for ide supported      */
 331 #define CONFIG_IDE_PREINIT
 332
 333 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 334 #define CFG_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus     */
 335
 336 #define CFG_ATA_IDE0_OFFSET     0x0000
 337
 338 #define CFG_ATA_BASE_ADDR       MPC5XXX_ATA
 339
 340 /* Offset for data I/O                  */
 341 #define CFG_ATA_DATA_OFFSET     (0x0060)
 342
 343 /* Offset for normal register accesses  */
 344 #define CFG_ATA_REG_OFFSET      (CFG_ATA_DATA_OFFSET)
 345
 346 /* Offset for alternate registers       */
 347 #define CFG_ATA_ALT_OFFSET      (0x005C)
 348
 349 /* Interval between registers                                                */
 350 #define CFG_ATA_STRIDE          4
 351
 352 /*-----------------------------------------------------------------------
 353  * CPLD stuff
 354  */
 355 #define CFG_FPGA_XC95XL         1       /* using Xilinx XC95XL CPLD      */
 356 #define CFG_FPGA_MAX_SIZE       32*1024 /* 32kByte is enough for CPLD    */
 357
 358 /* CPLD program pin configuration */
 359 #define CFG_FPGA_PRG            0x20000000      /* JTAG TMS pin (ppc output)           */
 360 #define CFG_FPGA_CLK            0x10000000      /* JTAG TCK pin (ppc output)           */
 361 #define CFG_FPGA_DATA           0x20000000      /* JTAG TDO->TDI data pin (ppc output) */
 362 #define CFG_FPGA_DONE           0x10000000      /* JTAG TDI->TDO pin (ppc input)       */
 363
 364 #define JTAG_GPIO_ADDR_TMS      (CFG_MBAR + 0xB10)      /* JTAG TMS pin (GPS data out value reg.)      */
 365 #define JTAG_GPIO_ADDR_TCK      (CFG_MBAR + 0xC0C)      /* JTAG TCK pin (GPW data out value reg.)      */
 366 #define JTAG_GPIO_ADDR_TDI      (CFG_MBAR + 0xC0C)      /* JTAG TDO->TDI pin (GPW data out value reg.) */
 367 #define JTAG_GPIO_ADDR_TDO      (CFG_MBAR + 0xB14)      /* JTAG TDI->TDO pin (GPS data in value reg.)  */
 368
 369 #define JTAG_GPIO_ADDR_CFG      (CFG_MBAR + 0xB00)
 370 #define JTAG_GPIO_CFG_SET       0x00000000
 371 #define JTAG_GPIO_CFG_RESET     0x00F00000
 372
 373 #define JTAG_GPIO_ADDR_EN_TMS   (CFG_MBAR + 0xB04)
 374 #define JTAG_GPIO_TMS_EN_SET    0x20000000      /* Enable for GPIO */
 375 #define JTAG_GPIO_TMS_EN_RESET  0x00000000
 376 #define JTAG_GPIO_ADDR_DDR_TMS  (CFG_MBAR + 0xB0C)
 377 #define JTAG_GPIO_TMS_DDR_SET   0x20000000      /* Set as output   */
 378 #define JTAG_GPIO_TMS_DDR_RESET 0x00000000
 379
 380 #define JTAG_GPIO_ADDR_EN_TCK   (CFG_MBAR + 0xC00)
 381 #define JTAG_GPIO_TCK_EN_SET    0x20000000      /* Enable for GPIO */
 382 #define JTAG_GPIO_TCK_EN_RESET  0x00000000
 383 #define JTAG_GPIO_ADDR_DDR_TCK  (CFG_MBAR + 0xC08)
 384 #define JTAG_GPIO_TCK_DDR_SET   0x20000000      /* Set as output   */
 385 #define JTAG_GPIO_TCK_DDR_RESET 0x00000000
 386
 387 #define JTAG_GPIO_ADDR_EN_TDI   (CFG_MBAR + 0xC00)
 388 #define JTAG_GPIO_TDI_EN_SET    0x10000000      /* Enable as GPIO  */
 389 #define JTAG_GPIO_TDI_EN_RESET  0x00000000
 390 #define JTAG_GPIO_ADDR_DDR_TDI  (CFG_MBAR + 0xC08)
 391 #define JTAG_GPIO_TDI_DDR_SET   0x10000000      /* Set as output   */
 392 #define JTAG_GPIO_TDI_DDR_RESET 0x00000000
 393
 394 #define JTAG_GPIO_ADDR_EN_TDO   (CFG_MBAR + 0xB04)
 395 #define JTAG_GPIO_TDO_EN_SET    0x10000000      /* Enable as GPIO  */
 396 #define JTAG_GPIO_TDO_EN_RESET  0x00000000
 397 #define JTAG_GPIO_ADDR_DDR_TDO  (CFG_MBAR + 0xB0C)
 398 #define JTAG_GPIO_TDO_DDR_SET   0x00000000
 399 #define JTAG_GPIO_TDO_DDR_RESET 0x10000000      /* Set as input    */
 400
 401 #endif                          /* __CONFIG_H */