include/configs/pm9263.h

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian.pop@leadtechdesign.com>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  * Ilko Iliev <www.ronetix.at>
   6  *
   7  * Configuation settings for the RONETIX PM9263 board.
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * SoC must be defined first, before hardware.h is included.
  33  * In this case SoC is defined in boards.cfg.
  34  */
  35 #include <asm/hardware.h>
  36
  37 /* ARM asynchronous clock */
  38 #define CONFIG_DISPLAY_CPUINFO
  39 #define CONFIG_DISPLAY_BOARDINFO
  40
  41 #define MASTER_PLL_DIV          6
  42 #define MASTER_PLL_MUL          65
  43 #define MAIN_PLL_DIV            2       /* 2 or 4 */
  44 #define CONFIG_SYS_AT91_MAIN_CLOCK      18432000
  45 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768           /* slow clock xtal */
  46
  47 #define CONFIG_SYS_HZ           1000
  48
  49 #define CONFIG_SYS_AT91_CPU_NAME        "AT91SAM9263"
  50 #define CONFIG_PM9263           1       /* on a Ronetix PM9263 Board    */
  51 #define CONFIG_ARCH_CPU_INIT
  52 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff  */
  53 #define CONFIG_SYS_TEXT_BASE    0
  54
  55 /* clocks */
  56 #define CONFIG_SYS_MOR_VAL                                              \
  57                 (AT91_PMC_MOR_MOSCEN |                                  \
  58                  (255 << 8))            /* Main Oscillator Start-up Time */
  59 #define CONFIG_SYS_PLLAR_VAL                                            \
  60                 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
  61                  AT91_PMC_PLLXR_OUT(3) |                                \
  62                  AT91_PMC_PLLXR_PLLCOUNT(0x3f) |        /* PLL Counter */\
  63                  (2 << 28) |            /* PLL Clock Frequency Range */ \
  64                  ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
  65
  66 #if (MAIN_PLL_DIV == 2)
  67 /* PCK/2 = MCK Master Clock from PLLA */
  68 #define CONFIG_SYS_MCKR1_VAL            \
  69                 (AT91_PMC_MCKR_CSS_SLOW |       \
  70                  AT91_PMC_MCKR_PRES_1 | \
  71                  AT91_PMC_MCKR_MDIV_2)
  72 /* PCK/2 = MCK Master Clock from PLLA */
  73 #define CONFIG_SYS_MCKR2_VAL            \
  74                 (AT91_PMC_MCKR_CSS_PLLA |       \
  75                  AT91_PMC_MCKR_PRES_1 | \
  76                  AT91_PMC_MCKR_MDIV_2)
  77 #else
  78 /* PCK/4 = MCK Master Clock from PLLA */
  79 #define CONFIG_SYS_MCKR1_VAL                    \
  80                 (AT91_PMC_MCKR_CSS_SLOW |               \
  81                  AT91_PMC_MCKR_PRES_1 |         \
  82                  AT91_PMC_MCKR_MDIV_4)
  83 /* PCK/4 = MCK Master Clock from PLLA */
  84 #define CONFIG_SYS_MCKR2_VAL                    \
  85                 (AT91_PMC_MCKR_CSS_PLLA |               \
  86                  AT91_PMC_MCKR_PRES_1 |         \
  87                  AT91_PMC_MCKR_MDIV_4)
  88 #endif
  89 /* define PDC[31:16] as DATA[31:16] */
  90 #define CONFIG_SYS_PIOD_PDR_VAL1        0xFFFF0000
  91 /* no pull-up for D[31:16] */
  92 #define CONFIG_SYS_PIOD_PPUDR_VAL       0xFFFF0000
  93 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
  94 #define CONFIG_SYS_MATRIX_EBI0CSA_VAL                                   \
  95         (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |       \
  96          AT91_MATRIX_CSA_EBI_CS1A)
  97
  98 /* SDRAM */
  99 /* SDRAMC_MR Mode register */
 100 #define CONFIG_SYS_SDRC_MR_VAL1         0
 101 /* SDRAMC_TR - Refresh Timer register */
 102 #define CONFIG_SYS_SDRC_TR_VAL1         0x3AA
 103 /* SDRAMC_CR - Configuration register*/
 104 #define CONFIG_SYS_SDRC_CR_VAL                                                  \
 105                 (AT91_SDRAMC_NC_9 |                                             \
 106                  AT91_SDRAMC_NR_13 |                                            \
 107                  AT91_SDRAMC_NB_4 |                                             \
 108                  AT91_SDRAMC_CAS_2 |                                            \
 109                  AT91_SDRAMC_DBW_32 |                                           \
 110                  (2 <<  8) |    /* tWR -  Write Recovery Delay */               \
 111                  (7 << 12) |    /* tRC -  Row Cycle Delay */                    \
 112                  (2 << 16) |    /* tRP -  Row Precharge Delay */                \
 113                  (2 << 20) |    /* tRCD - Row to Column Delay */                \
 114                  (5 << 24) |    /* tRAS - Active to Precharge Delay */          \
 115                  (8 << 28))     /* tXSR - Exit Self Refresh to Active Delay */
 116
 117 /* Memory Device Register -> SDRAM */
 118 #define CONFIG_SYS_SDRC_MDR_VAL         AT91_SDRAMC_MD_SDRAM
 119 #define CONFIG_SYS_SDRC_MR_VAL2         AT91_SDRAMC_MODE_PRECHARGE
 120 #define CONFIG_SYS_SDRAM_VAL1           0               /* SDRAM_BASE */
 121 #define CONFIG_SYS_SDRC_MR_VAL3         AT91_SDRAMC_MODE_REFRESH
 122 #define CONFIG_SYS_SDRAM_VAL2           0               /* SDRAM_BASE */
 123 #define CONFIG_SYS_SDRAM_VAL3           0               /* SDRAM_BASE */
 124 #define CONFIG_SYS_SDRAM_VAL4           0               /* SDRAM_BASE */
 125 #define CONFIG_SYS_SDRAM_VAL5           0               /* SDRAM_BASE */
 126 #define CONFIG_SYS_SDRAM_VAL6           0               /* SDRAM_BASE */
 127 #define CONFIG_SYS_SDRAM_VAL7           0               /* SDRAM_BASE */
 128 #define CONFIG_SYS_SDRAM_VAL8           0               /* SDRAM_BASE */
 129 #define CONFIG_SYS_SDRAM_VAL9           0               /* SDRAM_BASE */
 130 #define CONFIG_SYS_SDRC_MR_VAL4         AT91_SDRAMC_MODE_LMR
 131 #define CONFIG_SYS_SDRAM_VAL10          0               /* SDRAM_BASE */
 132 #define CONFIG_SYS_SDRC_MR_VAL5         AT91_SDRAMC_MODE_NORMAL
 133 #define CONFIG_SYS_SDRAM_VAL11          0               /* SDRAM_BASE */
 134 #define CONFIG_SYS_SDRC_TR_VAL2         1200            /* SDRAM_TR */
 135 #define CONFIG_SYS_SDRAM_VAL12          0               /* SDRAM_BASE */
 136
 137 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
 138 #define CONFIG_SYS_SMC0_SETUP0_VAL                                      \
 139                 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |   \
 140                  AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
 141 #define CONFIG_SYS_SMC0_PULSE0_VAL                                      \
 142                 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |   \
 143                  AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
 144 #define CONFIG_SYS_SMC0_CYCLE0_VAL      \
 145                 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
 146 #define CONFIG_SYS_SMC0_MODE0_VAL                               \
 147                 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |  \
 148                  AT91_SMC_MODE_DBW_16 |                         \
 149                  AT91_SMC_MODE_TDF |                            \
 150                  AT91_SMC_MODE_TDF_CYCLE(6))
 151
 152 /* user reset enable */
 153 #define CONFIG_SYS_RSTC_RMR_VAL                 \
 154                 (AT91_RSTC_KEY |                \
 155                 AT91_RSTC_CR_PROCRST |          \
 156                 AT91_RSTC_MR_ERSTL(1) | \
 157                 AT91_RSTC_MR_ERSTL(2))
 158
 159 /* Disable Watchdog */
 160 #define CONFIG_SYS_WDTC_WDMR_VAL                                \
 161                 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
 162                  AT91_WDT_MR_WDV(0xfff) |                                       \
 163                  AT91_WDT_MR_WDDIS |                            \
 164                  AT91_WDT_MR_WDD(0xfff))
 165
 166 #define CONFIG_CMDLINE_TAG      1       /* enable passing of ATAGs */
 167 #define CONFIG_SETUP_MEMORY_TAGS 1
 168 #define CONFIG_INITRD_TAG       1
 169
 170 #undef CONFIG_SKIP_LOWLEVEL_INIT
 171 #define CONFIG_USER_LOWLEVEL_INIT       1
 172
 173 /*
 174  * Hardware drivers
 175  */
 176 #define CONFIG_AT91_GPIO        1
 177 #define CONFIG_ATMEL_USART      1
 178 #define CONFIG_USART_BASE               ATMEL_BASE_DBGU
 179 #define CONFIG_USART_ID                 ATMEL_ID_SYS
 180
 181 /* LCD */
 182 #define CONFIG_LCD                      1
 183 #define LCD_BPP                         LCD_COLOR8
 184 #define CONFIG_LCD_LOGO                 1
 185 #undef LCD_TEST_PATTERN
 186 #define CONFIG_LCD_INFO                 1
 187 #define CONFIG_LCD_INFO_BELOW_LOGO      1
 188 #define CONFIG_SYS_WHITE_ON_BLACK       1
 189 #define CONFIG_ATMEL_LCD                1
 190 #define CONFIG_ATMEL_LCD_BGR555         1
 191 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    1
 192
 193 #define CONFIG_LCD_IN_PSRAM             1
 194
 195 /* LED */
 196 #define CONFIG_AT91_LED
 197 #define CONFIG_RED_LED          AT91_PIO_PORTB, 7       /* this is the power led */
 198 #define CONFIG_GREEN_LED        AT91_PIO_PORTB, 8       /* this is the user1 led */
 199
 200 #define CONFIG_BOOTDELAY        3
 201
 202 /*
 203  * BOOTP options
 204  */
 205 #define CONFIG_BOOTP_BOOTFILESIZE       1
 206 #define CONFIG_BOOTP_BOOTPATH           1
 207 #define CONFIG_BOOTP_GATEWAY            1
 208 #define CONFIG_BOOTP_HOSTNAME           1
 209
 210 /*
 211  * Command line configuration.
 212  */
 213 #include <config_cmd_default.h>
 214 #undef CONFIG_CMD_BDI
 215 #undef CONFIG_CMD_IMI
 216 #undef CONFIG_CMD_FPGA
 217 #undef CONFIG_CMD_LOADS
 218 #undef CONFIG_CMD_IMLS
 219
 220 #define CONFIG_CMD_CACHE
 221 #define CONFIG_CMD_PING         1
 222 #define CONFIG_CMD_DHCP         1
 223 #define CONFIG_CMD_NAND         1
 224 #define CONFIG_CMD_USB          1
 225
 226 /* SDRAM */
 227 #define CONFIG_NR_DRAM_BANKS    1
 228 #define PHYS_SDRAM              0x20000000
 229 #define PHYS_SDRAM_SIZE         0x04000000      /* 64 megs */
 230
 231 /* DataFlash */
 232 #define CONFIG_ATMEL_DATAFLASH_SPI
 233 #define CONFIG_HAS_DATAFLASH                    1
 234 #define CONFIG_SYS_SPI_WRITE_TOUT               (5 * CONFIG_SYS_HZ)
 235 #define CONFIG_SYS_MAX_DATAFLASH_BANKS          1
 236 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0     0xC0000000      /* CS0 */
 237 #define AT91_SPI_CLK                            15000000
 238 #define DATAFLASH_TCSS                          (0x1a << 16)
 239 #define DATAFLASH_TCHS                          (0x1 << 24)
 240
 241 /* NOR flash, if populated */
 242 #define CONFIG_SYS_FLASH_CFI            1
 243 #define CONFIG_FLASH_CFI_DRIVER         1
 244 #define PHYS_FLASH_1                    0x10000000
 245 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 246 #define CONFIG_SYS_MAX_FLASH_SECT       256
 247 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 248
 249 /* NAND flash */
 250 #ifdef CONFIG_CMD_NAND
 251 #define CONFIG_NAND_ATMEL
 252 #define CONFIG_SYS_NAND_MAX_CHIPS       1
 253 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 254 #define CONFIG_SYS_NAND_BASE            0x40000000
 255 #define CONFIG_SYS_NAND_DBW_8           1
 256 /* our ALE is AD21 */
 257 #define CONFIG_SYS_NAND_MASK_ALE        (1 << 21)
 258 /* our CLE is AD22 */
 259 #define CONFIG_SYS_NAND_MASK_CLE        (1 << 22)
 260 #define CONFIG_SYS_NAND_ENABLE_PIN      AT91_PIO_PORTD, 15
 261 #define CONFIG_SYS_NAND_READY_PIN       AT91_PIO_PORTB, 30
 262
 263 #endif
 264
 265 #define CONFIG_CMD_JFFS2                1
 266 #define CONFIG_JFFS2_CMDLINE            1
 267 #define CONFIG_JFFS2_NAND               1
 268 #define CONFIG_JFFS2_DEV                "nand0" /* NAND device jffs2 lives on */
 269 #define CONFIG_JFFS2_PART_OFFSET        0       /* start of jffs2 partition */
 270 #define CONFIG_JFFS2_PART_SIZE          (256 * 1024 * 1024) /* partition size*/
 271
 272 /* PSRAM */
 273 #define PHYS_PSRAM                      0x70000000
 274 #define PHYS_PSRAM_SIZE                 0x00400000      /* 4MB */
 275 /* Slave EBI1, PSRAM connected */
 276 #define CONFIG_PSRAM_SCFG               (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY   | \
 277                                          AT91_MATRIX_SCFG_FIXED_DEFMSTR(5)      | \
 278                                          AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED    | \
 279                                          AT91_MATRIX_SCFG_SLOT_CYCLE(255))
 280
 281 /* Ethernet */
 282 #define CONFIG_MACB                     1
 283 #define CONFIG_RMII                     1
 284 #define CONFIG_NET_MULTI                1
 285 #define CONFIG_NET_RETRY_COUNT          20
 286 #define CONFIG_RESET_PHY_R              1
 287
 288 /* USB */
 289 #define CONFIG_USB_ATMEL
 290 #define CONFIG_USB_OHCI_NEW                     1
 291 #define CONFIG_DOS_PARTITION                    1
 292 #define CONFIG_SYS_USB_OHCI_CPU_INIT            1
 293 #define CONFIG_SYS_USB_OHCI_REGS_BASE           0x00a00000      /* AT91SAM9263_UHP_BASE */
 294 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91sam9263"
 295 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
 296 #define CONFIG_USB_STORAGE                      1
 297
 298 #define CONFIG_SYS_LOAD_ADDR                    0x22000000      /* load address */
 299
 300 #define CONFIG_SYS_MEMTEST_START                PHYS_SDRAM
 301 #define CONFIG_SYS_MEMTEST_END                  0x23e00000
 302
 303 #define CONFIG_SYS_USE_FLASH    1
 304 #undef CONFIG_SYS_USE_DATAFLASH
 305 #undef CONFIG_SYS_USE_NANDFLASH
 306
 307 #ifdef CONFIG_SYS_USE_DATAFLASH
 308
 309 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
 310 #define CONFIG_ENV_IS_IN_DATAFLASH
 311 #define CFG_MONITOR_BASE        (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
 312 #define CONFIG_ENV_OFFSET       0x4200
 313 #define CONFIG_ENV_ADDR         (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
 314 #define CONFIG_ENV_SIZE         0x4200
 315 #define CONFIG_BOOTCOMMAND      "cp.b 0xC0042000 0x22000000 0x210000; bootm"
 316 #define CONFIG_BOOTARGS         "console=ttyS0,115200 " \
 317                                 "root=/dev/mtdblock0 " \
 318                                 "mtdparts=atmel_nand:-(root) "\
 319                                 "rw rootfstype=jffs2"
 320
 321 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */
 322
 323 /* bootstrap + u-boot + env + linux in nandflash */
 324 #define CONFIG_ENV_IS_IN_NAND
 325 #define CONFIG_ENV_OFFSET               0x60000
 326 #define CONFIG_ENV_OFFSET_REDUND        0x80000
 327 #define CONFIG_ENV_SIZE         0x20000         /* 1 sector = 128 kB */
 328 #define CONFIG_BOOTCOMMAND      "nand read 0x22000000 0xA0000 0x200000; bootm"
 329 #define CONFIG_BOOTARGS         "console=ttyS0,115200 "         \
 330                                 "root=/dev/mtdblock5 "          \
 331                                 "mtdparts=atmel_nand:"          \
 332                                         "128k(bootstrap)ro,"    \
 333                                         "256k(uboot)ro,"        \
 334                                         "128k(env1)ro,"         \
 335                                         "128k(env2)ro,"         \
 336                                         "2M(linux),"            \
 337                                         "-(root) "              \
 338                                 "rw rootfstype=jffs2"
 339
 340 #elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */
 341
 342 #define CONFIG_ENV_IS_IN_FLASH  1
 343 #define CONFIG_ENV_OFFSET       0x40000
 344 #define CONFIG_ENV_SECT_SIZE    0x10000
 345 #define CONFIG_ENV_SIZE         0x10000
 346 #define CONFIG_ENV_OVERWRITE    1
 347
 348 /* JFFS Partition offset set */
 349 #define CONFIG_SYS_JFFS2_FIRST_BANK     0
 350 #define CONFIG_SYS_JFFS2_NUM_BANKS      1
 351
 352 /* 512k reserved for u-boot */
 353 #define CONFIG_SYS_JFFS2_FIRST_SECTOR   11
 354
 355 #define CONFIG_BOOTCOMMAND              "run flashboot"
 356 #define CONFIG_ROOTPATH                 /ronetix/rootfs
 357 #define CONFIG_AUTOBOOT_PROMPT          "autoboot in %d seconds\n"
 358
 359 #define CONFIG_CON_ROT                  "fbcon=rotate:3 "
 360 #define CONFIG_BOOTARGS                 "root=/dev/mtdblock4 rootfstype=jffs2 "\
 361                                         CONFIG_CON_ROT
 362
 363 #define MTDIDS_DEFAULT                  "nor0=physmap-flash.0,nand0=nand"
 364 #define MTDPARTS_DEFAULT                \
 365         "mtdparts=physmap-flash.0:"     \
 366                 "256k(u-boot)ro,"       \
 367                 "64k(u-boot-env)ro,"    \
 368                 "1408k(kernel),"        \
 369                 "-(rootfs);"            \
 370         "nand:-(nand)"
 371
 372 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 373         "mtdids=" MTDIDS_DEFAULT "\0"                           \
 374         "mtdparts=" MTDPARTS_DEFAULT "\0"                       \
 375         "partition=nand0,0\0"                                   \
 376         "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"     \
 377         "nfsargs=setenv bootargs root=/dev/nfs rw "             \
 378                 CONFIG_CON_ROT                                  \
 379                 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
 380         "addip=setenv bootargs $(bootargs) "                    \
 381                 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
 382                 ":$(hostname):eth0:off\0"                       \
 383         "ramboot=tftpboot 0x22000000 vmImage;"                  \
 384                 "run ramargs;run addip;bootm 22000000\0"        \
 385         "nfsboot=tftpboot 0x22000000 vmImage;"                  \
 386                 "run nfsargs;run addip;bootm 22000000\0"        \
 387         "flashboot=run ramargs;run addip;bootm 0x10050000\0"    \
 388         ""
 389
 390 #else
 391 #error "Undefined memory device"
 392 #endif
 393
 394 #define CONFIG_BAUDRATE                 115200
 395 #define CONFIG_SYS_BAUDRATE_TABLE       {115200 , 19200, 38400, 57600, 9600 }
 396
 397 #define CONFIG_SYS_PROMPT               "u-boot-pm9263> "
 398 #define CONFIG_SYS_CBSIZE               256
 399 #define CONFIG_SYS_MAXARGS              16
 400 #define CONFIG_SYS_PBSIZE               \
 401                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 402 #define CONFIG_SYS_LONGHELP             1
 403 #define CONFIG_CMDLINE_EDITING          1
 404
 405 /*
 406  * Size of malloc() pool
 407  */
 408 #define CONFIG_SYS_MALLOC_LEN   ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
 409
 410 #define CONFIG_SYS_SDRAM_BASE   PHYS_SDRAM
 411 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
 412                                 GENERATED_GBL_DATA_SIZE)
 413
 414 #define CONFIG_STACKSIZE                (32 * 1024)     /* regular stack */
 415
 416 #ifdef CONFIG_USE_IRQ
 417 #error CONFIG_USE_IRQ not supported
 418 #endif
 419
 420 #endif