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Merge branch 'master' of git://git.denx.de/u-boot-arm
[people/ms/u-boot.git] / include / configs / pm9263.h
1 /*
2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
5 * Ilko Iliev <www.ronetix.at>
6 *
7 * Configuation settings for the RONETIX PM9263 board.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28 #ifndef __CONFIG_H
29 #define __CONFIG_H
30
31 #define CONFIG_AT91_LEGACY
32
33 /* ARM asynchronous clock */
34 #define CONFIG_DISPLAY_CPUINFO
35 #define CONFIG_DISPLAY_BOARDINFO
36
37 #define MASTER_PLL_DIV 6
38 #define MASTER_PLL_MUL 65
39 #define MAIN_PLL_DIV 2 /* 2 or 4 */
40 #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
41
42 #define CONFIG_SYS_HZ 1000
43
44 #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
45 #define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/
46 #define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */
47 #define CONFIG_ARCH_CPU_INIT
48 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
49
50 /* clocks */
51 #define CONFIG_SYS_MOR_VAL \
52 (AT91_PMC_MOSCEN | \
53 (255 << 8)) /* Main Oscillator Start-up Time */
54 #define CONFIG_SYS_PLLAR_VAL \
55 (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
56 AT91_PMC_OUT | \
57 AT91_PMC_PLLCOUNT | /* PLL Counter */ \
58 (2 << 28) | /* PLL Clock Frequency Range */ \
59 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
60
61 #if (MAIN_PLL_DIV == 2)
62 /* PCK/2 = MCK Master Clock from PLLA */
63 #define CONFIG_SYS_MCKR1_VAL \
64 (AT91_PMC_CSS_SLOW | \
65 AT91_PMC_PRES_1 | \
66 AT91SAM9_PMC_MDIV_2 | \
67 AT91_PMC_PDIV_1)
68 /* PCK/2 = MCK Master Clock from PLLA */
69 #define CONFIG_SYS_MCKR2_VAL \
70 (AT91_PMC_CSS_PLLA | \
71 AT91_PMC_PRES_1 | \
72 AT91SAM9_PMC_MDIV_2 | \
73 AT91_PMC_PDIV_1)
74 #else
75 /* PCK/4 = MCK Master Clock from PLLA */
76 #define CONFIG_SYS_MCKR1_VAL \
77 (AT91_PMC_CSS_SLOW | \
78 AT91_PMC_PRES_1 | \
79 AT91RM9200_PMC_MDIV_3 | \
80 AT91_PMC_PDIV_1)
81 /* PCK/4 = MCK Master Clock from PLLA */
82 #define CONFIG_SYS_MCKR2_VAL \
83 (AT91_PMC_CSS_PLLA | \
84 AT91_PMC_PRES_1 | \
85 AT91RM9200_PMC_MDIV_3 | \
86 AT91_PMC_PDIV_1)
87 #endif
88 /* define PDC[31:16] as DATA[31:16] */
89 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
90 /* no pull-up for D[31:16] */
91 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
92 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
93 #define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
94 (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \
95 AT91_MATRIX_EBI0_CS1A_SDRAMC)
96
97 /* SDRAM */
98 /* SDRAMC_MR Mode register */
99 #define CONFIG_SYS_SDRC_MR_VAL1 0
100 /* SDRAMC_TR - Refresh Timer register */
101 #define CONFIG_SYS_SDRC_TR_VAL1 0x3AA
102 /* SDRAMC_CR - Configuration register*/
103 #define CONFIG_SYS_SDRC_CR_VAL \
104 (AT91_SDRAMC_NC_9 | \
105 AT91_SDRAMC_NR_13 | \
106 AT91_SDRAMC_NB_4 | \
107 AT91_SDRAMC_CAS_2 | \
108 AT91_SDRAMC_DBW_32 | \
109 (2 << 8) | /* tWR - Write Recovery Delay */ \
110 (7 << 12) | /* tRC - Row Cycle Delay */ \
111 (2 << 16) | /* tRP - Row Precharge Delay */ \
112 (2 << 20) | /* tRCD - Row to Column Delay */ \
113 (5 << 24) | /* tRAS - Active to Precharge Delay */ \
114 (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */
115
116 /* Memory Device Register -> SDRAM */
117 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
118 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
119 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
120 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
121 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
122 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
123 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
124 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
125 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
126 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
127 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
128 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
129 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
130 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
131 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
132 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
133 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
134 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
135
136 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
137 #define CONFIG_SYS_SMC0_SETUP0_VAL \
138 (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
139 AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
140 #define CONFIG_SYS_SMC0_PULSE0_VAL \
141 (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
142 AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
143 #define CONFIG_SYS_SMC0_CYCLE0_VAL \
144 (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
145 #define CONFIG_SYS_SMC0_MODE0_VAL \
146 (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
147 AT91_SMC_DBW_16 | \
148 AT91_SMC_TDFMODE | \
149 AT91_SMC_TDF_(6))
150
151 /* user reset enable */
152 #define CONFIG_SYS_RSTC_RMR_VAL \
153 (AT91_RSTC_KEY | \
154 AT91_RSTC_PROCRST | \
155 AT91_RSTC_RSTTYP_WAKEUP | \
156 AT91_RSTC_RSTTYP_WATCHDOG)
157
158 /* Disable Watchdog */
159 #define CONFIG_SYS_WDTC_WDMR_VAL \
160 (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
161 AT91_WDT_WDV | \
162 AT91_WDT_WDDIS | \
163 AT91_WDT_WDD)
164
165 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
166 #define CONFIG_SETUP_MEMORY_TAGS 1
167 #define CONFIG_INITRD_TAG 1
168
169 #undef CONFIG_SKIP_LOWLEVEL_INIT
170 #undef CONFIG_SKIP_RELOCATE_UBOOT
171 #define CONFIG_USER_LOWLEVEL_INIT 1
172
173 /*
174 * Hardware drivers
175 */
176 #define CONFIG_AT91_GPIO 1
177 #define CONFIG_ATMEL_USART 1
178 #undef CONFIG_USART0
179 #undef CONFIG_USART1
180 #undef CONFIG_USART2
181 #define CONFIG_USART3 1 /* USART 3 is DBGU */
182
183 /* LCD */
184 #define CONFIG_LCD 1
185 #define LCD_BPP LCD_COLOR8
186 #define CONFIG_LCD_LOGO 1
187 #undef LCD_TEST_PATTERN
188 #define CONFIG_LCD_INFO 1
189 #define CONFIG_LCD_INFO_BELOW_LOGO 1
190 #define CONFIG_SYS_WHITE_ON_BLACK 1
191 #define CONFIG_ATMEL_LCD 1
192 #define CONFIG_ATMEL_LCD_BGR555 1
193 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
194
195 #define CONFIG_LCD_IN_PSRAM 1
196
197 /* LED */
198 #define CONFIG_AT91_LED
199 #define CONFIG_RED_LED AT91_PIN_PB7 /* this is the power led */
200 #define CONFIG_GREEN_LED AT91_PIN_PB8 /* this is the user1 led */
201
202 #define CONFIG_BOOTDELAY 3
203
204 /*
205 * BOOTP options
206 */
207 #define CONFIG_BOOTP_BOOTFILESIZE 1
208 #define CONFIG_BOOTP_BOOTPATH 1
209 #define CONFIG_BOOTP_GATEWAY 1
210 #define CONFIG_BOOTP_HOSTNAME 1
211
212 /*
213 * Command line configuration.
214 */
215 #include <config_cmd_default.h>
216 #undef CONFIG_CMD_BDI
217 #undef CONFIG_CMD_IMI
218 #undef CONFIG_CMD_FPGA
219 #undef CONFIG_CMD_LOADS
220 #undef CONFIG_CMD_IMLS
221
222 #define CONFIG_CMD_PING 1
223 #define CONFIG_CMD_DHCP 1
224 #define CONFIG_CMD_NAND 1
225 #define CONFIG_CMD_USB 1
226
227 /* SDRAM */
228 #define CONFIG_NR_DRAM_BANKS 1
229 #define PHYS_SDRAM 0x20000000
230 #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
231
232 /* DataFlash */
233 #define CONFIG_ATMEL_DATAFLASH_SPI
234 #define CONFIG_HAS_DATAFLASH 1
235 #define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
236 #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
237 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
238 #define AT91_SPI_CLK 15000000
239 #define DATAFLASH_TCSS (0x1a << 16)
240 #define DATAFLASH_TCHS (0x1 << 24)
241
242 /* NOR flash, if populated */
243 #define CONFIG_SYS_FLASH_CFI 1
244 #define CONFIG_FLASH_CFI_DRIVER 1
245 #define PHYS_FLASH_1 0x10000000
246 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
247 #define CONFIG_SYS_MAX_FLASH_SECT 256
248 #define CONFIG_SYS_MAX_FLASH_BANKS 1
249
250 /* NAND flash */
251 #ifdef CONFIG_CMD_NAND
252 #define CONFIG_NAND_ATMEL
253 #define CONFIG_SYS_NAND_MAX_CHIPS 1
254 #define CONFIG_SYS_MAX_NAND_DEVICE 1
255 #define CONFIG_SYS_NAND_BASE 0x40000000
256 #define CONFIG_SYS_NAND_DBW_8 1
257 /* our ALE is AD21 */
258 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
259 /* our CLE is AD22 */
260 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
261 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
262 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PB30
263
264 #endif
265
266 #define CONFIG_CMD_JFFS2 1
267 #define CONFIG_JFFS2_CMDLINE 1
268 #define CONFIG_JFFS2_NAND 1
269 #define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */
270 #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
271 #define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/
272
273 /* PSRAM */
274 #define PHYS_PSRAM 0x70000000
275 #define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */
276
277 /* Ethernet */
278 #define CONFIG_MACB 1
279 #define CONFIG_RMII 1
280 #define CONFIG_NET_MULTI 1
281 #define CONFIG_NET_RETRY_COUNT 20
282 #define CONFIG_RESET_PHY_R 1
283
284 /* USB */
285 #define CONFIG_USB_ATMEL
286 #define CONFIG_USB_OHCI_NEW 1
287 #define CONFIG_DOS_PARTITION 1
288 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
289 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
290 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
291 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
292 #define CONFIG_USB_STORAGE 1
293
294 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
295
296 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
297 #define CONFIG_SYS_MEMTEST_END 0x23e00000
298
299 #define CONFIG_SYS_USE_FLASH 1
300 #undef CONFIG_SYS_USE_DATAFLASH
301 #undef CONFIG_SYS_USE_NANDFLASH
302
303 #ifdef CONFIG_SYS_USE_DATAFLASH
304
305 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
306 #define CONFIG_ENV_IS_IN_DATAFLASH
307 #define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
308 #define CONFIG_ENV_OFFSET 0x4200
309 #define CONFIG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
310 #define CONFIG_ENV_SIZE 0x4200
311 #define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
312 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \
313 "root=/dev/mtdblock0 " \
314 "mtdparts=atmel_nand:-(root) "\
315 "rw rootfstype=jffs2"
316
317 #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */
318
319 /* bootstrap + u-boot + env + linux in nandflash */
320 #define CONFIG_ENV_IS_IN_NAND
321 #define CONFIG_ENV_OFFSET 0x60000
322 #define CONFIG_ENV_OFFSET_REDUND 0x80000
323 #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
324 #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
325 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \
326 "root=/dev/mtdblock5 " \
327 "mtdparts=atmel_nand:" \
328 "128k(bootstrap)ro," \
329 "256k(uboot)ro," \
330 "128k(env1)ro," \
331 "128k(env2)ro," \
332 "2M(linux)," \
333 "-(root) " \
334 "rw rootfstype=jffs2"
335
336 #elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */
337
338 #define CONFIG_ENV_IS_IN_FLASH 1
339 #define CONFIG_ENV_OFFSET 0x40000
340 #define CONFIG_ENV_SECT_SIZE 0x10000
341 #define CONFIG_ENV_SIZE 0x10000
342 #define CONFIG_ENV_OVERWRITE 1
343
344 /* JFFS Partition offset set */
345 #define CONFIG_SYS_JFFS2_FIRST_BANK 0
346 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
347
348 /* 512k reserved for u-boot */
349 #define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
350
351 #define CONFIG_BOOTCOMMAND "run flashboot"
352 #define CONFIG_ROOTPATH /ronetix/rootfs
353 #define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
354
355 #define CONFIG_CON_ROT "fbcon=rotate:3 "
356 #define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 "\
357 CONFIG_CON_ROT
358
359 #define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand"
360 #define MTDPARTS_DEFAULT \
361 "mtdparts=physmap-flash.0:" \
362 "256k(u-boot)ro," \
363 "64k(u-boot-env)ro," \
364 "1408k(kernel)," \
365 "-(rootfs);" \
366 "nand:-(nand)"
367
368 #define CONFIG_EXTRA_ENV_SETTINGS \
369 "mtdids=" MTDIDS_DEFAULT "\0" \
370 "mtdparts=" MTDPARTS_DEFAULT "\0" \
371 "partition=nand0,0\0" \
372 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
373 "nfsargs=setenv bootargs root=/dev/nfs rw " \
374 CONFIG_CON_ROT \
375 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
376 "addip=setenv bootargs $(bootargs) " \
377 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
378 ":$(hostname):eth0:off\0" \
379 "ramboot=tftpboot 0x22000000 vmImage;" \
380 "run ramargs;run addip;bootm 22000000\0" \
381 "nfsboot=tftpboot 0x22000000 vmImage;" \
382 "run nfsargs;run addip;bootm 22000000\0" \
383 "flashboot=run ramargs;run addip;bootm 0x10050000\0" \
384 ""
385
386 #else
387 #error "Undefined memory device"
388 #endif
389
390 #define CONFIG_BAUDRATE 115200
391 #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
392
393 #define CONFIG_SYS_PROMPT "u-boot-pm9263> "
394 #define CONFIG_SYS_CBSIZE 256
395 #define CONFIG_SYS_MAXARGS 16
396 #define CONFIG_SYS_PBSIZE \
397 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
398 #define CONFIG_SYS_LONGHELP 1
399 #define CONFIG_CMDLINE_EDITING 1
400
401 /*
402 * Size of malloc() pool
403 */
404 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
405 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
406
407 #define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
408
409 #ifdef CONFIG_USE_IRQ
410 #error CONFIG_USE_IRQ not supported
411 #endif
412
413 #endif
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