include/configs/pm9g45.h

   1 /*
   2  * (C) Copyright 2010
   3  * Ilko Iliev <iliev@ronetix.at>
   4  * Asen Dimov <dimov@ronetix.at>
   5  * Ronetix GmbH <www.ronetix.at>
   6  *
   7  * (C) Copyright 2007-2008
   8  * Stelian Pop <stelian@popies.net>
   9  * Lead Tech Design <www.leadtechdesign.com>
  10  *
  11  * Configuation settings for the PM9G45 board.
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /*
  20  * SoC must be defined first, before hardware.h is included.
  21  * In this case SoC is defined in boards.cfg.
  22  */
  23 #include <asm/hardware.h>
  24
  25 #define CONFIG_PM9G45           1       /* It's an Ronetix PM9G45 */
  26 #define CONFIG_SYS_AT91_CPU_NAME        "AT91SAM9G45"
  27
  28 #define CONFIG_MACH_TYPE        MACH_TYPE_PM9G45
  29
  30 /* ARM asynchronous clock */
  31 #define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
  32 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768           /* slow clock xtal */
  33
  34 #define CONFIG_ARCH_CPU_INIT
  35
  36 #define CONFIG_CMDLINE_TAG      1       /* enable passing of ATAGs */
  37 #define CONFIG_SETUP_MEMORY_TAGS 1
  38 #define CONFIG_INITRD_TAG       1
  39
  40 #define CONFIG_SKIP_LOWLEVEL_INIT
  41
  42 /*
  43  * Hardware drivers
  44  */
  45 #define CONFIG_AT91_GPIO        1
  46 #define CONFIG_ATMEL_USART      1
  47 #define CONFIG_USART_BASE               ATMEL_BASE_DBGU
  48 #define CONFIG_USART_ID                 ATMEL_ID_SYS
  49
  50 #define CONFIG_SYS_USE_NANDFLASH        1
  51
  52 /* LED */
  53 #define CONFIG_AT91_LED
  54 #define CONFIG_RED_LED          GPIO_PIN_PD(31) /* this is the user1 led */
  55 #define CONFIG_GREEN_LED        GPIO_PIN_PD(0)  /* this is the user2 led */
  56
  57
  58 /*
  59  * BOOTP options
  60  */
  61 #define CONFIG_BOOTP_BOOTFILESIZE       1
  62
  63 #define CONFIG_JFFS2_CMDLINE            1
  64 #define CONFIG_JFFS2_NAND               1
  65 #define CONFIG_JFFS2_DEV                "nand0" /* NAND dev jffs2 lives on */
  66 #define CONFIG_JFFS2_PART_OFFSET        0       /* start of jffs2 partition */
  67 #define CONFIG_JFFS2_PART_SIZE          (256 * 1024 * 1024) /* partition */
  68
  69 /* SDRAM */
  70 #define CONFIG_NR_DRAM_BANKS            1
  71 #define PHYS_SDRAM                      0x70000000
  72 #define PHYS_SDRAM_SIZE                 0x08000000      /* 128 megs */
  73
  74 /* NAND flash */
  75 #ifdef CONFIG_CMD_NAND
  76 #define CONFIG_NAND_ATMEL
  77 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  78 #define CONFIG_SYS_NAND_BASE            0x40000000
  79 #define CONFIG_SYS_NAND_DBW_8           1
  80 /* our ALE is AD21 */
  81 #define CONFIG_SYS_NAND_MASK_ALE        (1 << 21)
  82 /* our CLE is AD22 */
  83 #define CONFIG_SYS_NAND_MASK_CLE        (1 << 22)
  84 #define CONFIG_SYS_NAND_ENABLE_PIN      GPIO_PIN_PC(14)
  85 #define CONFIG_SYS_NAND_READY_PIN       GPIO_PIN_PD(3)
  86
  87 #endif
  88
  89 /* Ethernet */
  90 #define CONFIG_MACB                     1
  91 #define CONFIG_RMII                     1
  92 #define CONFIG_NET_RETRY_COUNT          20
  93 #define CONFIG_RESET_PHY_R              1
  94
  95 /* USB */
  96 #define CONFIG_USB_ATMEL
  97 #define CONFIG_USB_ATMEL_CLK_SEL_UPLL
  98 #define CONFIG_USB_OHCI_NEW             1
  99 #define CONFIG_SYS_USB_OHCI_CPU_INIT    1
 100 #define CONFIG_SYS_USB_OHCI_REGS_BASE   0x00700000 /* _UHP_OHCI_BASE */
 101 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "at91sam9g45"
 102 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
 103
 104 /* board specific(not enough SRAM) */
 105 #define CONFIG_AT91SAM9G45_LCD_BASE     PHYS_SDRAM + 0xE00000
 106
 107 #define CONFIG_SYS_LOAD_ADDR            PHYS_SDRAM + 0x2000000 /* load addr */
 108
 109 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM
 110 #define CONFIG_SYS_MEMTEST_END          CONFIG_AT91SAM9G45_LCD_BASE
 111
 112 /* bootstrap + u-boot + env + linux in nandflash */
 113 #define CONFIG_ENV_OFFSET               0x60000
 114 #define CONFIG_ENV_OFFSET_REDUND        0x80000
 115 #define CONFIG_ENV_SIZE                 0x20000         /* 1 sector = 128 kB */
 116 #define CONFIG_BOOTCOMMAND      "nand read 0x72000000 0x200000 0x200000; bootm"
 117
 118 /*
 119  * Size of malloc() pool
 120  */
 121 #define CONFIG_SYS_MALLOC_LEN           ROUND(3 * CONFIG_ENV_SIZE + 128*1024,\
 122                                         0x1000)
 123
 124 #define CONFIG_SYS_SDRAM_BASE   PHYS_SDRAM
 125 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
 126                                 GENERATED_GBL_DATA_SIZE)
 127
 128 #endif