include/configs/ppmc7xx.h

   1 /*
   2  * ppmc7xx.h
   3  * ---------
   4  *
   5  * Wind River PPMC 7xx/74xx board configuration file.
   6  *
   7  * By Richard Danter (richard.danter@windriver.com)
   8  * Copyright (C) 2005 Wind River Systems
   9  */
  10
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 #define CONFIG_PPMC7XX
  16
  17
  18 /*===================================================================
  19  *
  20  * User configurable settings - Modify to your preference
  21  *
  22  *===================================================================
  23  */
  24
  25 /*
  26  * Debug
  27  *
  28  * DEBUG                        - Define this is you want extra debug info
  29  * GTREGREAD                    - Required to build with debug
  30  * do_bdinfo                    - Required to build with debug
  31  */
  32
  33 #undef  DEBUG
  34 #define GTREGREAD(x)                    0xFFFFFFFF
  35 #define do_bdinfo(a,b,c,d)
  36
  37
  38 /*
  39  * CPU type
  40  *
  41  * CONFIG_7xx                   - We have a 750 or 755 CPU
  42  * CONFIG_74xx                  - We have a 7400 CPU
  43  * CONFIG_ALTIVEC               - We have altivec enabled CPU (only 7400)
  44  * CONFIG_BUS_CLK               - System bus clock in Hz
  45  */
  46
  47 #define CONFIG_7xx
  48 #undef  CONFIG_74xx
  49 #undef  CONFIG_ALTIVEC
  50 #define CONFIG_BUS_CLK                  66000000
  51
  52
  53 /*
  54  * Monitor configuration
  55  *
  56  * List of command sets to include in shell
  57  *
  58  * The following command sets have been tested and known to work:
  59  *
  60  * CMD_CACHE            - Cache control commands
  61  * CMD_MEMORY           - Memory display, change and test commands
  62  * CMD_FLASH            - Erase and program flash
  63  * CMD_ENV              - Environment commands
  64  * CMD_RUN              - Run commands stored in env vars
  65  * CMD_ELF              - Load ELF files
  66  * CMD_NET              - Networking/file download commands
  67  * CMD_PIN              - ICMP Echo Request command
  68  * CMD_PCI              - PCI Bus scanning command
  69  */
  70
  71 /*
  72  * Command line configuration.
  73  */
  74 #include <config_cmd_default.h>
  75
  76 #define CONFIG_CMD_FLASH
  77 #define CONFIG_CMD_ENV
  78 #define CONFIG_CMD_RUN
  79 #define CONFIG_CMD_ELF
  80 #define CONFIG_CMD_NET
  81 #define CONFIG_CMD_PING
  82 #define CONFIG_CMD_PCI
  83
  84 #undef CONFIG_CMD_KGDB
  85
  86
  87 /*
  88  * Serial configuration
  89  *
  90  * CONFIG_CONS_INDEX            - Serial console port number (COM1)
  91  * CONFIG_BAUDRATE                      - Serial speed
  92  */
  93
  94 #define CONFIG_CONS_INDEX               1
  95 #define CONFIG_BAUDRATE                 9600
  96
  97
  98 /*
  99  * PCI config
 100  *
 101  * CONFIG_PCI                           - Enable PCI bus
 102  * CONFIG_PCI_PNP                       - Enable Plug & Play support
 103  * CONFIG_PCI_SCAN_SHOW         - Enable display of devices at startup
 104  */
 105
 106 #define CONFIG_PCI
 107 #define CONFIG_PCI_PNP
 108 #undef  CONFIG_PCI_SCAN_SHOW
 109
 110
 111 /*
 112  * Network config
 113  *
 114  * CONFIG_NET_MULTI                     - Support for multiple network interfaces
 115  * CONFIG_EEPRO100                      - Intel 8255x Ethernet Controller
 116  * CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM
 117  */
 118
 119 #define CONFIG_NET_MULTI
 120 #define CONFIG_EEPRO100
 121 #define CONFIG_EEPRO100_SROM_WRITE
 122
 123
 124 /*
 125  * Enable extra init functions
 126  *
 127  * CONFIG_MISC_INIT_F           - Call pre-relocation init functions
 128  * CONFIG_MISC_INIT_R           - Call post relocation init functions
 129  */
 130
 131 #undef  CONFIG_MISC_INIT_F
 132 #define CONFIG_MISC_INIT_R
 133
 134
 135 /*
 136  * Boot config
 137  *
 138  * CONFIG_BOOTCOMMAND           - Command(s) to execute to auto-boot
 139  * CONFIG_BOOTDELAY                     - How long to wait before auto-boot (in sec)
 140  */
 141
 142 #define CONFIG_BOOTCOMMAND              \
 143         "bootp;" \
 144         "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
 145         "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
 146         "bootm"
 147 #define CONFIG_BOOTDELAY                5
 148
 149
 150 /*===================================================================
 151  *
 152  * Board configuration settings - You should not need to modify these
 153  *
 154  *===================================================================
 155  */
 156
 157
 158 /*
 159  * Memory map
 160  *
 161  * This board runs in a standard CHRP (Map-B) configuration.
 162  *
 163  *      Type            Start           End                     Size    Width   Chip Sel
 164  *      ----------- ----------- ----------- ------- ------- --------
 165  *      SDRAM           0x00000000      0x04000000      64MB    64b             SDRAMCS0
 166  *      User LED's      0x78000000                                              RCS3
 167  *      UART            0x7C000000                                              RCS2
 168  *      Mailbox         0xFF000000                                              RCS1
 169  *      Flash           0xFFC00000      0xFFFFFFFF      4MB     64b             RCS0
 170  *
 171  * Flash sectors are laid out as follows.
 172  *
 173  *      Sector  Start           End                     Size    Comments
 174  *      ------- ----------- ----------- ------- -----------
 175  *       0              0xFFC00000      0xFFC3FFFF      256KB
 176  *   1          0xFFC40000      0xFFC7FFFF      256KB
 177  *       2              0xFFC80000      0xFFCBFFFF      256KB
 178  *       3              0xFFCC0000      0xFFCFFFFF      256KB
 179  *       4              0xFFD00000      0xFFD3FFFF      256KB
 180  *       5              0xFFD40000      0xFFD7FFFF      256KB
 181  *       6              0xFFD80000      0xFFDBFFFF      256KB
 182  *       7              0xFFDC0000      0xFFDFFFFF      256KB
 183  *   8          0xFFE00000      0xFFE3FFFF      256KB
 184  *       9              0xFFE40000      0xFFE7FFFF      256KB
 185  *  10          0xFFE80000      0xFFEBFFFF      256KB
 186  *  11          0xFFEC0000      0xFFEFFFFF      256KB
 187  *  12          0xFFF00000      0xFFF3FFFF      256KB   U-Boot code here
 188  *  13          0xFFF40000      0xFFF7FFFF      256KB
 189  *  14          0xFFF80000      0xFFFBFFFF      256KB
 190  *  15          0xFFFC0000      0xFFFDFFFF      128KB
 191  *  16          0xFFFE0000      0xFFFE7FFF       32KB   U-Boot env vars here
 192  *  17          0xFFFE8000      0xFFFEFFFF       32KB   U-Boot backup copy of env vars here
 193  *  18          0xFFFF0000      0xFFFFFFFF       64KB
 194  */
 195
 196
 197 /*
 198  * SDRAM config - see memory map details above.
 199  *
 200  * CFG_SDRAM_BASE                       - Start address of SDRAM, this _must_ be zero!
 201  * CFG_SDRAM_SIZE                       - Total size of contiguous SDRAM bank(s)
 202  */
 203
 204 #define CFG_SDRAM_BASE                  0x00000000
 205 #define CFG_SDRAM_SIZE                  0x04000000
 206
 207
 208 /*
 209  * Flash config - see memory map details above.
 210  *
 211  * CFG_FLASH_BASE                       - Start address of flash memory
 212  * CFG_FLASH_SIZE                       - Total size of contiguous flash mem
 213  * CFG_FLASH_ERASE_TOUT         - Erase timeout in ms
 214  * CFG_FLASH_WRITE_TOUT         - Write timeout in ms
 215  * CFG_MAX_FLASH_BANKS          - Number of banks of flash on board
 216  * CFG_MAX_FLASH_SECT           - Number of sectors in a bank
 217  */
 218
 219 #define CFG_FLASH_BASE                  0xFFC00000
 220 #define CFG_FLASH_SIZE                  0x00400000
 221 #define CFG_FLASH_ERASE_TOUT    250000
 222 #define CFG_FLASH_WRITE_TOUT    5000
 223 #define CFG_MAX_FLASH_BANKS             1
 224 #define CFG_MAX_FLASH_SECT              19
 225
 226
 227 /*
 228  * Monitor config - see memory map details above
 229  *
 230  * CFG_MONITOR_BASE                     - Base address of monitor code
 231  * CFG_MALLOC_LEN                       - Size of malloc pool (128KB)
 232  */
 233
 234 #define CFG_MONITOR_BASE                TEXT_BASE
 235 #define CFG_MALLOC_LEN                  0x20000
 236
 237
 238 /*
 239  * Command shell settings
 240  *
 241  * CFG_BARGSIZE                 - Boot Argument buffer size
 242  * CFG_BOOTMAPSZ                - Size of app's mapped RAM at boot (Linux=8MB)
 243  * CFG_CBSIZE                   - Console Buffer (input) size
 244  * CFG_LOAD_ADDR                - Default load address
 245  * CFG_LONGHELP                 - Provide more detailed help
 246  * CFG_MAXARGS                  - Number of args accepted by monitor commands
 247  * CFG_MEMTEST_START            - Start address of test to run on RAM
 248  * CFG_MEMTEST_END              - End address of RAM test
 249  * CFG_PBSIZE                   - Print Buffer (output) size
 250  * CFG_PROMPT                   - Prompt string
 251  */
 252
 253 #define CFG_BARGSIZE                    1024
 254 #define CFG_BOOTMAPSZ                   0x800000
 255 #define CFG_CBSIZE                      1024
 256 #define CFG_LOAD_ADDR                   0x100000
 257 #define CFG_LONGHELP
 258 #define CFG_MAXARGS                     16
 259 #define CFG_MEMTEST_START               0x00040000
 260 #define CFG_MEMTEST_END                 0x00040100
 261 #define CFG_PBSIZE                      1024
 262 #define CFG_PROMPT                      "=> "
 263
 264
 265 /*
 266  * Environment config - see memory map details above
 267  *
 268  * CFG_ENV_IS_IN_FLASH          - The env variables are stored in flash
 269  * CFG_ENV_ADDR                 - Address of the sector containing env vars
 270  * CFG_ENV_SIZE                 - Ammount of RAM for env vars (used to save RAM, 4KB)
 271  * CFG_ENV_SECT_SIZE            - Size of sector containing env vars (32KB)
 272  */
 273
 274 #define CFG_ENV_IS_IN_FLASH             1
 275 #define CFG_ENV_ADDR                    0xFFFE0000
 276 #define CFG_ENV_SIZE                    0x1000
 277 #define CFG_ENV_ADDR_REDUND             0xFFFE8000
 278 #define CFG_ENV_SIZE_REDUND             0x1000
 279 #define CFG_ENV_SECT_SIZE               0x8000
 280
 281
 282 /*
 283  * Initial RAM config
 284  *
 285  * Since the main system RAM is initialised very early, we place the INIT_RAM
 286  * in the main system RAM just above the exception vectors. The contents are
 287  * copied to top of RAM by the init code.
 288  *
 289  * CFG_INIT_RAM_ADDR            - Address of Init RAM, above exception vect
 290  * CFG_INIT_RAM_END                     - Size of Init RAM
 291  * CFG_GBL_DATA_SIZE            - Ammount of RAM to reserve for global data
 292  * CFG_GBL_DATA_OFFSET          - Start of global data, top of stack
 293  */
 294
 295 #define CFG_INIT_RAM_ADDR               (CFG_SDRAM_BASE + 0x4000)
 296 #define CFG_INIT_RAM_END                0x4000
 297 #define CFG_GBL_DATA_SIZE               128
 298 #define CFG_GBL_DATA_OFFSET             (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 299
 300
 301 /*
 302  * Initial BAT config
 303  *
 304  * BAT0 - System SDRAM
 305  * BAT1 - LED's and Serial Port
 306  * BAT2 - PCI Memory
 307  * BAT3 - PCI I/O including Flash Memory
 308  */
 309
 310 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 311 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
 312 #define CFG_DBAT0L CFG_IBAT0L
 313 #define CFG_DBAT0U CFG_IBAT0U
 314
 315 #define CFG_IBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
 316 #define CFG_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 317 #define CFG_DBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 318 #define CFG_DBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 319
 320 #define CFG_IBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
 321 #define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 322 #define CFG_DBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 323 #define CFG_DBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 324
 325 #define CFG_IBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
 326 #define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 327 #define CFG_DBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 328 #define CFG_DBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 329
 330
 331 /*
 332  * Cache config
 333  *
 334  * CFG_CACHELINE_SIZE           - Size of a cache line (CPU specific)
 335  * CFG_L2                                       - L2 cache enabled if defined
 336  * L2_INIT                                      - L2 cache init flags
 337  * L2_ENABLE                            - L2 cache enable flags
 338  */
 339
 340 #define CFG_CACHELINE_SIZE              32
 341 #undef  CFG_L2
 342 #define L2_INIT                                 0
 343 #define L2_ENABLE                               0
 344
 345
 346 /*
 347  * Clocks config
 348  *
 349  * CFG_BUS_HZ                           - Bus clock frequency in Hz
 350  * CFG_BUS_CLK                          - As above (?)
 351  * CFG_HZ                                       - Decrementer freq in Hz
 352  */
 353
 354 #define CFG_BUS_HZ                              CONFIG_BUS_CLK
 355 #define CFG_BUS_CLK                             CONFIG_BUS_CLK
 356 #define CFG_HZ                                  1000
 357
 358
 359 /*
 360  * Serial port config
 361  *
 362  * CFG_BAUDRATE_TABLE           - List of valid baud rates
 363  * CFG_NS16550                          - Include the NS16550 driver
 364  * CFG_NS16550_SERIAL           - Include the serial (wrapper) driver
 365  * CFG_NS16550_CLK                      - Frequency of reference clock
 366  * CFG_NS16550_REG_SIZE         - 64-bit accesses to 8-bit port
 367  * CFG_NS16550_COM1                     - Base address of 1st serial port
 368  */
 369
 370 #define CFG_BAUDRATE_TABLE              { 9600, 19200, 38400, 57600, 115200 }
 371 #define CFG_NS16550
 372 #define CFG_NS16550_SERIAL
 373 #define CFG_NS16550_CLK                 3686400
 374 #define CFG_NS16550_REG_SIZE    -8
 375 #define CFG_NS16550_COM1                0x7C000000
 376
 377
 378 /*
 379  * PCI Config - Address Map B (CHRP)
 380  */
 381
 382 #define CFG_PCI_MEMORY_BUS      0x00000000
 383 #define CFG_PCI_MEMORY_PHYS     0x00000000
 384 #define CFG_PCI_MEMORY_SIZE     0x40000000
 385 #define CFG_PCI_MEM_BUS         0x80000000
 386 #define CFG_PCI_MEM_PHYS        0x80000000
 387 #define CFG_PCI_MEM_SIZE        0x7D000000
 388 #define CFG_ISA_MEM_BUS         0x00000000
 389 #define CFG_ISA_MEM_PHYS        0xFD000000
 390 #define CFG_ISA_MEM_SIZE        0x01000000
 391 #define CFG_PCI_IO_BUS          0x00800000
 392 #define CFG_PCI_IO_PHYS         0xFE800000
 393 #define CFG_PCI_IO_SIZE         0x00400000
 394 #define CFG_ISA_IO_BUS          0x00000000
 395 #define CFG_ISA_IO_PHYS         0xFE000000
 396 #define CFG_ISA_IO_SIZE         0x00800000
 397 #define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS
 398 #define CFG_ISA_IO              CFG_ISA_IO_PHYS
 399 #define CFG_60X_PCI_IO_OFFSET   CFG_ISA_IO_PHYS
 400
 401
 402 /*
 403  * Extra init functions
 404  *
 405  * CFG_BOARD_ASM_INIT           - Call assembly init code
 406  */
 407
 408 #define CFG_BOARD_ASM_INIT
 409
 410
 411 /*
 412  * Boot flags
 413  *
 414  * BOOTFLAG_COLD                        - Indicates a power-on boot
 415  * BOOTFLAG_WARM                        - Indicates a software reset
 416  */
 417
 418 #define BOOTFLAG_COLD                   0x01
 419 #define BOOTFLAG_WARM                   0x02
 420
 421
 422 #endif /* __CONFIG_H */