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1 /*
2 * Copyright 2011-2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 /*
8 * Corenet DS style board configuration file
9 */
10 #ifndef __QEMU_PPCE500_H
11 #define __QEMU_PPCE500_H
12
13 #define CONFIG_CMD_REGINFO
14
15 /* High Level Configuration Options */
16 #define CONFIG_BOOKE
17 #define CONFIG_E500 /* BOOKE e500 family */
18 #define CONFIG_QEMU_E500
19
20 #undef CONFIG_SYS_TEXT_BASE
21 #define CONFIG_SYS_TEXT_BASE 0xf01000 /* 15 MB */
22
23 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
24
25 #define CONFIG_SYS_RAMBOOT
26
27 #define CONFIG_PCI1 1 /* PCI controller 1 */
28 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
29 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
30
31 #define CONFIG_ENV_OVERWRITE
32
33 #define CONFIG_ENABLE_36BIT_PHYS
34
35 #define CONFIG_ADDR_MAP
36 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
37
38 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
39 #define CONFIG_SYS_MEMTEST_END 0x00400000
40 #define CONFIG_SYS_ALT_MEMTEST
41 #define CONFIG_PANIC_HANG /* do not reset board on panic */
42
43 /* Needed to fill the ccsrbar pointer */
44 #define CONFIG_BOARD_EARLY_INIT_F
45
46 /* Virtual address to CCSRBAR */
47 #define CONFIG_SYS_CCSRBAR 0xe0000000
48 /* Physical address should be a function call */
49 #ifndef __ASSEMBLY__
50 extern unsigned long long get_phys_ccsrbar_addr_early(void);
51 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH (get_phys_ccsrbar_addr_early() >> 32)
52 #define CONFIG_SYS_CCSRBAR_PHYS_LOW get_phys_ccsrbar_addr_early()
53 #else
54 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
55 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
56 #endif
57
58 /* Virtual address range for PCI region maps */
59 #define CONFIG_SYS_PCI_MAP_START 0x80000000
60 #define CONFIG_SYS_PCI_MAP_END 0xe8000000
61
62 /* Virtual address to a temporary map if we need it (max 128MB) */
63 #define CONFIG_SYS_TMPVIRT 0xe8000000
64
65 /*
66 * DDR Setup
67 */
68 #define CONFIG_VERY_BIG_RAM
69 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
70 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
71
72 #define CONFIG_CHIP_SELECTS_PER_CTRL 0
73
74 #define CONFIG_SYS_CLK_FREQ 33000000
75
76 #define CONFIG_SYS_NO_FLASH
77
78 #define CONFIG_SYS_BOOT_BLOCK 0x00000000 /* boot TLB */
79
80 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
81
82 #define CONFIG_ENV_IS_NOWHERE
83
84 #define CONFIG_HWCONFIG
85
86 #define CONFIG_SYS_INIT_RAM_ADDR 0x00100000
87 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0x0
88 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0x00100000
89 /* The assembler doesn't like typecast */
90 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
91 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
92 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
93 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
94
95 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
96 GENERATED_GBL_DATA_SIZE)
97 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
98
99 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
100 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
101
102 #define CONFIG_CONS_INDEX 1
103 #define CONFIG_SYS_NS16550_SERIAL
104 #define CONFIG_SYS_NS16550_REG_SIZE 1
105 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
106
107 #define CONFIG_SYS_BAUDRATE_TABLE \
108 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
109
110 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
111 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
112
113 /*
114 * General PCI
115 * Memory space is mapped 1-1, but I/O space must start from 0.
116 */
117
118 #ifdef CONFIG_PCI
119 #define CONFIG_PCI_INDIRECT_BRIDGE
120 #define CONFIG_PCI_PNP /* do pci plug-and-play */
121
122 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
123 #define CONFIG_DOS_PARTITION
124 #endif /* CONFIG_PCI */
125
126 #define CONFIG_LBA48
127 #define CONFIG_DOS_PARTITION
128
129 /*
130 * Environment
131 */
132 #define CONFIG_ENV_SIZE 0x2000
133
134 #define CONFIG_LOADS_ECHO /* echo on for serial download */
135
136 #define CONFIG_LAST_STAGE_INIT
137
138 /*
139 * Command line configuration.
140 */
141 #define CONFIG_CMD_IRQ
142
143 #ifdef CONFIG_PCI
144 #define CONFIG_CMD_PCI
145 #endif
146
147 /*
148 * Miscellaneous configurable options
149 */
150 #define CONFIG_SYS_LONGHELP /* undef to save memory */
151 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
152 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
153 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
154 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
155 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
156 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
157 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
158
159 /*
160 * For booting Linux, the board info and command line data
161 * have to be in the first 64 MB of memory, since this is
162 * the maximum mapped by the Linux kernel during initialization.
163 */
164 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
165 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
166
167 /*
168 * Environment Configuration
169 */
170 #define CONFIG_ROOTPATH "/opt/nfsroot"
171 #define CONFIG_BOOTFILE "uImage"
172 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
173
174 /* default location for tftp and bootm */
175 #define CONFIG_LOADADDR 1000000
176
177 #define CONFIG_BAUDRATE 115200
178
179 #define CONFIG_BOOTCOMMAND \
180 "test -n \"$qemu_kernel_addr\" && bootm $qemu_kernel_addr - $fdt_addr_r\0"
181
182 #endif /* __QEMU_PPCE500_H */