include/configs/quantum.h

   1 /*
   2  * (C) Copyright 2003-2010
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  * changes for 16M board
  27  */
  28
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 /*
  33  * High Level Configuration Options
  34  * (easy to change)
  35  */
  36
  37 #undef CONFIG_MPC860
  38 #define CONFIG_MPC850           1       /* This is a MPC850 CPU         */
  39 #define CONFIG_RPXLITE          1       /* QUANTUM is the RPXlite clone */
  40 #define CONFIG_RMU              1   /* The QUNATUM is based on our RMU */
  41
  42 #define CONFIG_SYS_TEXT_BASE    0xfff00000
  43
  44 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  45 #undef  CONFIG_8xx_CONS_SMC2
  46 #undef  CONFIG_8xx_CONS_NONE
  47 #define CONFIG_BAUDRATE         9600    /* console baudrate = 9600bps   */
  48 #if 0
  49 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  50 #else
  51 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  52 #endif
  53
  54 /* default developmenmt environment */
  55
  56 #define CONFIG_ETHADDR 00:0B:17:00:00:00
  57
  58 #define CONFIG_IPADDR  10.10.69.10
  59 #define CONFIG_SERVERIP 10.10.69.49
  60 #define CONFIG_NETMASK  255.255.255.0
  61 #define CONFIG_HOSTNAME QUANTUM
  62 #define CONFIG_ROOTPATH /opt/eldk/pcc_8xx
  63
  64 #define CONFIG_BOOTARGS  "root=/dev/ram rw"
  65
  66 #define CONFIG_BOOTCOMMAND "bootm ff000000"
  67
  68 #define CONFIG_EXTRA_ENV_SETTINGS \
  69     "serial#=12345\0"           \
  70         "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0"    \
  71         "ramargs=setenv bootargs root=/dev/ram rw\0" \
  72     "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0"
  73
  74 /*
  75  * Select the more full-featured memory test (Barr embedded systems)
  76  */
  77 #define CONFIG_SYS_ALT_MEMTEST
  78
  79 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  80 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  81
  82
  83 /* M48T02 Paralled access timekeeper with same interface as the M48T35A*/
  84 #define CONFIG_RTC_M48T35A 1
  85
  86 #if 0
  87 #define CONFIG_WATCHDOG 1               /* watchdog enabled             */
  88 #else
  89 #undef CONFIG_WATCHDOG
  90 #endif
  91
  92 /*  NVRAM and RTC */
  93 #define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA000000
  94 #define CONFIG_SYS_NVRAM_SIZE 2048
  95
  96
  97 /*
  98  * Command line configuration.
  99  */
 100 #include <config_cmd_default.h>
 101
 102 #define CONFIG_CMD_DATE
 103 #define CONFIG_CMD_DHCP
 104 #define CONFIG_CMD_NFS
 105 #define CONFIG_CMD_PING
 106 #define CONFIG_CMD_REGINFO
 107 #define CONFIG_CMD_SNTP
 108
 109
 110 /*
 111  * BOOTP options
 112  */
 113 #define CONFIG_BOOTP_SUBNETMASK
 114 #define CONFIG_BOOTP_GATEWAY
 115 #define CONFIG_BOOTP_HOSTNAME
 116 #define CONFIG_BOOTP_BOOTPATH
 117 #define CONFIG_BOOTP_BOOTFILESIZE
 118
 119
 120 #define CONFIG_AUTOBOOT_KEYED   /* Enable password protection */
 121 #define CONFIG_AUTOBOOT_PROMPT          \
 122         "\nEnter password - autoboot in %d sec...\n", bootdelay
 123 #define CONFIG_AUTOBOOT_DELAY_STR       "system"
 124 /*
 125  * Miscellaneous configurable options
 126  */
 127 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 128 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 129 #if defined(CONFIG_CMD_KGDB)
 130 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 131 #else
 132 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 133 #endif
 134 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 135 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 136 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 137
 138 #define CONFIG_SYS_MEMTEST_START        0x00040000      /* memtest works on     */
 139 #define CONFIG_SYS_MEMTEST_END          0x01f00000      /* 256K ... 15 MB in DRAM       */
 140
 141 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 142
 143 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 144
 145 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 146
 147 /*
 148  * Low Level Configuration Settings
 149  * (address mappings, register initial values, etc.)
 150  * You should know what you are doing if you make changes here.
 151  */
 152 /*-----------------------------------------------------------------------
 153  * Internal Memory Mapped Register
 154  */
 155 #define CONFIG_SYS_IMMR         0xFA200000
 156
 157 /*-----------------------------------------------------------------------
 158  * Definitions for initial stack pointer and data area (in DPRAM)
 159  */
 160 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 161 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 162 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 163 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 164
 165 /*-----------------------------------------------------------------------
 166  * Start addresses for the final memory configuration
 167  * (Set up by the startup code)
 168  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 169  */
 170 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 171 #define CONFIG_SYS_FLASH_BASE   0xFF000000
 172
 173 #if 1
 174     #define CONFIG_FLASH_CFI_DRIVER
 175 #else
 176     #undef CONFIG_FLASH_CFI_DRIVER
 177 #endif
 178
 179
 180 #ifdef CONFIG_FLASH_CFI_DRIVER
 181     #define CONFIG_SYS_FLASH_CFI 1
 182     #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 183     #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
 184 #endif
 185
 186 /*%%% #define CONFIG_SYS_FLASH_BASE             0xFFF00000 */
 187 #if defined(DEBUG) || defined(CONFIG_CMD_IDE)
 188 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 189 #else
 190 #define CONFIG_SYS_MONITOR_LEN          (128 << 10)     /* Reserve 128 kB for Monitor   */
 191 #endif
 192 #define CONFIG_SYS_MONITOR_BASE 0xFFF00000
 193 /*%%% #define CONFIG_SYS_MONITOR_BASE   CONFIG_SYS_FLASH_BASE */
 194 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 195
 196 /*
 197  * For booting Linux, the board info and command line data
 198  * have to be in the first 8 MB of memory, since this is
 199  * the maximum mapped by the Linux kernel during initialization.
 200  */
 201 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 202
 203 /*-----------------------------------------------------------------------
 204  * FLASH organization
 205  */
 206 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 207 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip */
 208
 209 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 210 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 211
 212 #define CONFIG_ENV_IS_IN_FLASH  1
 213 #define CONFIG_ENV_OFFSET           0x00040000  /*   Offset   of Environment Sector     absolute address 0xfff40000*/
 214 #define CONFIG_ENV_SECT_SIZE    0x40000 /* Total Size of Environment Sector     */
 215 #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
 216 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 217
 218 /* Address and size of Redundant Environment Sector     */
 219 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
 220 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 221
 222 /* FPGA */
 223 #define CONFIG_MISC_INIT_R
 224 #define CONFIG_SYS_FPGA_SPARTAN2
 225 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 226
 227
 228 /*-----------------------------------------------------------------------
 229  * Reset address
 230  */
 231 #define CONFIG_SYS_RESET_ADDRESS        ((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res)))
 232
 233 /*-----------------------------------------------------------------------
 234  * Cache Configuration
 235  */
 236 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 237 #if defined(CONFIG_CMD_KGDB)
 238 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 239 #endif
 240
 241 /*-----------------------------------------------------------------------
 242  * SYPCR - System Protection Control                            11-9
 243  * SYPCR can only be written once after reset!
 244  *-----------------------------------------------------------------------
 245  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 246  */
 247 #if defined(CONFIG_WATCHDOG)
 248 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 249                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 250 #else
 251 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 252 #endif
 253
 254 /*-----------------------------------------------------------------------
 255  * SIUMCR - SIU Module Configuration                            11-6
 256  *-----------------------------------------------------------------------
 257  * PCMCIA config., multi-function pin tri-state
 258  */
 259 #define CONFIG_SYS_SIUMCR       (SIUMCR_MLRC10)
 260
 261 /*-----------------------------------------------------------------------
 262  * TBSCR - Time Base Status and Control                         11-26
 263  *-----------------------------------------------------------------------
 264  * Clear Reference Interrupt Status, Timebase freezing enabled
 265  */
 266 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
 267
 268 /*-----------------------------------------------------------------------
 269  * RTCSC - Real-Time Clock Status and Control Register          11-27
 270  *-----------------------------------------------------------------------
 271  */
 272 /*%%%#define CONFIG_SYS_RTCSC   (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
 273 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_RTE)
 274
 275 /*-----------------------------------------------------------------------
 276  * PISCR - Periodic Interrupt Status and Control                11-31
 277  *-----------------------------------------------------------------------
 278  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 279  */
 280 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
 281
 282 /*-----------------------------------------------------------------------
 283  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 284  *-----------------------------------------------------------------------
 285  * Reset PLL lock status sticky bit, timer expired status bit and timer
 286  * interrupt status bit
 287  *
 288  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 289  */
 290 /* up to 50 MHz we use a 1:1 clock */
 291 #define CONFIG_SYS_PLPRCR       ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
 292
 293 /*-----------------------------------------------------------------------
 294  * SCCR - System Clock and reset Control Register               15-27
 295  *-----------------------------------------------------------------------
 296  * Set clock output, timebase and RTC source and divider,
 297  * power management and some other internal clocks
 298  */
 299 #define SCCR_MASK       SCCR_EBDF00
 300 /* up to 50 MHz we use a 1:1 clock */
 301 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS)
 302
 303 /*-----------------------------------------------------------------------
 304  * PCMCIA stuff
 305  *-----------------------------------------------------------------------
 306  *
 307  */
 308 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 309 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 310 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 311 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 312 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 313 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 314 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 315 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 316
 317 /*-----------------------------------------------------------------------
 318  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 319  *-----------------------------------------------------------------------
 320  */
 321
 322 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 323
 324 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 325 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 326 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 327
 328 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 329 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 330
 331 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 332
 333 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 334
 335 /* Offset for data I/O                  */
 336 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 337
 338 /* Offset for normal register accesses  */
 339 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 340
 341 /* Offset for alternate registers       */
 342 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 343
 344 /*-----------------------------------------------------------------------
 345  *
 346  *-----------------------------------------------------------------------
 347  *
 348  */
 349 /*#define       CONFIG_SYS_DER 0x2002000F*/
 350 #define CONFIG_SYS_DER 0
 351
 352 /*
 353  * Init Memory Controller:
 354  *
 355  * BR0 and OR0 (FLASH)
 356  */
 357
 358 #define FLASH_BASE_PRELIM       0xFE000000      /* FLASH base */
 359 #define CONFIG_SYS_PRELIM_OR_AM 0xFE000000      /* OR addr mask */
 360
 361 /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
 362 #define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
 363
 364 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 365 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
 366
 367 /*
 368  * BR1 and OR1 (SDRAM)
 369  *
 370  */
 371 #define SDRAM_BASE_PRELIM       0x00000000      /* SDRAM base   */
 372 #define SDRAM_MAX_SIZE          0x08000000      /* max 128 MB */
 373
 374 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 375 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000E00
 376
 377 #define CONFIG_SYS_OR1_PRELIM   (0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM ) /* map 256 MB */
 378 #define CONFIG_SYS_BR1_PRELIM   ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 379
 380 /* RPXLITE mem setting */
 381 #define CONFIG_SYS_BR3_PRELIM   0xFA400001              /* FPGA */
 382 #define CONFIG_SYS_OR3_PRELIM   0xFFFF8910
 383
 384 #define CONFIG_SYS_BR4_PRELIM   0xFA000401              /* NVRAM&SRAM */
 385 #define CONFIG_SYS_OR4_PRELIM   0xFFFE0970
 386
 387 /*
 388  * Memory Periodic Timer Prescaler
 389  */
 390
 391 /* periodic timer for refresh */
 392 #define CONFIG_SYS_MAMR_PTA     20
 393
 394 /*
 395  * Refresh clock Prescalar
 396  */
 397 #define CONFIG_SYS_MPTPR        MPTPR_PTP_DIV2
 398
 399 /*
 400  * MAMR settings for SDRAM
 401  */
 402
 403 /* 9 column SDRAM */
 404 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 405                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 406                          MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)
 407
 408 /*
 409  * BCSRx
 410  *
 411  * Board Status and Control Registers
 412  *
 413  */
 414
 415 #define BCSR0 0xFA400000
 416 #define BCSR1 0xFA400001
 417 #define BCSR2 0xFA400002
 418 #define BCSR3 0xFA400003
 419
 420 #define BCSR0_ENMONXCVR 0x01    /* Monitor XVCR Control */
 421 #define BCSR0_ENNVRAM   0x02    /* CS4# Control */
 422 #define BCSR0_LED5      0x04    /* LED5 control 0='on' 1='off' */
 423 #define BCSR0_LED4      0x08    /* LED4 control 0='on' 1='off' */
 424 #define BCSR0_FULLDPLX  0x10    /* Ethernet XCVR Control */
 425 #define BCSR0_COLTEST   0x20
 426 #define BCSR0_ETHLPBK   0x40
 427 #define BCSR0_ETHEN     0x80
 428
 429 #define BCSR1_PCVCTL7   0x01    /* PC Slot B Control */
 430 #define BCSR1_PCVCTL6   0x02
 431 #define BCSR1_PCVCTL5   0x04
 432 #define BCSR1_PCVCTL4   0x08
 433 #define BCSR1_IPB5SEL   0x10
 434
 435 #define BCSR2_ENPA5HDR  0x08    /* USB Control */
 436 #define BCSR2_ENUSBCLK  0x10
 437 #define BCSR2_USBPWREN  0x20
 438 #define BCSR2_USBSPD    0x40
 439 #define BCSR2_USBSUSP   0x80
 440
 441 #define BCSR3_BWRTC     0x01    /* Real Time Clock Battery */
 442 #define BCSR3_BWNVR     0x02    /* NVRAM Battery */
 443 #define BCSR3_RDY_BSY   0x04    /* Flash Operation */
 444 #define BCSR3_RPXL      0x08    /* Reserved (reads back '1') */
 445 #define BCSR3_D27       0x10    /* Dip Switch settings */
 446 #define BCSR3_D26       0x20
 447 #define BCSR3_D25       0x40
 448 #define BCSR3_D24       0x80
 449
 450 #endif  /* __CONFIG_H */