include/configs/r0p7734.h

   1 /*
   2  * Configuation settings for the Renesas Solutions r0p7734 board
   3  *
   4  * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __R0P7734_H
  10 #define __R0P7734_H
  11
  12 #undef DEBUG
  13 #define CONFIG_CPU_SH7734       1
  14 #define CONFIG_R0P7734          1
  15 #define CONFIG_400MHZ_MODE      1
  16 /* #define CONFIG_533MHZ_MODE   1 */
  17
  18 #define CONFIG_BOARD_LATE_INIT
  19 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000
  20
  21 #define CONFIG_CMD_FLASH
  22 #define CONFIG_CMD_MEMORY
  23 #define CONFIG_CMD_PING
  24 #define CONFIG_CMD_MII
  25 #define CONFIG_CMD_NFS
  26 #define CONFIG_CMD_SDRAM
  27 #define CONFIG_CMD_ENV
  28 #define CONFIG_CMD_SAVEENV
  29
  30 #define CONFIG_BAUDRATE         115200
  31 #define CONFIG_BOOTDELAY        3
  32 #define CONFIG_BOOTARGS         "console=ttySC3,115200"
  33
  34 #define CONFIG_VERSION_VARIABLE
  35 #undef  CONFIG_SHOW_BOOT_PROGRESS
  36
  37 /* Ether */
  38 #define CONFIG_SH_ETHER 1
  39 #define CONFIG_SH_ETHER_USE_PORT (0)
  40 #define CONFIG_SH_ETHER_PHY_ADDR (0x0)
  41 #define CONFIG_PHYLIB
  42 #define CONFIG_PHY_SMSC 1
  43 #define CONFIG_BITBANGMII
  44 #define CONFIG_BITBANGMII_MULTI
  45 #define CONFIG_SH_ETHER_SH7734_MII (0x00) /* MII */
  46 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
  47 #ifndef CONFIG_SH_ETHER
  48 # define CONFIG_SMC911X
  49 # define CONFIG_SMC911X_16_BIT
  50 # define CONFIG_SMC911X_BASE (0x84000000)
  51 #endif
  52
  53
  54 /* I2C */
  55 #define CONFIG_CMD_I2C
  56 #define CONFIG_SH_SH7734_I2C    1
  57 #define CONFIG_HARD_I2C                 1
  58 #define CONFIG_I2C_MULTI_BUS    1
  59 #define CONFIG_SYS_MAX_I2C_BUS  2
  60 #define CONFIG_SYS_I2C_MODULE   0
  61 #define CONFIG_SYS_I2C_SPEED    100000 /* 100 kHz */
  62 #define CONFIG_SYS_I2C_SLAVE    0x50
  63 #define CONFIG_SH_I2C_DATA_HIGH 4
  64 #define CONFIG_SH_I2C_DATA_LOW  5
  65 #define CONFIG_SH_I2C_CLOCK             500000000
  66 #define CONFIG_SH_I2C_BASE0             0xFFC70000
  67 #define CONFIG_SH_I2C_BASE1             0xFFC7100
  68
  69 /* undef to save memory */
  70 #define CONFIG_SYS_LONGHELP
  71 /* Monitor Command Prompt */
  72 /* Buffer size for input from the Console */
  73 #define CONFIG_SYS_CBSIZE               256
  74 /* Buffer size for Console output */
  75 #define CONFIG_SYS_PBSIZE               256
  76 /* max args accepted for monitor commands */
  77 #define CONFIG_SYS_MAXARGS              16
  78 /* Buffer size for Boot Arguments passed to kernel */
  79 #define CONFIG_SYS_BARGSIZE     512
  80 /* List of legal baudrate settings for this board */
  81 #define CONFIG_SYS_BAUDRATE_TABLE       { 115200 }
  82
  83 /* SCIF */
  84 #define CONFIG_SCIF_CONSOLE     1
  85 #define CONFIG_SCIF                     1
  86 #define CONFIG_CONS_SCIF3       1
  87
  88 /* Suppress display of console information at boot */
  89 #undef  CONFIG_SYS_CONSOLE_INFO_QUIET
  90 #undef  CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
  91 #undef  CONFIG_SYS_CONSOLE_ENV_OVERWRITE
  92
  93 /* SDRAM */
  94 #define CONFIG_SYS_SDRAM_BASE   (0x88000000)
  95 #define CONFIG_SYS_SDRAM_SIZE   (128 * 1024 * 1024)
  96 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
  97
  98 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
  99 #define CONFIG_SYS_MEMTEST_END   (CONFIG_SYS_MEMTEST_START + 100 * 1024 * 1024)
 100 /* Enable alternate, more extensive, memory test */
 101 #undef  CONFIG_SYS_ALT_MEMTEST
 102 /* Scratch address used by the alternate memory test */
 103 #undef  CONFIG_SYS_MEMTEST_SCRATCH
 104
 105 /* Enable temporary baudrate change while serial download */
 106 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE
 107
 108 /* FLASH */
 109 #define CONFIG_FLASH_CFI_DRIVER 1
 110 #define CONFIG_SYS_FLASH_CFI
 111 #undef  CONFIG_SYS_FLASH_QUIET_TEST
 112 #define CONFIG_SYS_FLASH_EMPTY_INFO
 113 #define CONFIG_SYS_FLASH_BASE   (0xA0000000)
 114 #define CONFIG_SYS_MAX_FLASH_SECT       512
 115
 116 /* if you use all NOR Flash , you change dip-switch. Please see Manual. */
 117 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 118 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 119
 120 /* Timeout for Flash erase operations (in ms) */
 121 #define CONFIG_SYS_FLASH_ERASE_TOUT     (3 * 1000)
 122 /* Timeout for Flash write operations (in ms) */
 123 #define CONFIG_SYS_FLASH_WRITE_TOUT     (3 * 1000)
 124 /* Timeout for Flash set sector lock bit operations (in ms) */
 125 #define CONFIG_SYS_FLASH_LOCK_TOUT      (3 * 1000)
 126 /* Timeout for Flash clear lock bit operations (in ms) */
 127 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    (3 * 1000)
 128
 129 /*
 130  * Use hardware flash sectors protection instead
 131  * of U-Boot software protection
 132  */
 133 #undef  CONFIG_SYS_FLASH_PROTECTION
 134 #undef  CONFIG_SYS_DIRECT_FLASH_TFTP
 135
 136 /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
 137 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
 138 /* Monitor size */
 139 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024)
 140 /* Size of DRAM reserved for malloc() use */
 141 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)
 142 #define CONFIG_SYS_BOOTMAPSZ    (8 * 1024 * 1024)
 143
 144 /* ENV setting */
 145 #define CONFIG_ENV_IS_IN_FLASH
 146 #define CONFIG_ENV_OVERWRITE    1
 147 #define CONFIG_ENV_SECT_SIZE    (128 * 1024)
 148 #define CONFIG_ENV_SIZE         (CONFIG_ENV_SECT_SIZE)
 149 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
 150 /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
 151 #define CONFIG_ENV_OFFSET       (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
 152 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SECT_SIZE)
 153
 154 /* Board Clock */
 155 #if defined(CONFIG_400MHZ_MODE)
 156 #define CONFIG_SYS_CLK_FREQ 50000000
 157 #else
 158 #define CONFIG_SYS_CLK_FREQ 44444444
 159 #endif
 160 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
 161 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
 162 #define CONFIG_SYS_TMU_CLK_DIV      4
 163
 164 #endif  /* __R0P7734_H */