include/configs/r2dplus.h

   1 #ifndef __CONFIG_H
   2 #define __CONFIG_H
   3
   4 #undef DEBUG
   5
   6 #define CONFIG_CPU_SH7751       1
   7 #define CONFIG_CPU_SH_TYPE_R    1
   8 #define CONFIG_R2DPLUS          1
   9 #define __LITTLE_ENDIAN__       1
  10
  11 /*
  12  * Command line configuration.
  13  */
  14 #define CONFIG_CMD_CACHE
  15 #define CONFIG_CMD_PCI
  16 #define CONFIG_CMD_PING
  17 #define CONFIG_CMD_IDE
  18 #define CONFIG_CMD_EXT2
  19 #define CONFIG_DOS_PARTITION
  20 #define CONFIG_CMD_SH_ZIMAGEBOOT
  21
  22 /* SCIF */
  23 #define CONFIG_SCIF_CONSOLE     1
  24 #define CONFIG_BAUDRATE         115200
  25 #define CONFIG_CONS_SCIF1       1
  26 #define CONFIG_BOARD_LATE_INIT
  27
  28 #define CONFIG_BOOTDELAY        -1
  29 #define CONFIG_BOOTARGS         "console=ttySC0,115200"
  30 #define CONFIG_ENV_OVERWRITE    1
  31
  32 /* SDRAM */
  33 #define CONFIG_SYS_SDRAM_BASE           (0x8C000000)
  34 #define CONFIG_SYS_SDRAM_SIZE           (0x04000000)
  35
  36 #define CONFIG_SYS_TEXT_BASE    0x0FFC0000
  37 #define CONFIG_SYS_LONGHELP
  38 #define CONFIG_SYS_CBSIZE               256
  39 #define CONFIG_SYS_PBSIZE               256
  40 #define CONFIG_SYS_MAXARGS              16
  41 #define CONFIG_SYS_BARGSIZE             512
  42
  43 #define CONFIG_SYS_MEMTEST_START        (CONFIG_SYS_SDRAM_BASE)
  44 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_TEXT_BASE - 0x100000)
  45
  46 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
  47 /* Address of u-boot image in Flash */
  48 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
  49 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)
  50 /* Size of DRAM reserved for malloc() use */
  51 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)
  52 #define CONFIG_SYS_BOOTMAPSZ            (8 * 1024 * 1024)
  53
  54 /*
  55  * NOR Flash ( Spantion S29GL256P )
  56  */
  57 #define CONFIG_SYS_FLASH_CFI
  58 #define CONFIG_FLASH_CFI_DRIVER
  59 #define CONFIG_SYS_FLASH_BASE           (0xA0000000)
  60 #define CONFIG_SYS_MAX_FLASH_BANKS (1)
  61 #define CONFIG_SYS_MAX_FLASH_SECT  256
  62 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
  63
  64 #define CONFIG_ENV_IS_IN_FLASH
  65 #define CONFIG_ENV_SECT_SIZE    0x40000
  66 #define CONFIG_ENV_SIZE        (CONFIG_ENV_SECT_SIZE)
  67 #define CONFIG_ENV_ADDR        (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
  68
  69 /*
  70  * SuperH Clock setting
  71  */
  72 #define CONFIG_SYS_CLK_FREQ     60000000
  73 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
  74 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
  75 #define CONFIG_SYS_TMU_CLK_DIV          4
  76 #define CONFIG_SYS_PLL_SETTLING_TIME    100/* in us */
  77
  78 /*
  79  * IDE support
  80  */
  81 #define CONFIG_IDE_RESET        1
  82 #define CONFIG_SYS_PIO_MODE             1
  83 #define CONFIG_SYS_IDE_MAXBUS           1 /* IDE bus */
  84 #define CONFIG_SYS_IDE_MAXDEVICE        1
  85 #define CONFIG_SYS_ATA_BASE_ADDR        0xb4000000
  86 #define CONFIG_SYS_ATA_STRIDE           2 /* 1bit shift */
  87 #define CONFIG_SYS_ATA_DATA_OFFSET      0x1000  /* data reg offset */
  88 #define CONFIG_SYS_ATA_REG_OFFSET       0x1000  /* reg offset */
  89 #define CONFIG_SYS_ATA_ALT_OFFSET       0x800   /* alternate register offset */
  90 #define CONFIG_IDE_SWAP_IO
  91
  92 /*
  93  * SuperH PCI Bridge Configration
  94  */
  95 #define CONFIG_PCI
  96 #define CONFIG_SH4_PCI
  97 #define CONFIG_SH7751_PCI
  98 #define CONFIG_PCI_PNP
  99 #define CONFIG_PCI_SCAN_SHOW    1
 100 #define __io
 101 #define __mem_pci
 102
 103 #define CONFIG_PCI_MEM_BUS      0xFD000000      /* Memory space base addr */
 104 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
 105 #define CONFIG_PCI_MEM_SIZE     0x01000000      /* Size of Memory window */
 106 #define CONFIG_PCI_IO_BUS       0xFE240000      /* IO space base address */
 107 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
 108 #define CONFIG_PCI_IO_SIZE      0x00040000      /* Size of IO window */
 109 #define CONFIG_PCI_SYS_BUS      (CONFIG_SYS_SDRAM_BASE & 0x1fffffff)
 110 #define CONFIG_PCI_SYS_PHYS     (CONFIG_SYS_SDRAM_BASE & 0x1fffffff)
 111 #define CONFIG_PCI_SYS_SIZE     CONFIG_SYS_SDRAM_SIZE
 112
 113 /*
 114  * Network device (RTL8139) support
 115  */
 116 #define CONFIG_RTL8139
 117
 118 #endif /* __CONFIG_H */